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Thu, 12 Feb 2026 02:32:53 -0800 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , , , , Gal Pressman , Moshe Shemesh , Shay Drory Subject: [PATCH net 1/6] net/mlx5: Fix multiport device check over light SFs Date: Thu, 12 Feb 2026 12:32:12 +0200 Message-ID: <20260212103217.1752943-2-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260212103217.1752943-1-tariqt@nvidia.com> References: <20260212103217.1752943-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD75:EE_|CH1PPF7A6EE32B1:EE_ X-MS-Office365-Filtering-Correlation-Id: f1f187f3-8c68-4ba4-ba40-08de6a221dba X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?FoFKNEAL503/u03YPea3CcWwQVGDRMLm37yEb2ztBW2NXMSkmwu9V/ME80jK?= =?us-ascii?Q?xuTsdJcCVyKdlyG29PPjRSZ1ddyGXIw3AA6zv2QO9hsusLO4Q4ad4/QeZ6B7?= =?us-ascii?Q?Uc6d2mni9vBs1NKjWzVvZvK0iKoJfc9GVyHhYcSTZQGozaHe75fg5XnL3XnK?= =?us-ascii?Q?SOGmNagNgcG0YmifLR9k/tVQLSqk78XK3RTqZ3NLKesTckusxrtzv+k/1FrM?= =?us-ascii?Q?EbyNcS16+qs7Hd4YVQEx73UTDcnunnS8Ls/+0s38pybYiNGkvJAXTpMLyE4U?= =?us-ascii?Q?EmX0J4wiXzfh3C4vZ1cyjbGATS9uZ7xuz224EMWG8AoRQQ+HbBa9jp0Ysqpg?= =?us-ascii?Q?jr3qNfs1DtXL1DvBFLdGTr03SMnbxeu6nVPANkoAf9hMmGyBSMtweVmLoe1c?= =?us-ascii?Q?X2XmHK3jses0wZLitPRyL8XEuGxy6SYXeMFXdlrKydUr35Wrs5D7xW5LsRaP?= =?us-ascii?Q?+fD3S2Sr1ItrF7YOCgFlXnoNxosW2sqkDqM5Wz++uyLLhIp7UwkZ5nAJ/Qlv?= =?us-ascii?Q?NwcYU2WYd/KS1kN7KUbbYaZKLq9rWkzP6e/rejWprU+zOczBpoWqHCr5LMJN?= =?us-ascii?Q?toZ6Ioi221VtTaHTaNF51WKfemAUdj4ow01qWP8kKjOvZ6XHLAAXcckSQcYB?= =?us-ascii?Q?ahwsmTubFFxV4YKUBXID3vpPySNeZAzry+XEyUdVU/rxtfaGi9HIWC8xrmu+?= =?us-ascii?Q?RDGTdzdF+ncmo+7k6ddzRREZBQ/isp9jWG6yemmTDlbiBmEwzEV7B+5l71mO?= =?us-ascii?Q?DV34u4qi7yYctM8TEwg00DtmJ+2Mreb2KeIwQLuzQ+3NM5PImp1bXxONR/bv?= =?us-ascii?Q?Vd9CtSMQQyy9EuYvyp81xfvxk12y874xeLnBgWHxLGsLfo39UMJrcyPa5kCw?= =?us-ascii?Q?dTypsWSA5XLk/uSERlr3IicoNBZKRJoqhBe10xdW4ej3j5IJ0+W7iFdw2Gu3?= =?us-ascii?Q?UW/DAfEtAjokbbZm3puTXcm4FxcA9WSYjwmP8XR5W9zX4/H3vrPdTLupz2E2?= =?us-ascii?Q?/B/9kImqaHXHCXnKBf0HkDAIXrS8aTAs8iJIbFsh9o7Z3xMuwvklfa15gOTI?= =?us-ascii?Q?zD2XcOQ+FWr3wbTQ4wQhCdVLIdayaPTfWcTv/VJnAXFo8BXLxW120uk+WaTk?= =?us-ascii?Q?E9xrvItfR3hBOyNHiGluGteSCbN+RrSNA+B9/TCzBftvNx004hTx60EbtiuB?= =?us-ascii?Q?0ZKKJjNFbOcX7/+wdoYFBFG87gbE5+cQOUgUzHxOoXA0a6jHPUpjqFyNFm9E?= =?us-ascii?Q?3zuE/+62/zSguclKy+x9OkiE5ezNu9wAYkv+Nhixy+wI0w7ef28YgshQfrYY?= =?us-ascii?Q?JgWRM9gKfQufkFIqM8QfRbrUmJCcBw4IRDzJt8j/fIrmhroRX5pmDYqNfiJG?= =?us-ascii?Q?XIIkF4xc2vHZPvc/cBojxfYK2Xg4wxeH5H1qZBe4umgIXP57FOUO2MHnoVHe?= =?us-ascii?Q?bysL+b043m0VvpjqpmzR+8ZiqQezam6pwe79AoQXuGvUkajyNZdcdnNeNrVt?= =?us-ascii?Q?HtkoDU96ETLcX0xn/1Lzqp3p0oCBIPFFzLjtHy45V10YZEeK0ZKeE6YDQcSE?= =?us-ascii?Q?bpK27fU/+uVAcj0Iu3PXJB03UzvvrHU823giN4ju6QImTKoRXfVkhdviZLcT?= =?us-ascii?Q?wn/pU2i7397G7lm/W7FNwURp2T5+zVj99j+5KJ9LrEzGua1cngWU6pIgn/ZA?= =?us-ascii?Q?/cSKOw=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: VU7ENqFZVodcs+vKKhoCw34kEp7o+iCt9uSF+Zx08cyJayfgSPZjzIX45n+YqiXXa1b7bkRSHIG1D88OPzU7SGmX7K1ttj/upvRKRKfKq1JkG9KGAi7qi4aXiul79eisNQAMlgPLOicrcLTT7QKRZlOyNM94CSJHO0ZY6bjDh2GfmdwCqEQ90cBTOVEO5ndpTbqt9bldy/Fxkb6mrPq9n7rlQvk5C2VWKwb77hYnz81PpQdHorRdox7deV/1lsYuut8beNDSkSrTPxDuvrKW4MHQ3kgU39m3KMAouTwdo09P/ciJAJFYO4r+Rm2XkI7uMBLNIhTLu/OG3ZGcncwbpIeraSTAzNM/MspaiEfvYiY9WV2DKze0BVHu90H7L2MdnGTMv7Gmu4myW8zYW8+vwqua+edgBhWYXSQCc4gGfMPAxuTrDlTevlZVk2wVI3X4 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Feb 2026 10:33:09.1597 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f1f187f3-8c68-4ba4-ba40-08de6a221dba X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD75.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH1PPF7A6EE32B1 Content-Type: text/plain; charset="utf-8" From: Shay Drory Driver is using num_vhca_ports capability to distinguish between multiport master device and multiport slave device. num_vhca_ports is a capability the driver sets according to the MAX num_vhca_ports capability reported by FW. On the other hand, light SFs doesn't set the above capbility. This leads to wrong results whenever light SFs is checking whether he is a multiport master or slave. Therefore, use the MAX capability to distinguish between master and slave devices. Fixes: e71383fb9cd1 ("net/mlx5: Light probe local SFs") Signed-off-by: Shay Drory Reviewed-by: Moshe Shemesh Signed-off-by: Tariq Toukan Reviewed-by: Jacob Keller --- include/linux/mlx5/driver.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h index 1c54aa6f74fb..1967d1c79139 100644 --- a/include/linux/mlx5/driver.h +++ b/include/linux/mlx5/driver.h @@ -1281,12 +1281,12 @@ static inline bool mlx5_rl_is_supported(struct mlx5= _core_dev *dev) static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev) { return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) && - MLX5_CAP_GEN(dev, num_vhca_ports) <=3D 1; + MLX5_CAP_GEN_MAX(dev, num_vhca_ports) <=3D 1; } =20 static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev) { - return MLX5_CAP_GEN(dev, num_vhca_ports) > 1; + return MLX5_CAP_GEN_MAX(dev, num_vhca_ports) > 1; } =20 static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev) --=20 2.44.0 From nobody Thu Apr 2 18:47:37 2026 Received: from PH0PR06CU001.outbound.protection.outlook.com (mail-westus3azon11011045.outbound.protection.outlook.com [40.107.208.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8220E2EA72A; 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , , , , Gal Pressman , Moshe Shemesh , Jianbo Liu Subject: [PATCH net 2/6] net/mlx5: Fix misidentification of write combining CQE during poll loop Date: Thu, 12 Feb 2026 12:32:13 +0200 Message-ID: <20260212103217.1752943-3-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260212103217.1752943-1-tariqt@nvidia.com> References: <20260212103217.1752943-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE37:EE_|IA1PR12MB6018:EE_ X-MS-Office365-Filtering-Correlation-Id: 0ef2ba0b-1ab0-488b-c767-08de6a2221dc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?fe88+JyhI/fWw10CnvHy9SZ94aKK4ieEUcXCcgG52zV24htYB8nJDPfikHVo?= =?us-ascii?Q?JhqB239pVt79+zv99dHW1hJ36t9nUQJprIq5sh3WjSl8gEucbBUabHUsd8fo?= =?us-ascii?Q?Vx3zvE66uqW4uF/BrkVvArBbSzlgX1iUXwgjzLgn6j7L9brSFBLASEN//kGD?= =?us-ascii?Q?A+FIR+ZCGPJvcYCggQJ+wa6nJQWc5maS3mZByKihguzp/g8DXgURYjHMyxQO?= =?us-ascii?Q?D9BnKSZT5DdW+vwJS3fka3nV08J6b2FU46neTf5b70XMKnQ8A7rIwn1Lqexy?= =?us-ascii?Q?T9x8NOOaz9wvZ0yo85BTnSPwNCls1j8Dh/Asi+Xq2gmpgIrH2u8zJ61OZgrM?= =?us-ascii?Q?rfHqwGhLN3ZTQuZDdrM3OQjq5Fba3SiOljhpjHCqJ6eZC81YOn/Woc+nKMox?= =?us-ascii?Q?3DVLsI00zcMxGkcTk/P5h72Y0d0C1n9Ux7j0Khc0eJPqp7dQ4AfqmLuPe86j?= =?us-ascii?Q?ieMtLM7MFTwGa5HchIaFuCyFxP9p1rurFnnUVyCMpPW/jtHIz3XKof9eH3tV?= =?us-ascii?Q?gFSIAE69TugkBvVMUNQusDDP3VPt2PRUo8jAlHnTlGL4m9p/wmJXKMmcJfVO?= =?us-ascii?Q?rk+lbG1v7XcHTjFpU2dfOeWfooPlcXKQ6KY15rklUwTQpfU6fFACXsFxEJYo?= =?us-ascii?Q?40wZK24gMw5zrgWcF+wTqhWhul9EdBJqMK6PnkUN6ISfF67JmcWh43JNBmsZ?= =?us-ascii?Q?mVFPs4LElMmuNBU4hw8aotHkTQfMRh2tFoGhBtcnNOpKUp9HLDSpa9rDJCCk?= =?us-ascii?Q?EXVlwSptC7lGn8Y2mR5CCTteNREX/9bknxzs8o42Z7VLVJCPVIuvVCk3etRq?= =?us-ascii?Q?9f9IF72Ol2wtLKb9WRGd048H0ML8QfYw5YmN69Afyl9p1wPOC8aolzpQkq79?= =?us-ascii?Q?EzLIiJlnOEM8MINvjQC64vgGl5vzDKS13FuBfxLG9A9KzkI6MEUWrp7zmRZK?= =?us-ascii?Q?aHLM3o5Lmmy/73IOnvSTvJFLbJb2cD92dPYwwfhuSlKIa1vvAN0nrq++lbkg?= =?us-ascii?Q?wz5fsgJh9DNHTDAq/PY4+eD9SdQf4pc78XBQwsmqs9SM2o06EYCbqtI+6Eph?= =?us-ascii?Q?XJXJYSa/KcCiZKOEuvAWpEea9LB+5j88Wmh60hYcR5n9JH3SOCdx9R+ujLGe?= =?us-ascii?Q?qPnHJmmgmmmmzDifWDpWuKDj1S7eyfz0ACW8mbKteBDyIaNBgDVWQpa2KUup?= =?us-ascii?Q?MzJJCtojgWn2CJ/l+lNDfVLinMfpzm+YCTwRxv+QKjXhjJomFaOsyQSHz8wu?= =?us-ascii?Q?7H507xMo4NOaYieR9cRoDz5fR4iOtpF+KUBBQ1MWOvpCJd4xBD6GrkT8FBeX?= =?us-ascii?Q?2Cy39KxMfuEgl7j+IUmH3bdpKTSipqVqq87HkCZs7XOGes7ly2aJUzK0bRVc?= =?us-ascii?Q?FlhGBpuq5lBAqy0tCzJJ48Kbwfl81A26A6hRu6cWWnG4IPFidEDtiisAo02/?= =?us-ascii?Q?KZkxGCibjcemBLS7VsJUDZ85/Y4390xhAbsjKhUafXoX/zgI7uti6e4uNsot?= =?us-ascii?Q?XPrIj5MDsZpND2XU+olCp4U4iJwB1x7JaCqCsHyPzRd9TP5XC99ZoA0D89EF?= =?us-ascii?Q?EtGqCFqbXmr9zPZzzF4S0UWMWZ9cuZO15Jonyt3DkREgkkp4Gd9YWc+Rl62K?= =?us-ascii?Q?y2qnAg+E1FZdAVPFP8rr+ZDgedU3zkSwKkxPL9Pl3S+a7UkNXb3pl34zVAOh?= =?us-ascii?Q?Tt2VHQ=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: E4MY2jNHXrx2rb5wkjFWw+d2mZUPLy8xgwC7Ns4GjRs2LhRTB8qxb6yMxGJjQcJasY+4HEpxrKx8KG42Ucz6q8k8z+R2laF+Z/3UbNOXYfzFFfCycxW81M3lx6RS2IO56h6vUuk+NYALrIgBGyWQ/oQWWTqMitew9mpiqkGSD4bU2uyy9HTALjBp/n1529LaAOjtNoR8z0AcEAx3HMq8nSL+0RhUaeKcknWgXn2dX3kdRbT957fLDTV2NEkYADXokQzRKTPJGj0GYPScXC9Xt9r3pTi0NY/qSI2+JdFSZhFuYVWEBXz0Qdorr/2k6O3uUP3GXOAETZuG/wKQE/vcqd01OW4vWttpXXnoI9scKxFv3TTrLTJ84k857whtd1I9qRiZyt/iEvqeX4m+LrYYAGVJI7aH+NY43OTPy39TBMRcO5rb7nGQXevu8Ji3Bmds X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Feb 2026 10:33:16.1287 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0ef2ba0b-1ab0-488b-c767-08de6a2221dc X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE37.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6018 Content-Type: text/plain; charset="utf-8" From: Gal Pressman The write combining completion poll loop uses usleep_range() which can sleep much longer than requested due to scheduler latency. Under load, we witnessed a 20ms+ delay until the process was rescheduled, causing the jiffies based timeout to expire while the thread is sleeping. The original do-while loop structure (poll, sleep, check timeout) would exit without a final poll when waking after timeout, missing a CQE that arrived during sleep. Restructure the loop by moving the poll into the while condition, ensuring we always poll after sleeping, catching CQEs that arrived during that time. While at it, remove the redundant 'err' assignment. Fixes: d98995b4bf98 ("net/mlx5: Reimplement write combining test") Signed-off-by: Gal Pressman Reviewed-by: Jianbo Liu Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/wc.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/wc.c b/drivers/net/eth= ernet/mellanox/mlx5/core/wc.c index 815a7c97d6b0..29db15c4b978 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/wc.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/wc.c @@ -390,12 +390,10 @@ static void mlx5_core_test_wc(struct mlx5_core_dev *m= dev) mlx5_wc_post_nop(sq, &offset, true); =20 expires =3D jiffies + TEST_WC_POLLING_MAX_TIME_JIFFIES; - do { - err =3D mlx5_wc_poll_cq(sq); - if (err) - usleep_range(2, 10); - } while (mdev->wc_state =3D=3D MLX5_WC_STATE_UNINITIALIZED && - time_is_after_jiffies(expires)); + while ((mlx5_wc_poll_cq(sq), + mdev->wc_state =3D=3D MLX5_WC_STATE_UNINITIALIZED) && + time_is_after_jiffies(expires)) + usleep_range(2, 10); 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Thu, 12 Feb 2026 02:33:02 -0800 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , , , , Gal Pressman , Moshe Shemesh , Jianbo Liu Subject: [PATCH net 3/6] net/mlx5e: Fix misidentification of ASO CQE during poll loop Date: Thu, 12 Feb 2026 12:32:14 +0200 Message-ID: <20260212103217.1752943-4-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260212103217.1752943-1-tariqt@nvidia.com> References: <20260212103217.1752943-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE36:EE_|PH7PR12MB8053:EE_ X-MS-Office365-Filtering-Correlation-Id: 7f8f616f-edea-4f2a-5124-08de6a22262b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|376014|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?Yn5Yit0QR5Yt+JZUMkVtQsGeJCaCcHT8iwcZRqM1KimXurWILjPzXQJEZhiT?= =?us-ascii?Q?FSnOlwAKq+6LYkETfPgwr4oK30aR6GmVmcicIiyIFWIei27Wwu6DMRZi7ure?= =?us-ascii?Q?7uPlqMVO0fU3JK+cS0T6iBTir7k9pNeVI00FKvhmlAZDQwIrnVIjy1hur0Z8?= =?us-ascii?Q?LDEELs2XWvdaY6R1BMdboUTl22PNFwfAhQVtnc4y7cKVXUXfFglSj1o0t7tX?= =?us-ascii?Q?Bx6DW/bSHze8ZB3RsmUVvWOyI840mfdlm16CXrNvq8lpUMpB05QzBB4T8E7l?= =?us-ascii?Q?F7Fk9NV8v3QsTwTT4vLrNAYJx444o0CJOTVRG3RHYJ4Sa0leEnCNrIt+TB06?= =?us-ascii?Q?csyl9rb2xT6M9wJL4sKbJbj8SHjYAC7JDJMsA3vljW0ynC7Yllxm4Zku4Y57?= =?us-ascii?Q?swv9e9fA4sQJ4uIIh7M/2kVRv23Xov2FAz/iBnn2vJEo7dGRJU0pZZN40R/W?= =?us-ascii?Q?Zxf/L/YNCbS3HbJ1l/9zMtSeb1QLOtdX2u2FNra/t6hJnru/c8AyxCvZrk/l?= =?us-ascii?Q?bXRVDPxhw9ZEUb4mqZWKQtioEMOOa/8pQok6mYz+tKRWNaMYROFkLXtPgdT+?= =?us-ascii?Q?QpIJWFaGgJR26kq7R+ZGNgbKP0Zc3XzEe5DniV97rE31NG6SHpkhR8uP/hjd?= =?us-ascii?Q?34ug0u5TAh/8QXCNdVfXIIehUKb178Px+ZkeeN9GQITi9uyHu+eQTJ1WoWxx?= =?us-ascii?Q?RR7B28FkwOEj28/32YA8/lipjOoIUqwSQu888h2UK9R51FyHU48BXP20LncQ?= =?us-ascii?Q?HIhH8AHiiLPH0Kmc2nNyPhiLsL7Y2XGHuOXd0VCDRu/kMZpsrWv4yZn2OmSF?= =?us-ascii?Q?mxo2T+QjW1H/EyLPeXvZSNTuZJnx9SeOBqnq8cbhVwQSVtHuhLuU5HDr0j7N?= =?us-ascii?Q?Rsb9V2IQk/Spz0/lCFMKMSfxtkfaPeR8nTrchlT2L/fRW58HH7SYDpsgLp0U?= =?us-ascii?Q?wVri+sj4c5bSeYqiAlJZkV+OzB4GepB79dEslRE1GFTt5z8ZCL++ECNvdx18?= =?us-ascii?Q?hT8EbAfvnB+i56hA4B8buAHMWRAxllmjLEWuMWM9RUVLMI8DC42FVoDEUPWT?= =?us-ascii?Q?EY564BPNeG3eIo8GsfxpMpn8CIY7juQBwhWyT+EQYvNPCjKH8iH56O9H7Nqd?= =?us-ascii?Q?w2xN89pmuQG4/StqFiDr8LtLpOBxaQ2spiCrK0FVMykf0wc3+u2HLq7UQwzM?= =?us-ascii?Q?H59OAS9Voezll/1GgUutkCiufkW0X/hKNZVqcRpogTBx4TBXNyzQp2Flb1Si?= =?us-ascii?Q?umpEIS1Q0s5GpVM7407RM9ajeUKXyZ7cPJygigrwQ9g6i1PMz8HpfVSFzM5m?= =?us-ascii?Q?qZWOT4YVRbiJus8/9poyImcuaSVRhNTJ3tQrvjm3lSIlXww2RE7+rqc/WAkk?= =?us-ascii?Q?QGj2ErbY6CV5zaFqq64I3VNY2Z4GTRPI42CFGq3vLozrS9WsKZPwbV7OluGa?= =?us-ascii?Q?LgH78udMSZzQoZX+kjYvWVviRXN7SZRnyvIOjXOEoNUZhht/OCU3+HbiZz9R?= =?us-ascii?Q?ox42jt0WvsMoh3Ck2TljD8meZXgrl9gOIIX0uH49fUAkYD0azinI/E718Nsg?= =?us-ascii?Q?2//mBYB50kO7QxGUAzjj/IRNQB1MobhRdTxJMzF4orZdopGqNvbjDtEZ5zpW?= =?us-ascii?Q?p8jSyz6QySW1V4L2MaZjIb7760/76jKaXyIbUa7/p9xf2t1WlN9ZODcqTEgs?= =?us-ascii?Q?Bi/TeQ=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(376014)(1800799024);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: vyDn0ia548rNtIZPZKUNd38BKuFWJKwsrCjBWpffsfoZJpRqTf5BrqzffLH1SsNd8vRdBjuoroDgJdpyUsGsq7MeGT8LeZeXmAB5HLa8wIdnhboZ+KKLqSc2xIfplbeFJCWHljdoeqbev4pOMogORVnJgpuR0Tfy+ejfoICraszyvdlfB5GqT335/TrgkkcgRYwToNDiN9ZnzqG/eQbbYU5/fk1TROJjZ+UeEcTQS7JkcAQb8/SXkwtL/Oqx5r0gRQ89us1/wCP1aGfWzriN+Nd3lO9epOfK7lSBb5VatH8fS4WXFUEnhTLLAoFM3cJm5q+kYoPajZQlrLuJKWiVdepd/JA0bE7yvrIFlCbQ80YFSoZR9D0POao946qd4zLrsawDNMsMT9KU2D2RtL+c+O3Ie3cW7zWI2i3adCK9eKzju0Syoy/gMxnM+ZFtHODU X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Feb 2026 10:33:23.3829 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7f8f616f-edea-4f2a-5124-08de6a22262b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE36.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB8053 Content-Type: text/plain; charset="utf-8" From: Gal Pressman The ASO completion poll loop uses usleep_range() which can sleep much longer than requested due to scheduler latency. Under load, we witnessed a 20ms+ delay until the process was rescheduled, causing the jiffies based timeout to expire while the thread is sleeping. The original do-while loop structure (poll, sleep, check timeout) would exit without a final poll when waking after timeout, missing a CQE that arrived during sleep. Restructure the loop by moving the poll into the while condition, ensuring we always poll after sleeping, catching CQEs that arrived during that time. Fixes: 739cfa34518e ("net/mlx5: Make ASO poll CQ usable in atomic context") Fixes: 7e3fce82d945 ("net/mlx5e: Overcome slow response for first macsec AS= O WQE") Signed-off-by: Gal Pressman Reviewed-by: Jianbo Liu Signed-off-by: Tariq Toukan Reviewed-by: Jacob Keller --- drivers/net/ethernet/mellanox/mlx5/core/en/tc/meter.c | 8 +++----- drivers/net/ethernet/mellanox/mlx5/core/en_accel/macsec.c | 8 +++----- 2 files changed, 6 insertions(+), 10 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/tc/meter.c b/driver= s/net/ethernet/mellanox/mlx5/core/en/tc/meter.c index 7819fb297280..2ab618e11aad 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/tc/meter.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/tc/meter.c @@ -188,11 +188,9 @@ mlx5e_tc_meter_modify(struct mlx5_core_dev *mdev, =20 /* With newer FW, the wait for the first ASO WQE is more than 2us, put th= e wait 10ms. */ expires =3D jiffies + msecs_to_jiffies(10); - do { - err =3D mlx5_aso_poll_cq(aso, true); - if (err) - usleep_range(2, 10); - } while (err && time_is_after_jiffies(expires)); + while ((err =3D mlx5_aso_poll_cq(aso, true)) && + time_is_after_jiffies(expires)) + usleep_range(2, 10); mutex_unlock(&flow_meters->aso_lock); =20 return err; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/macsec.c b/dr= ivers/net/ethernet/mellanox/mlx5/core/en_accel/macsec.c index 528b04d4de41..2b3556fbfc42 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/macsec.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/macsec.c @@ -1412,11 +1412,9 @@ static int macsec_aso_query(struct mlx5_core_dev *md= ev, struct mlx5e_macsec *mac =20 mlx5_aso_post_wqe(maso, false, &aso_wqe->ctrl); expires =3D jiffies + msecs_to_jiffies(10); - do { - err =3D mlx5_aso_poll_cq(maso, false); - if (err) - usleep_range(2, 10); - } while (err && time_is_after_jiffies(expires)); + while ((err =3D mlx5_aso_poll_cq(maso, false)) && + time_is_after_jiffies(expires)) + usleep_range(2, 10); =20 if (err) goto err_out; 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Thu, 12 Feb 2026 02:33:06 -0800 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , , , , Gal Pressman , Moshe Shemesh , Jianbo Liu Subject: [PATCH net 4/6] net/mlx5e: MACsec, add ASO poll loop in macsec_aso_set_arm_event Date: Thu, 12 Feb 2026 12:32:15 +0200 Message-ID: <20260212103217.1752943-5-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260212103217.1752943-1-tariqt@nvidia.com> References: <20260212103217.1752943-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE33:EE_|MW6PR12MB8949:EE_ X-MS-Office365-Filtering-Correlation-Id: a58d191e-3cc9-411a-4a76-08de6a22289e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|82310400026|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?+EjGYokyCNh49iCbXB5/NWbuF1Grjjt+AqryCfUUfw5MPNe3nZf8a7GP8uiv?= =?us-ascii?Q?rRHJGsg87l/s9geZE1U/jT77oxJXTRUJey4bPYBbKSKWXtZnMfHETq1jNV/X?= =?us-ascii?Q?gKMUlCE1BIKaYXN/tMnNOcBsNlcI1MqYj6pmAXMd1+7mwcpXlUpbxMFj9IKM?= =?us-ascii?Q?XuyFDix68vk4Amy3GxdAMvohNZB7a07HY6T7AXHUA6eCEFIofX++XhvNU5zv?= =?us-ascii?Q?6KRFtOYVzjacrHZ7cPz+T/IADsDOZaoEH9R9ac3o8pLmGs7mDzpvV6WxmOll?= =?us-ascii?Q?TzIANDxqGewsjnSBtXCx/i7NV+f9NfaNHI2Cyw+P+TKXwgkB1p8W3dwmMeL1?= =?us-ascii?Q?g3zfcK4hdyQ6PXBdNITlSaypjhA8BaT5f1elaA3BaM9qkMy2T1Mr1+n3Y14/?= =?us-ascii?Q?chGZFAbLUVhguFYTGrChwwqHuTqoOo6Vq0vKN97voqoWl1y9wDq4+72/8s0m?= =?us-ascii?Q?7Rd2+BBGGaF4F86J6WsPiWFRUomtPhWpvKglXyxRWc9JIUGFwDZ67Y0VPKZV?= =?us-ascii?Q?mgg/BCBiC60YV/md4qlV53UMCTJlXcCYwQ1rkTXy9wsT1lmz/kCuYuOSy+aE?= =?us-ascii?Q?TvSE4xrkeYf3k3jl9Dy+G90Ud6Jz1S6qo8pgiI9mwwm/q0Uh0n6zUoPTPGyE?= =?us-ascii?Q?TMtan+DILV5BnHQ328ImET+8SkFpyi9LwlxCqljRKlLg7M3mWjgmWA80lQcM?= =?us-ascii?Q?Zf98yXhbgacA137/ukWfMWTAT2z5IyVCSncK1t0YHxTA9efkf2+5rjuhWs9q?= =?us-ascii?Q?dz0HpdSZQTXG7iQnJ80XHOBkXm0w5ytESMd3xML95rPjuaR5bTz+R+FbXxLp?= =?us-ascii?Q?NJa/EhJzz0JNn2VLaxpz1lk2kLDhQtVrjnoB+GTC+gFRhs3+FV6HQOVDf48q?= =?us-ascii?Q?C3Idp/5QRMpreoUu6ccvnRS73McA56nmjtujBDctQ+DF9xEKW8t0cvJQbwXT?= =?us-ascii?Q?w5E5fHgDvphCOmvqxik4I8s/01ra2mK6K5F2ET2EUwCW+tDAUS2O6WG07CoO?= =?us-ascii?Q?Jg9MU428gl2rmufkzNSzJpS2i60o8UsAx9iqbBSK09wivtRt9wBaOMPb8NMq?= =?us-ascii?Q?/4DYeGm7161cOMsKm3/5TKDoUldSoqh6ZrEiWfvLEBuXuVaw11APisEV4D2n?= =?us-ascii?Q?OjjtXqtpPXWydYScVmSUaxXiH38TkqY5NrJrH3VQwrOq1NDYcEC06UsqC7+e?= =?us-ascii?Q?tBvML8Ndc/SoFipJnIdbiYaKlnWJGsozDnkcXy3d007KfL/HRuGN+KJyR8Bk?= =?us-ascii?Q?txzHkNrat/w8GkSz8cmY8Exhrfww/E6WOeLC8N1Cmd4d0dhMyI2sDv8LBHIr?= =?us-ascii?Q?dxsmtOSqZBzg0IPEo8fawvjHunwdP0MKb0zur0jfJEWWeIGtjnuTSUOFc2cS?= =?us-ascii?Q?v4rPtOtMCbcEWLhADREiJdE3hr4S+Z7Q4JMknX+K1J6QKIG2YVEbv4cVEQbL?= =?us-ascii?Q?9dIOWT4iJntUZC6o1Fhi97vy4SEylr5mURjMwAuWDvNEBK4P/BO5D4a+77qW?= =?us-ascii?Q?k8rUXqA8ZFDSigqxuoTAtOc4nMEeadnUCEQYy7QlELIJioSfJFfL69NTX+wI?= =?us-ascii?Q?QyePDR5wanJSxjHMupUKEgz/FLjn5ruzAHILuHdkxBPwkp4pg/GLNgggp/9f?= =?us-ascii?Q?FIdJYUpHWuu63ofNzW8tzleOc4BYVul5EmSrScpZe91NoVsHXcMdN5PomNu3?= =?us-ascii?Q?hOFIJw=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(82310400026)(376014);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: kRQFrUzj6MY3/aE3VRJmQOP3P37TPPItCRJMtO5v5z9GqAu5GeoxaQxn9hhP2iukID7CAlK9P4SgGtNtnbwNXNQHbGgm5dDUkYEo0cYc9xUMV1ZJOFCZriEjarW9CTTPK34fs9tSoXJ42RlQvK7Px295ZDDt2UXldNfN6rXzXUcgYg97P9uGtYUAae81jPiLlPFVtUW1WGT1Z6Za6Dc8GZCReOAuTWdSCDM7ppuBTjSMG8q9NYh2as1pRThwfoE5N5+E39XdcY/PQPDkiBaolyJisCoLaHctZntsx8pEGshniLKmxFMgQqWqTD4C0/alipYAtBFhZGN9MFUDGYYVd4BxR1UdtR0X6NI3FUpGy8pT1u9Ye2cYbMbp3wD7zpWua3bp2rUUDMhkrJlRaWNmX0WcieDhrdb0TpnyoRZxxLrHOArZUPi5pwzyiW1SQmFv X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Feb 2026 10:33:27.4775 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a58d191e-3cc9-411a-4a76-08de6a22289e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE33.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW6PR12MB8949 Content-Type: text/plain; charset="utf-8" From: Gal Pressman The macsec_aso_set_arm_event function calls mlx5_aso_poll_cq once without a retry loop. If the CQE is not immediately available after posting the WQE, the function fails unnecessarily. Add a poll loop with timeout, consistent with other ASO polling code paths in the driver. Fixes: 739cfa34518e ("net/mlx5: Make ASO poll CQ usable in atomic context") Signed-off-by: Gal Pressman Reviewed-by: Jianbo Liu Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en_accel/macsec.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/macsec.c b/dr= ivers/net/ethernet/mellanox/mlx5/core/en_accel/macsec.c index 2b3556fbfc42..e64a46be1cbd 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/macsec.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/macsec.c @@ -1374,6 +1374,7 @@ static int macsec_aso_set_arm_event(struct mlx5_core_= dev *mdev, struct mlx5e_mac struct mlx5e_macsec_aso *aso; struct mlx5_aso_wqe *aso_wqe; struct mlx5_aso *maso; + unsigned long expires; int err; =20 aso =3D &macsec->aso; @@ -1385,7 +1386,10 @@ static int macsec_aso_set_arm_event(struct mlx5_core= _dev *mdev, struct mlx5e_mac MLX5_ACCESS_ASO_OPC_MOD_MACSEC); macsec_aso_build_ctrl(aso, &aso_wqe->aso_ctrl, in); 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , , , , Gal Pressman , Moshe Shemesh , Cosmin Ratiu , Dragos Tatulea Subject: [PATCH net 5/6] net/mlx5e: Fix deadlocks between devlink and netdev instance locks Date: Thu, 12 Feb 2026 12:32:16 +0200 Message-ID: <20260212103217.1752943-6-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260212103217.1752943-1-tariqt@nvidia.com> References: <20260212103217.1752943-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD77:EE_|MN0PR12MB6149:EE_ X-MS-Office365-Filtering-Correlation-Id: 61e9e210-4555-4f9f-e6c2-08de6a22281d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|82310400026|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?fYkBXpFNXPJgQSFC22fuXOJqJV17MgMQMW0SuW1ugu4jOSK5zAFYBZI1yO4D?= =?us-ascii?Q?gCBx9wLVmPogV8gFe+n5Ln0qfaTZ8U13vcy2d9X6eMurlHGDD7FsM0kM7iLx?= =?us-ascii?Q?KpkaQ17oWozFg8VsZ8FZNrdokoYDncRp1UcVjhuFgAwZUUc0RkVRYzjcrbCw?= =?us-ascii?Q?IgQFt1tP8JclHO5mAkSMoJ6xAF3hKs2vJUuJeliwmeWbqksBDNtT8/cpVxCV?= =?us-ascii?Q?ynsGr3HTjlBcPEzr1yVuxKJdH4k+vwz/5oSk3tmd09tvYkF6qkPeIqqyAg3R?= =?us-ascii?Q?dMIyw7AESJ8AJJAYhoO2vm3uzfXu3SxlZbAKftJMSj567WBr43Nztfcs/MR8?= =?us-ascii?Q?6NX2Kr+rSt69jJ6lK2ZeT9CGs8lhwoTLuhcbL3rixS4QL71WQjJ0lICxRbjY?= =?us-ascii?Q?gyTzMmp9Ve9VgohOkysC/VTjc4Emkx/YVGmpVZ7LH4au/OefsSHGwQERki0E?= =?us-ascii?Q?uMC6ZSvy9j6uRG1kwH6wWV+w5wKeCnWlkLz6yH2f+BJK8WGnQvN0kgTsqbgV?= =?us-ascii?Q?oe53AHYjO+FyZgFvyEcE9fCmqXKaeiQPHjKLV/5AjstcpcnZpVUYSyaCiygt?= =?us-ascii?Q?rZbDFa2AHY20hFLPyQyK74ud8/jFe69F64Z8e8Nx5bTkRpd16JqKJLvJuUFy?= =?us-ascii?Q?EyEVrCAC660UXXnGa33/kX19y7Sp8ThpESYUblUuYLezNvG7o6vFcV1+Vq3N?= =?us-ascii?Q?Mk85hBrprULLm/3eDwJJcRccUliVOXhF1eKYhOdbq/qcNSk+pfcEUyRdh5fw?= =?us-ascii?Q?yMrqW9oErUVoXZd+bedsw50ljRf1tc06J616WjXatvsD5wuo+dInp4F68J6m?= =?us-ascii?Q?b1zDTBljOLn45v3f6nAQdyzANMXEO1CC9w3JnIhvRfhwFpOfUCLiYG2Kkzo9?= =?us-ascii?Q?fVbX8eq+xwlCXqP9F20RCHEYK5Aspi+oXgeDjYw8KX+nlHClEXxLbIKOBBV3?= =?us-ascii?Q?ia0rkG8B1sgvlMUoo3+nV2BGUKXiYbOSzGl9u5l/vvQEeGdZuBQY/GhG7ubD?= =?us-ascii?Q?+jbqdZpFx0xzoYLUvIQoOMqvhWciOs/dDPxzj8+SGQotvlx9Ew18XtyEqZbI?= =?us-ascii?Q?Cs8eRV0z7MXP1VwOlJrUaov4DDcdZvGrRtSHNQlk2dIohU8OZbniuiUwxdGS?= =?us-ascii?Q?wIC4Xp11pQ+vOeRoytbL3Zan+lnM9d0Rv+J5RUGKLbCgg7NimwghDp+yr97E?= =?us-ascii?Q?E64HQi9GxdZHNkHugxZlDtsOmpRz6IJNU8o1AnvvcY4i+Hp2ATMZqpW/qiRk?= =?us-ascii?Q?S92F6B9MEv14AqL5N0nJjMBDMw86gwhTvbd4PGjX01gxFTislV4J8u4lW4m8?= =?us-ascii?Q?l3nBo1VgLcmyjEP7W4jb2RBAf5/9/XuQB8EU8umnJwEshzXk+8a9yK1N2EA7?= =?us-ascii?Q?2Jf2SqKMdiO0YRYO8mlpBf4uCskxWSX8BvVbhGtgEV2xvS2Fvsfe7oUjt+H+?= =?us-ascii?Q?MHf6Obx/svAcTArX6v9EL3cv5t6fMom2fTgMf1CPAryz3FoE9cwgsC8Q8MG/?= =?us-ascii?Q?mp/U4EhXlh38W68OAMiFkfnsq+7Rn/YG5lPRyDe/MpSUbZ+bU8zig/PQfzSk?= =?us-ascii?Q?CnfPTZeI2JcPJqRf61jWJT1e+hR8NK/GH8lWTud3OszhMp1n+8nV2gC4EOa6?= =?us-ascii?Q?ovNVsFAOzZHykQZ1PI3Sw5rFgiuJkCBXL0rmr88Kem3+MaMet4XiR/4FXC60?= =?us-ascii?Q?psrOPA=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(82310400026)(376014);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: JT3BPXKKf+bpqMS3z4yQpPnxUcY9ZkHVZBc+Mr96fLuHr7c7pmZOBNc4NesW0lcTtVvnkE9nUADsX6GklK+ndTQZEPXuN/uDNomirrvaHBPh+I66KpS1gnqDZ+rtULna1PL3FCTGf5cwksNC/fw7GcafoZ1fu12Jg2j+2OBCY6gb6eWIMuHFh33b1959+Y5SfJxloQp4EoWLb8mUigkbWcBpKoKvHBBT+wISK3WVvrdcp2MzvUdjkKwScbh+02QpZCsiQQpYUAM8tYJhgOXpmr9vhsyPzSW8iFE5jQFwtEV6kqX/jFafWjjhfy3rI0m8dgSDuhNj5Nhpxn/yAMXmTnxOY+J0nOQzwkVke3noMejbbDKYn1lNdgE/SGbQ8aFiwmQjXpct+TaOBwT5gvlvgQz2+0fDGBmQPWkKktjyi3jcWd1RzqgBHDXTREgf3xFs X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Feb 2026 10:33:26.5897 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 61e9e210-4555-4f9f-e6c2-08de6a22281d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD77.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6149 Content-Type: text/plain; charset="utf-8" From: Cosmin Ratiu In the mentioned "Fixes" commit, various work tasks triggering devlink health reporter recovery were switched to use netdev_trylock to protect against concurrent tear down of the channels being recovered. But this had the side effect of introducing potential deadlocks because of incorrect lock ordering. The correct lock order is described by the init flow: probe_one -> mlx5_init_one (acquires devlink lock) -> mlx5_init_one_devl_locked -> mlx5_register_device -> mlx5_rescan_drivers_locked -...-> mlx5e_probe -> _mlx5e_probe -> register_netdev (acquires rtnl lock) -> register_netdevice (acquires netdev lock) =3D> devlink lock -> rtnl lock -> netdev lock. But in the current recovery flow, the order is wrong: mlx5e_tx_err_cqe_work (acquires netdev lock) -> mlx5e_reporter_tx_err_cqe -> mlx5e_health_report -> devlink_health_report (acquires devlink lock =3D> boom!) -> devlink_health_reporter_recover -> mlx5e_tx_reporter_recover -> mlx5e_tx_reporter_recover_from_ctx -> mlx5e_tx_reporter_err_cqe_recover The same pattern exists in: mlx5e_reporter_rx_timeout mlx5e_reporter_tx_ptpsq_unhealthy mlx5e_reporter_tx_timeout Fix these by moving the netdev_trylock calls from the work handlers lower in the call stack, in the respective recovery functions, where they are actually necessary. Fixes: 8f7b00307bf1 ("net/mlx5e: Convert mlx5 netdevs to instance locking") Signed-off-by: Cosmin Ratiu Reviewed-by: Dragos Tatulea Signed-off-by: Tariq Toukan Reviewed-by: Jacob Keller --- .../net/ethernet/mellanox/mlx5/core/en/ptp.c | 14 ----- .../mellanox/mlx5/core/en/reporter_rx.c | 13 +++++ .../mellanox/mlx5/core/en/reporter_tx.c | 52 +++++++++++++++++-- .../net/ethernet/mellanox/mlx5/core/en_main.c | 40 -------------- 4 files changed, 61 insertions(+), 58 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/ptp.c b/drivers/net= /ethernet/mellanox/mlx5/core/en/ptp.c index 424f8a2728a3..74660e7fe674 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/ptp.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/ptp.c @@ -457,22 +457,8 @@ static void mlx5e_ptpsq_unhealthy_work(struct work_str= uct *work) { struct mlx5e_ptpsq *ptpsq =3D container_of(work, struct mlx5e_ptpsq, report_unhealthy_work); - struct mlx5e_txqsq *sq =3D &ptpsq->txqsq; - - /* Recovering the PTP SQ means re-enabling NAPI, which requires the - * netdev instance lock. However, SQ closing has to wait for this work - * task to finish while also holding the same lock. So either get the - * lock or find that the SQ is no longer enabled and thus this work is - * not relevant anymore. - */ - while (!netdev_trylock(sq->netdev)) { - if (!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state)) - return; - msleep(20); - } =20 mlx5e_reporter_tx_ptpsq_unhealthy(ptpsq); - netdev_unlock(sq->netdev); } =20 static int mlx5e_ptp_open_txqsq(struct mlx5e_ptp *c, u32 tisn, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/reporter_rx.c b/dri= vers/net/ethernet/mellanox/mlx5/core/en/reporter_rx.c index 0686fbdd5a05..6efb626b5506 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/reporter_rx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/reporter_rx.c @@ -1,6 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 // Copyright (c) 2019 Mellanox Technologies. =20 +#include + #include "health.h" #include "params.h" #include "txrx.h" @@ -177,6 +179,16 @@ static int mlx5e_rx_reporter_timeout_recover(void *ctx) rq =3D ctx; priv =3D rq->priv; =20 + /* Acquire netdev instance lock to synchronize with channel close and + * reopen flows. Either successfully obtain the lock, or detect that + * channels are closing for another reason, making this work no longer + * necessary. + */ + while (!netdev_trylock(rq->netdev)) { + if (!test_bit(MLX5E_STATE_CHANNELS_ACTIVE, &rq->priv->state)) + return 0; + msleep(20); + } mutex_lock(&priv->state_lock); =20 eq =3D rq->cq.mcq.eq; @@ -186,6 +198,7 @@ static int mlx5e_rx_reporter_timeout_recover(void *ctx) clear_bit(MLX5E_SQ_STATE_ENABLED, &rq->icosq->state); =20 mutex_unlock(&priv->state_lock); + netdev_unlock(rq->netdev); =20 return err; } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/reporter_tx.c b/dri= vers/net/ethernet/mellanox/mlx5/core/en/reporter_tx.c index 9e2cf191ed30..9f6454102cf7 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/reporter_tx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/reporter_tx.c @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* Copyright (c) 2019 Mellanox Technologies. */ =20 +#include + #include "health.h" #include "en/ptp.h" #include "en/devlink.h" @@ -78,6 +80,18 @@ static int mlx5e_tx_reporter_err_cqe_recover(void *ctx) if (!test_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state)) return 0; =20 + /* Recovering queues means re-enabling NAPI, which requires the netdev + * instance lock. However, SQ closing flows have to wait for work tasks + * to finish while also holding the netdev instance lock. So either get + * the lock or find that the SQ is no longer enabled and thus this work + * is not relevant anymore. + */ + while (!netdev_trylock(dev)) { + if (!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state)) + return 0; + msleep(20); + } + err =3D mlx5_core_query_sq_state(mdev, sq->sqn, &state); if (err) { netdev_err(dev, "Failed to query SQ 0x%x state. err =3D %d\n", @@ -113,9 +127,11 @@ static int mlx5e_tx_reporter_err_cqe_recover(void *ctx) else mlx5e_trigger_napi_sched(sq->cq.napi); =20 + netdev_unlock(dev); return 0; out: clear_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state); + netdev_unlock(dev); return err; } =20 @@ -136,10 +152,24 @@ static int mlx5e_tx_reporter_timeout_recover(void *ct= x) sq =3D to_ctx->sq; eq =3D sq->cq.mcq.eq; priv =3D sq->priv; + + /* Recovering the TX queues implies re-enabling NAPI, which requires + * the netdev instance lock. + * However, channel closing flows have to wait for this work to finish + * while holding the same lock. So either get the lock or find that + * channels are being closed for other reason and this work is not + * relevant anymore. + */ + while (!netdev_trylock(sq->netdev)) { + if (!test_bit(MLX5E_STATE_CHANNELS_ACTIVE, &priv->state)) + return 0; + msleep(20); + } + err =3D mlx5e_health_channel_eq_recover(sq->netdev, eq, sq->cq.ch_stats); if (!err) { to_ctx->status =3D 0; /* this sq recovered */ - return err; + goto out; } =20 mutex_lock(&priv->state_lock); @@ -147,7 +177,7 @@ static int mlx5e_tx_reporter_timeout_recover(void *ctx) mutex_unlock(&priv->state_lock); if (!err) { to_ctx->status =3D 1; /* all channels recovered */ - return err; + goto out; } =20 to_ctx->status =3D err; @@ -155,7 +185,8 @@ static int mlx5e_tx_reporter_timeout_recover(void *ctx) netdev_err(priv->netdev, "mlx5e_safe_reopen_channels failed recovering from a tx_timeout, err(= %d).\n", err); - +out: + netdev_unlock(sq->netdev); return err; } =20 @@ -172,10 +203,22 @@ static int mlx5e_tx_reporter_ptpsq_unhealthy_recover(= void *ctx) return 0; =20 priv =3D ptpsq->txqsq.priv; + netdev =3D priv->netdev; + + /* Recovering the PTP SQ means re-enabling NAPI, which requires the + * netdev instance lock. However, SQ closing has to wait for this work + * task to finish while also holding the same lock. So either get the + * lock or find that the SQ is no longer enabled and thus this work is + * not relevant anymore. + */ + while (!netdev_trylock(netdev)) { + if (!test_bit(MLX5E_SQ_STATE_ENABLED, &ptpsq->txqsq.state)) + return 0; + msleep(20); + } =20 mutex_lock(&priv->state_lock); chs =3D &priv->channels; - netdev =3D priv->netdev; =20 carrier_ok =3D netif_carrier_ok(netdev); netif_carrier_off(netdev); @@ -192,6 +235,7 @@ static int mlx5e_tx_reporter_ptpsq_unhealthy_recover(vo= id *ctx) netif_carrier_on(netdev); =20 mutex_unlock(&priv->state_lock); + netdev_unlock(netdev); =20 return err; } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/en_main.c index 4b2963bbe7ff..e15e6fb4cd8e 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -688,19 +688,7 @@ static void mlx5e_rq_timeout_work(struct work_struct *= timeout_work) struct mlx5e_rq, rx_timeout_work); =20 - /* Acquire netdev instance lock to synchronize with channel close and - * reopen flows. Either successfully obtain the lock, or detect that - * channels are closing for another reason, making this work no longer - * necessary. - */ - while (!netdev_trylock(rq->netdev)) { - if (!test_bit(MLX5E_STATE_CHANNELS_ACTIVE, &rq->priv->state)) - return; - msleep(20); - } - mlx5e_reporter_rx_timeout(rq); - netdev_unlock(rq->netdev); } =20 static int mlx5e_alloc_mpwqe_rq_drop_page(struct mlx5e_rq *rq) @@ -1997,20 +1985,7 @@ void mlx5e_tx_err_cqe_work(struct work_struct *recov= er_work) struct mlx5e_txqsq *sq =3D container_of(recover_work, struct mlx5e_txqsq, recover_work); =20 - /* Recovering queues means re-enabling NAPI, which requires the netdev - * instance lock. However, SQ closing flows have to wait for work tasks - * to finish while also holding the netdev instance lock. So either get - * the lock or find that the SQ is no longer enabled and thus this work - * is not relevant anymore. - */ - while (!netdev_trylock(sq->netdev)) { - if (!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state)) - return; - msleep(20); - } - mlx5e_reporter_tx_err_cqe(sq); - netdev_unlock(sq->netdev); } =20 static struct dim_cq_moder mlx5e_get_def_tx_moderation(u8 cq_period_mode) @@ -5121,19 +5096,6 @@ static void mlx5e_tx_timeout_work(struct work_struct= *work) struct net_device *netdev =3D priv->netdev; int i; =20 - /* Recovering the TX queues implies re-enabling NAPI, which requires - * the netdev instance lock. - * However, channel closing flows have to wait for this work to finish - * while holding the same lock. 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , , , , Gal Pressman , Moshe Shemesh , Cosmin Ratiu , Dragos Tatulea Subject: [PATCH net 6/6] net/mlx5e: Use unsigned for mlx5e_get_max_num_channels Date: Thu, 12 Feb 2026 12:32:17 +0200 Message-ID: <20260212103217.1752943-7-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260212103217.1752943-1-tariqt@nvidia.com> References: <20260212103217.1752943-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD78:EE_|CY5PR12MB6432:EE_ X-MS-Office365-Filtering-Correlation-Id: b02ba699-b5bb-4774-0d7b-08de6a222b9e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|376014|82310400026; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 4lQBRSZEIDPbS5i5BIilVXXczefEuabtkqFCBT2nCSqZCmScn7FkUglONi1VcKDCbfeVKsO5SrjsKl6pAnLsffN6lIQnHAEkOyv1QPazV4OXbgdyc98LPQFlB/ZtNvlX+I68JtDBgWSFNYg9BFT3kMut1nFbOBVWEQTRD1Ik2cbWBjJRr4U/o56lL/NwDwU7lTg8a0dns+7ocmrDgJFt5BV5H6dfFuLCyVNaU3ddy0jsrkbKzESZJtgj8aFmLhcH32WqHaFnUnnVoMdfFIfJvM2Ej9xJo1i2m45KVcXf4MglqD0PWLdAv7sOzA5vQTZFZ+/kn3g1/H/yer9B6lxyQGghYdo78IH0z51vzJuRYPSX/J+hGLdzdT+M6zk0aCdmNrBEcBJ0MpBOmJyjPTU7+OMZR+kKhoQ8rhf15k/rZa09P3Fwajs6DvEzSb6r6iQM X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Feb 2026 10:33:32.3892 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b02ba699-b5bb-4774-0d7b-08de6a222b9e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD78.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6432 From: Cosmin Ratiu The max number of channels is always an unsigned int, use the correct type to fix compilation errors done with strict type checking, e.g.: error: call to =E2=80=98__compiletime_assert_1110=E2=80=99 declared with at= tribute error: min(mlx5e_get_devlink_param_num_doorbells(mdev), mlx5e_get_max_num_channels(mdev)) signedness error Fixes: 74a8dadac17e ("net/mlx5e: Preparations for supporting larger number = of channels") Signed-off-by: Cosmin Ratiu Reviewed-by: Dragos Tatulea Signed-off-by: Tariq Toukan Reviewed-by: Jacob Keller --- drivers/net/ethernet/mellanox/mlx5/core/en.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/eth= ernet/mellanox/mlx5/core/en.h index ff4ab4691baf..a06d08576fd4 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h @@ -179,7 +179,8 @@ static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_= size) } =20 /* Use this function to get max num channels (rxqs/txqs) only to create ne= tdev */ -static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev) +static inline unsigned int +mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev) { return is_kdump_kernel() ? MLX5E_MIN_NUM_CHANNELS : --=20 2.44.0