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Thu, 12 Feb 2026 08:21:19 +0000 (GMT) From: Sanghoon Bae To: robh@kernel.org, krzk@kernel.org, conor+dt@kernel.org, vkoul@kernel.org, alim.akhtar@samsung.com, kishon@kernel.org Cc: krzk+dt@kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-samsung-soc@vger.kernel.org, sowon.na@samsung.com, Sanghoon Bae Subject: [PATCH v2 1/2] dt-bindings: soc: samsung: exynos-sysreg: Add hsi0 for ExynosAutov920 Date: Thu, 12 Feb 2026 17:21:03 +0900 Message-ID: <20260212082105.1878720-2-sh86.bae@samsung.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20260212082105.1878720-1-sh86.bae@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20260212082119epcas2p34791b0d7ad5ea3b50c6bcfe03cf0f16a X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P cpgsPolicy: CPGSC10-234,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20260212082119epcas2p34791b0d7ad5ea3b50c6bcfe03cf0f16a References: <20260212082105.1878720-1-sh86.bae@samsung.com> Add hsi0 compatible on samsung,exynos-sysreg To support ExynosAutov920 PCIe settings: - PCIe PHY power control - PLL settings for PCIe - PCIe device direction (RC/EP) Signed-off-by: Sanghoon Bae --- .../devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-s= ysreg.yaml b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-s= ysreg.yaml index d27ed6c9d61e..a44fd24ed0ea 100644 --- a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.y= aml +++ b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.y= aml @@ -30,6 +30,7 @@ properties: - samsung,exynos8895-fsys1-sysreg - samsung,exynos8895-peric0-sysreg - samsung,exynos8895-peric1-sysreg + - samsung,exynosautov920-hsi0-sysreg - samsung,exynosautov920-peric0-sysreg - samsung,exynosautov920-peric1-sysreg - tesla,fsd-cam-sysreg --=20 2.45.2 From nobody Sat Apr 18 01:57:59 2026 Received: from mailout3.samsung.com (mailout3.samsung.com [203.254.224.33]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B32482D028A for ; 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Thu, 12 Feb 2026 08:21:21 +0000 (GMT) Received: from epcas2p1.samsung.com (unknown [182.195.38.204]) by epsnrtp01.localdomain (Postfix) with ESMTP id 4fBStn15pfz6B9mL; Thu, 12 Feb 2026 08:21:21 +0000 (GMT) Received: from epsmtip1.samsung.com (unknown [182.195.34.30]) by epcas2p4.samsung.com (KnoxPortal) with ESMTPA id 20260212082120epcas2p4c6d8af1b07e82baded76eb356c9b87ee~Tcg13PRPb1340313403epcas2p4G; Thu, 12 Feb 2026 08:21:20 +0000 (GMT) Received: from asswp146.dsn.sec.samsung.com (unknown [10.229.19.146]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20260212082120epsmtip13610ddac2922bc1f19dbba658114bc75~Tcg1wg_pT2276322763epsmtip10; Thu, 12 Feb 2026 08:21:20 +0000 (GMT) From: Sanghoon Bae To: robh@kernel.org, krzk@kernel.org, conor+dt@kernel.org, vkoul@kernel.org, alim.akhtar@samsung.com, kishon@kernel.org Cc: krzk+dt@kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-samsung-soc@vger.kernel.org, sowon.na@samsung.com, Sanghoon Bae Subject: [PATCH v2 2/2] arm64: dts: exynosautov920: Add hsi0 syscon node for PCIe PHY Date: Thu, 12 Feb 2026 17:21:04 +0900 Message-ID: <20260212082105.1878720-3-sh86.bae@samsung.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20260212082105.1878720-1-sh86.bae@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20260212082120epcas2p4c6d8af1b07e82baded76eb356c9b87ee X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P cpgsPolicy: CPGSC10-234,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20260212082120epcas2p4c6d8af1b07e82baded76eb356c9b87ee References: <20260212082105.1878720-1-sh86.bae@samsung.com> Add the syscon-hsi0 node to control PCIe PHY power, PLL settings, and device direction (RC/EP mode) on ExynosAutov920. Signed-off-by: Sanghoon Bae --- arch/arm64/boot/dts/exynos/exynosautov920.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/bo= ot/dts/exynos/exynosautov920.dtsi index 2cb8041c8a9f..d21f8e008a00 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi @@ -1021,6 +1021,12 @@ cmu_hsi0: clock-controller@16000000 { "noc"; }; =20 + syscon_hsi0: syscon@16030000 { + compatible =3D "samsung,exynosautov920-hsi0-sysreg", + "syscon"; + reg =3D <0x16030000 0x1000>; + }; + pinctrl_hsi0: pinctrl@16040000 { compatible =3D "samsung,exynosautov920-pinctrl"; reg =3D <0x16040000 0x10000>; --=20 2.45.2