From nobody Thu Apr 2 09:12:32 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8C70E1D5147; Thu, 12 Feb 2026 16:41:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770914493; cv=none; b=mVICmtmhGm7aeXidexBbeRi2McpaySDiRew1Rs2j1F8WCHh0vNS2kEXlb/Mi2+dacps0vUQSgF2tRdf5rU6G6oXXnXkSgodZFZ6OuCtR/Ed5paTnMvCUN8Z7t5GPDwpXe9P+7MlxZzj2S8K/0cANtCWedSEnOIWcavb9TraLq0Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770914493; c=relaxed/simple; bh=ZZIqZvO+cbHwWRRln2LQYDho2ESFfBuyDF9/EYjv+0w=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:To:Cc; b=G9doigIp+4NpO9qhD33rvG4PMZqBRHgEsJydM46nbs0nR73CEJgOc/fAlDwGrXhA3Lr/EA2v/hftctANPiYzHrDomgIGOjAat2YfH4dT5bDVn/+Yj8oJNKnfQz3lsopPqF9lQ9wIfBRDuOz3btMBWOHw+qlG1Zy0oJH+ZJ6k+IY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Viz0zh10; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Viz0zh10" Received: by smtp.kernel.org (Postfix) with ESMTPS id 447D3C19424; Thu, 12 Feb 2026 16:41:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1770914493; bh=ZZIqZvO+cbHwWRRln2LQYDho2ESFfBuyDF9/EYjv+0w=; h=From:Date:Subject:To:Cc:Reply-To:From; b=Viz0zh10U/tDI0iG0hoVyMEtvEzSb/TIdfafb3bo77+11HVjP9smwmW98yBeVyRaV +UKRxKpbHe0h5VKIKRzM7dHRKSBsZ1QfFD8RGIoPy6RLcfGSNkYVUH67wTrGms3S8e SA0CFAVsrbxux/W+O29HdgQAPnHMcMkfs9mShid7fL2mz00fVNlr3ZAed/vOELcHAW 2CbQXLTz5QUgDFe1oxNieHY4rkU8N+0GmfAslU93g9TCps519MbWkm96fjVQ4Yts4s QwtZQAPRvPYYcrfWhku8Vlox27Vw8ofRvcs7y2OxBAwUDTKlMCuBSuxMHfjUmhA7B3 ih0hCABgAPcpg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 281EDEE36A1; Thu, 12 Feb 2026 16:41:33 +0000 (UTC) From: Aaron Kling via B4 Relay Date: Thu, 12 Feb 2026 10:41:25 -0600 Subject: [PATCH v3] arm64: dts: qcom: sm8550: Add UART15 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260212-sm8550-uart15-v3-1-b90405f94bec@gmail.com> X-B4-Tracking: v=1; b=H4sIAAAAAAAC/3XMSwrCMBSF4a2UOzaSmz4SHbkPcZBX2wvWSlKDU rp3046K4PAc+P4Zog/kI5yLGYJPFGl85FEeCrC9fnSekcsbBBcNF1yyOKi65uylw4Q1OxlpXKW 8rKSDbJ7Bt/Teetdb3j3FaQyfLZ9wff+VEjJkTlnbyqpxyMWlGzTdj3YcYC0lsdOIv1pkbZwoN XcelbF7vSzLF6rTw8/oAAAA X-Change-ID: 20260207-sm8550-uart15-9b7bd48e747d To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Xilin Wu , Molly Sophia , Aaron Kling , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1770914492; l=2588; i=webgeek1234@gmail.com; s=20250217; h=from:subject:message-id; bh=mR3/JRYkuGO8CBqOJAZJw6sx5dxfOUEZ5hawmrAeEFo=; b=aJx/b4n2h90yqY54V5mcmlCBuCfHejlMSqOOiBQPfP7/OiVeqMfSxHKS6XuTbH+o/eXOGYe+e WHBxjMNT5ybAF70oCuuZYYKSFNCnE1UA7pn7RFthPmtrVnoGEkoCysF X-Developer-Key: i=webgeek1234@gmail.com; a=ed25519; pk=TQwd6q26txw7bkK7B8qtI/kcAohZc7bHHGSD7domdrU= X-Endpoint-Received: by B4 Relay for webgeek1234@gmail.com/20250217 with auth_id=342 X-Original-From: Aaron Kling Reply-To: webgeek1234@gmail.com From: Xilin Wu Add uart15 node for UART bus present on sm8550 SoC. Signed-off-by: Molly Sophia Signed-off-by: Xilin Wu Reviewed-by: Dmitry Baryshkov Signed-off-by: Aaron Kling Reviewed-by: Konrad Dybcio --- This patch was originally submitted as part of a series to support the AYN Odin 2 [0]. That series stalled, so submitting separately. [0] https://lore.kernel.org/all/20240424-ayn-odin2-initial-v1-0-e0aa05c991f= d@gmail.com/ --- Changes in v3: - Properly pad reg address - Link to v2: https://lore.kernel.org/r/20260211-sm8550-uart15-v2-1-bd23a0d= e18bc@gmail.com Changes in v2: - Use QCOM_ICC_TAG_ define in interconnect paths phandle third argument - Link to v1: https://lore.kernel.org/r/20260207-sm8550-uart15-v1-1-d8ccf74= 6d102@gmail.com --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qco= m/sm8550.dtsi index e3f93f4f412ded9583a6bc9215185a0daf5f1b57..eebd5f9663edcc91480097aa39e= 9ca4dc3592dd9 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -1251,6 +1251,22 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, #size-cells =3D <0>; status =3D "disabled"; }; + + uart15: serial@89c000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0 0x0089c000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S7_CLK>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_uart15_default>; + interrupts =3D ; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", "qup-config"; + status =3D "disabled"; + }; }; =20 i2c_master_hub_0: geniqup@9c0000 { @@ -5095,6 +5111,14 @@ qup_uart14_cts_rts: qup-uart14-cts-rts-state { bias-pull-down; }; =20 + qup_uart15_default: qup-uart15-default-state { + /* TX, RX */ + pins =3D "gpio74", "gpio75"; + function =3D "qup2_se7"; + drive-strength =3D <2>; + bias-pull-up; + }; + sdc2_sleep: sdc2-sleep-state { clk-pins { pins =3D "sdc2_clk"; --- base-commit: 9845cf73f7db6094c0d8419d6adb848028f4a921 change-id: 20260207-sm8550-uart15-9b7bd48e747d Best regards, --=20 Aaron Kling