From nobody Thu Apr 2 20:08:14 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 89E1835B649; Thu, 12 Feb 2026 12:50:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770900604; cv=none; b=MAEenNz3BFe+j7Jj0C/be900g8Lt8JxOp03rolh/65WzV0wHAkyPJSxWobzcHWrsxj730ANAX4xY/L4xDHp7x+7ZiWmkeN+gbaF10QKwLHQfHbWv2VR3Sw/TAQXZ+M1UCblbx4zyIT8gPFPkF3rplm8AyWqMm6N7NPb3WMCnidY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770900604; c=relaxed/simple; bh=qOWmHhapn1WLqzrm0uoyFl9ooDpTy4BaWBzi3lwpMv0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=lnO/DuRsVPUkQXkMXXZTGK8l+3EJXGlGGjNsAyAtOQQr/USv0g48x1dalGfr95x+qbzHPIgMDxynKEBhrUw1Ak5Zz0YLY+hi+2XEg7UTH+Ke/dg2SMJwkzcn4pvm5QfM7vrNUw407n5AyakOq157C2Hk1qz2ZdpvsKtK/+E1//I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=hKSRLksz; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="hKSRLksz" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1770900601; x=1802436601; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=qOWmHhapn1WLqzrm0uoyFl9ooDpTy4BaWBzi3lwpMv0=; b=hKSRLksziA6/EOZU+O2F3rjEdjNdJpDI7fGb/N630sk9AbxYeZVuzcj9 EUenfZiUi0U3vDfw2h6bAF+y8tvo1kLznjCKUR+9vRwWzg9XDpvV+eTip XusBgY2m9XIeeOlVafyD/VDdhapQLlloAl98KRs4GfuZZb9OCP2CnEnqt udClx18vtxZugNSZ47OXBFcRGfNSU0gRZfLdmNGFSoIDV1/8ucxLCGKx6 sAfGXsf52YIwr4/0PLr70M+kzMx6LWLHMhvPCPjOWatunQDJSQ7sytrts 1pyhM3BUW4+vzsP2WTME98bU2VPyxHTcm58BQ+jkEXmM8y1r6OwyGIaLX w==; X-CSE-ConnectionGUID: k0Z43qZDSFazgSW80pkbgA== X-CSE-MsgGUID: srVtu2WERlu2mFYUNAybPA== X-IronPort-AV: E=Sophos;i="6.21,286,1763449200"; d="scan'208";a="53739855" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 12 Feb 2026 05:50:00 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Thu, 12 Feb 2026 05:49:10 -0700 Received: from [127.0.1.1] (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Thu, 12 Feb 2026 05:49:08 -0700 From: Ariana Lazar Date: Thu, 12 Feb 2026 14:48:35 +0200 Subject: [PATCH 2/2] iio: dac: add support for Microchip MCP48FEB02 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260212-mcp48feb02-v1-2-ce5843db65db@microchip.com> References: <20260212-mcp48feb02-v1-0-ce5843db65db@microchip.com> In-Reply-To: <20260212-mcp48feb02-v1-0-ce5843db65db@microchip.com> To: Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , "Andy Shevchenko" , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley CC: , , , Ariana Lazar X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1770900543; l=43346; i=ariana.lazar@microchip.com; s=20250825; h=from:subject:message-id; bh=qOWmHhapn1WLqzrm0uoyFl9ooDpTy4BaWBzi3lwpMv0=; b=hXer2uNyNQWVx35FoMwfbUavrfYtJwThvO6dyl5U45QyqBUBohYrL2n894KsfOQTzio2SvtcU dn8O8RqCkrAA0+nGhmY1OnLtuQQnOmMvtxhKGX6vWa/JxjkU4j4Z6fL X-Developer-Key: i=ariana.lazar@microchip.com; a=ed25519; pk=jmvf1fSxcnzZmXfITM3L94IwutM+wqA1POQHiYyD6Dk= This is the iio driver for Microchip MCP48FxBy1/2/4/8 series of buffered voltage output Digital-to-Analog Converters with nonvolatile or volatile memory and an SPI Interface. The families support up to 8 output channels. The devices can be 8-bit, 10-bit and 12-bit. Signed-off-by: Ariana Lazar --- MAINTAINERS | 1 + drivers/iio/dac/Kconfig | 20 + drivers/iio/dac/Makefile | 1 + drivers/iio/dac/mcp48feb02.c | 1243 ++++++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 1265 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index ed24fd2758ad0103dbc5191d0ec180f8ee5e8298..c861001ff9a94af2ff98c9c697e= 40909a4c69f6d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14950,6 +14950,7 @@ M: Ariana Lazar L: linux-iio@vger.kernel.org S: Supported F: Documentation/devicetree/bindings/iio/dac/microchip,mcp48feb02.yaml +F: drivers/iio/dac/mcp48feb02.c =20 MCR20A IEEE-802.15.4 RADIO DRIVER M: Stefan Schmidt diff --git a/drivers/iio/dac/Kconfig b/drivers/iio/dac/Kconfig index e0996dc014a3d538ab6b4e0d50ff54ede50f1527..56fb14abb36c6955348ca0b1ad7= 2ce47a4af4e0d 100644 --- a/drivers/iio/dac/Kconfig +++ b/drivers/iio/dac/Kconfig @@ -519,6 +519,26 @@ config MCP4821 To compile this driver as a module, choose M here: the module will be called mcp4821. =20 +config MCP48FEB02 + tristate "MCP48FxBy1/2/4/8 driver" + depends on SPI + help + Say yes here if you want to build the driver for the Microchip: + - 8-bit DAC: + MCP48FEB01, MCP48FEB02, MCP48FEB04, MCP48FEB08, + MCP48FVB01, MCP48FVB02, MCP48FVB04, MCP48FVB08 + - 10-bit DAC: + MCP48FEB11, MCP48FEB12, MCP48FEB14, MCP48FEB18, + MCP48FVB11, MCP48FVB12, MCP48FVB14, MCP48FVB18 + - 12-bit DAC: + MCP48FEB21, MCP48FEB22, MCP48FEB24, MCP48FEB28, + MCP48FVB21, MCP48FVB22, MCP48FVB24, MCP48FVB28 + having 1 to 8 channels, 8/10/12-bit digital-to-analog converter + (DAC) with SPI interface. + + To compile this driver as a module, choose M here: the module + will be called mcp48feb02. + config MCP4922 tristate "MCP4902, MCP4912, MCP4922 DAC driver" depends on SPI diff --git a/drivers/iio/dac/Makefile b/drivers/iio/dac/Makefile index 3684cd52b7fa9bc0ad9f855323dcbb2e4965c404..77b473823bdcc265797169a2bcc= 263b110092faa 100644 --- a/drivers/iio/dac/Makefile +++ b/drivers/iio/dac/Makefile @@ -51,6 +51,7 @@ obj-$(CONFIG_MAX5821) +=3D max5821.o obj-$(CONFIG_MCP4725) +=3D mcp4725.o obj-$(CONFIG_MCP4728) +=3D mcp4728.o obj-$(CONFIG_MCP4821) +=3D mcp4821.o +obj-$(CONFIG_MCP48FEB02) +=3D mcp48feb02.o obj-$(CONFIG_MCP4922) +=3D mcp4922.o obj-$(CONFIG_STM32_DAC_CORE) +=3D stm32-dac-core.o obj-$(CONFIG_STM32_DAC) +=3D stm32-dac.o diff --git a/drivers/iio/dac/mcp48feb02.c b/drivers/iio/dac/mcp48feb02.c new file mode 100644 index 0000000000000000000000000000000000000000..20955f77053329a9c385f55c731= 4032eb6b04dfd --- /dev/null +++ b/drivers/iio/dac/mcp48feb02.c @@ -0,0 +1,1243 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * IIO driver for MCP48FEB02 Multi-Channel DAC with SPI interface + * + * Copyright (C) 2026 Microchip Technology Inc. and its subsidiaries + * + * Author: Ariana Lazar + * + * Datasheet links: + * [MCP48FEBxx] https://ww1.microchip.com/downloads/aemDocuments/documents= /OTH/ProductDocuments/DataSheets/20005429B.pdf + * [MCP48FVBxx] https://ww1.microchip.com/downloads/aemDocuments/documents= /OTH/ProductDocuments/DataSheets/20005466A.pdf + * [MCP48FxBx4/8] https://ww1.microchip.com/downloads/aemDocuments/documen= ts/MSLD/ProductDocuments/DataSheets/MCP48FXBX4-8-Family-Data-Sheet-DS200063= 62A.pdf + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Register addresses must be left shifted with 3 positions in order to ap= pend command mask */ +#define MCP48FEB02_DAC0_REG_ADDR 0x00 +#define MCP48FEB02_VREF_REG_ADDR 0x40 +#define MCP48FEB02_POWER_DOWN_REG_ADDR 0x48 +#define MCP48FEB02_DAC_CTRL_MASK GENMASK(1, 0) + +#define MCP48FEB02_GAIN_CTRL_STATUS_REG_ADDR 0x50 +#define MCP48FEB02_GAIN_BIT_MASK BIT(0) +#define MCP48FEB02_GAIN_BIT_STATUS_EEWA_MASK BIT(6) +#define MCP48FEB02_GAIN_BITS_MASK GENMASK(15, 8) + +#define MCP48FEB02_WIPERLOCK_STATUS_REG_ADDR 0x58 + +#define MCP48FEB02_NV_DAC0_REG_ADDR 0x80 +#define MCP48FEB02_NV_VREF_REG_ADDR 0xC0 +#define MCP48FEB02_NV_POWER_DOWN_REG_ADDR 0xC8 +#define MCP48FEB02_NV_GAIN_CTRL_I2C_SLAVE_REG_ADDR 0xD0 +#define MCP48FEB02_NV_I2C_SLAVE_ADDR_MASK GENMASK(7, 0) + +/* Voltage reference, Power-Down control register and DAC Wiperlock status= register fields */ +#define DAC_CTRL_MASK(ch) (GENMASK(1, 0) << (2 * (ch))) +#define DAC_CTRL_VAL(ch, val) ((val) << (2 * (ch))) + +/* Gain Control and I2C Slave Address Reguster fields */ +#define DAC_GAIN_MASK(ch) (BIT(0) << (8 + (ch))) +#define DAC_GAIN_VAL(ch, val) ((val) << (8 + (ch))) + +#define REG_ADDR(reg) ((reg) << 3) +#define NV_REG_ADDR(reg) ((NV_DAC_ADDR_OFFSET + (reg)) << 3) +#define READFLAG_MASK GENMASK(2, 1) + +#define MCP48FEB02_MAX_CH 8 +#define MCP48FEB02_MAX_SCALES_CH 3 +#define MCP48FEB02_DAC_WIPER_UNLOCKED 0 +#define MCP48FEB02_NORMAL_OPERATION 0 +#define MCP48FEB02_INTERNAL_BAND_GAP_uV 2440000 +#define NV_DAC_ADDR_OFFSET 0x10 + +enum mcp48feb02_vref_mode { + MCP48FEB02_VREF_VDD =3D 0, + MCP48FEB02_INTERNAL_BAND_GAP =3D 1, + MCP48FEB02_EXTERNAL_VREF_UNBUFFERED =3D 2, + MCP48FEB02_EXTERNAL_VREF_BUFFERED =3D 3, +}; + +enum mcp48feb02_scale { + MCP48FEB02_SCALE_VDD =3D 0, + MCP48FEB02_SCALE_GAIN_X1 =3D 1, + MCP48FEB02_SCALE_GAIN_X2 =3D 2, +}; + +enum mcp48feb02_gain_bit_mode { + MCP48FEB02_GAIN_BIT_X1 =3D 0, + MCP48FEB02_GAIN_BIT_X2 =3D 1, +}; + +static const char * const mcp48feb02_powerdown_modes[] =3D { + "1kohm_to_gnd", + "100kohm_to_gnd", + "open_circuit", +}; + +/** + * struct mcp48feb02_features - chip specific data + * @name: device name + * @phys_channels: number of hardware channels + * @resolution: DAC resolution + * @have_ext_vref1: does the hardware have an the second external voltage = reference? + * @have_eeprom: does the hardware have an internal eeprom? + */ +struct mcp48feb02_features { + const char *name; + unsigned int phys_channels; + unsigned int resolution; + bool have_ext_vref1; + bool have_eeprom; +}; + +static const struct mcp48feb02_features mcp48feb01_chip_features =3D { + .name =3D "mcp48feb01", + .phys_channels =3D 1, + .resolution =3D 8, + .have_ext_vref1 =3D false, + .have_eeprom =3D true, +}; + +static const struct mcp48feb02_features mcp48feb02_chip_features =3D { + .name =3D "mcp48feb02", + .phys_channels =3D 2, + .resolution =3D 8, + .have_ext_vref1 =3D false, + .have_eeprom =3D true, +}; + +static const struct mcp48feb02_features mcp48feb04_chip_features =3D { + .name =3D "mcp48feb04", + .phys_channels =3D 4, + .resolution =3D 8, + .have_ext_vref1 =3D true, + .have_eeprom =3D true, +}; + +static const struct mcp48feb02_features mcp48feb08_chip_features =3D { + .name =3D "mcp48feb08", + .phys_channels =3D 8, + .resolution =3D 8, + .have_ext_vref1 =3D true, + .have_eeprom =3D true, +}; + +static const struct mcp48feb02_features mcp48feb11_chip_features =3D { + .name =3D "mcp48feb11", + .phys_channels =3D 1, + .resolution =3D 10, + .have_ext_vref1 =3D false, + .have_eeprom =3D true, +}; + +static const struct mcp48feb02_features mcp48feb12_chip_features =3D { + .name =3D "mcp48feb12", + .phys_channels =3D 2, + .resolution =3D 10, + .have_ext_vref1 =3D false, + .have_eeprom =3D true, +}; + +static const struct mcp48feb02_features mcp48feb14_chip_features =3D { + .name =3D "mcp48feb14", + .phys_channels =3D 4, + .resolution =3D 10, + .have_ext_vref1 =3D true, + .have_eeprom =3D true, +}; + +static const struct mcp48feb02_features mcp48feb18_chip_features =3D { + .name =3D "mcp48feb18", + .phys_channels =3D 8, + .resolution =3D 10, + .have_ext_vref1 =3D true, + .have_eeprom =3D true, +}; + +static const struct mcp48feb02_features mcp48feb21_chip_features =3D { + .name =3D "mcp48feb21", + .phys_channels =3D 1, + .resolution =3D 12, + .have_ext_vref1 =3D false, + .have_eeprom =3D true, +}; + +static const struct mcp48feb02_features mcp48feb22_chip_features =3D { + .name =3D "mcp48feb22", + .phys_channels =3D 2, + .resolution =3D 12, + .have_ext_vref1 =3D false, + .have_eeprom =3D true, +}; + +static const struct mcp48feb02_features mcp48feb24_chip_features =3D { + .name =3D "mcp48feb24", + .phys_channels =3D 4, + .resolution =3D 12, + .have_ext_vref1 =3D true, + .have_eeprom =3D true, +}; + +static const struct mcp48feb02_features mcp48feb28_chip_features =3D { + .name =3D "mcp48feb28", + .phys_channels =3D 8, + .resolution =3D 12, + .have_ext_vref1 =3D true, + .have_eeprom =3D true, +}; + +static const struct mcp48feb02_features mcp48fvb01_chip_features =3D { + .name =3D "mcp48fvb01", + .phys_channels =3D 1, + .resolution =3D 8, + .have_ext_vref1 =3D false, + .have_eeprom =3D false, +}; + +static const struct mcp48feb02_features mcp48fvb02_chip_features =3D { + .name =3D "mcp48fvb02", + .phys_channels =3D 2, + .resolution =3D 8, + .have_ext_vref1 =3D false, + .have_eeprom =3D false, +}; + +static const struct mcp48feb02_features mcp48fvb04_chip_features =3D { + .name =3D "mcp48fvb04", + .phys_channels =3D 4, + .resolution =3D 8, + .have_ext_vref1 =3D true, + .have_eeprom =3D false, +}; + +static const struct mcp48feb02_features mcp48fvb08_chip_features =3D { + .name =3D "mcp48fvb08", + .phys_channels =3D 8, + .resolution =3D 8, + .have_ext_vref1 =3D true, + .have_eeprom =3D false, +}; + +static const struct mcp48feb02_features mcp48fvb11_chip_features =3D { + .name =3D "mcp48fvb11", + .phys_channels =3D 1, + .resolution =3D 10, + .have_ext_vref1 =3D false, + .have_eeprom =3D false, +}; + +static const struct mcp48feb02_features mcp48fvb12_chip_features =3D { + .name =3D "mcp48fvb12", + .phys_channels =3D 2, + .resolution =3D 10, + .have_ext_vref1 =3D false, + .have_eeprom =3D false, +}; + +static const struct mcp48feb02_features mcp48fvb14_chip_features =3D { + .name =3D "mcp48fvb14", + .phys_channels =3D 4, + .resolution =3D 10, + .have_ext_vref1 =3D true, + .have_eeprom =3D false, +}; + +static const struct mcp48feb02_features mcp48fvb18_chip_features =3D { + .name =3D "mcp48fvb18", + .phys_channels =3D 8, + .resolution =3D 10, + .have_ext_vref1 =3D true, + .have_eeprom =3D false, +}; + +static const struct mcp48feb02_features mcp48fvb21_chip_features =3D { + .name =3D "mcp48fvb21", + .phys_channels =3D 1, + .resolution =3D 12, + .have_ext_vref1 =3D false, + .have_eeprom =3D false, +}; + +static const struct mcp48feb02_features mcp48fvb22_chip_features =3D { + .name =3D "mcp48fvb22", + .phys_channels =3D 2, + .resolution =3D 12, + .have_ext_vref1 =3D false, + .have_eeprom =3D false, +}; + +static const struct mcp48feb02_features mcp48fvb24_chip_features =3D { + .name =3D "mcp48fvb24", + .phys_channels =3D 4, + .resolution =3D 12, + .have_ext_vref1 =3D true, + .have_eeprom =3D false, +}; + +static const struct mcp48feb02_features mcp48fvb28_chip_features =3D { + .name =3D "mcp48fvb28", + .phys_channels =3D 8, + .resolution =3D 12, + .have_ext_vref1 =3D true, + .have_eeprom =3D false, +}; + +/** + * struct mcp48feb02_channel_data - channel configuration + * @ref_mode: chosen voltage for reference + * @use_2x_gain: output driver gain control + * @powerdown: is false if the channel is in normal operation mode + * @powerdown_mode: selected power-down mode + * @dac_data: dac value + */ +struct mcp48feb02_channel_data { + u8 ref_mode; + bool use_2x_gain; + bool powerdown; + u8 powerdown_mode; + u16 dac_data; +}; + +/** + * struct mcp48feb02_data - chip configuration + * @chdata: options configured for each channel on the device + * @lock: prevents concurrent reads/writes to driver's state members + * @chip_features: pointer to features struct + * @scale_1: scales set on channels that are based on Vref1 + * @scale: scales set on channels that are based on Vref/Vref0 + * @active_channels_mask: enabled channels + * @regmap: regmap for directly accessing device register + * @labels: table with channels labels + * @phys_channels: physical channels on the device + * @vref1_buffered: Vref1 buffer is enabled + * @vref_buffered: Vref/Vref0 buffer is enabled + * @use_vref1: vref1-supply is defined + * @use_vref: vref-supply is defined + */ +struct mcp48feb02_data { + struct mcp48feb02_channel_data chdata[MCP48FEB02_MAX_CH]; + struct mutex lock; /* prevents concurrent reads/writes to driver's state = members */ + const struct mcp48feb02_features *chip_features; + int scale_1[2 * MCP48FEB02_MAX_SCALES_CH]; + int scale[2 * MCP48FEB02_MAX_SCALES_CH]; + unsigned long active_channels_mask; + struct regmap *regmap; + const char *labels[MCP48FEB02_MAX_CH]; + u16 phys_channels; + bool vref1_buffered; + bool vref_buffered; + bool use_vref1; + bool use_vref; +}; + +static const struct regmap_range mcp48feb02_readable_ranges[] =3D { + regmap_reg_range(MCP48FEB02_DAC0_REG_ADDR, MCP48FEB02_WIPERLOCK_STATUS_RE= G_ADDR), + regmap_reg_range(MCP48FEB02_NV_DAC0_REG_ADDR, MCP48FEB02_NV_GAIN_CTRL_I2C= _SLAVE_REG_ADDR), +}; + +static const struct regmap_range mcp48feb02_writable_ranges[] =3D { + regmap_reg_range(MCP48FEB02_DAC0_REG_ADDR, MCP48FEB02_WIPERLOCK_STATUS_RE= G_ADDR), + regmap_reg_range(MCP48FEB02_NV_DAC0_REG_ADDR, MCP48FEB02_NV_GAIN_CTRL_I2C= _SLAVE_REG_ADDR), +}; + +static const struct regmap_range mcp48feb02_volatile_ranges[] =3D { + regmap_reg_range(MCP48FEB02_DAC0_REG_ADDR, MCP48FEB02_WIPERLOCK_STATUS_RE= G_ADDR), + regmap_reg_range(MCP48FEB02_NV_DAC0_REG_ADDR, MCP48FEB02_NV_GAIN_CTRL_I2C= _SLAVE_REG_ADDR), + regmap_reg_range(MCP48FEB02_DAC0_REG_ADDR, MCP48FEB02_WIPERLOCK_STATUS_RE= G_ADDR), + regmap_reg_range(MCP48FEB02_NV_DAC0_REG_ADDR, MCP48FEB02_NV_GAIN_CTRL_I2C= _SLAVE_REG_ADDR), +}; + +static const struct regmap_access_table mcp48feb02_readable_table =3D { + .yes_ranges =3D mcp48feb02_readable_ranges, + .n_yes_ranges =3D ARRAY_SIZE(mcp48feb02_readable_ranges), +}; + +static const struct regmap_access_table mcp48feb02_writable_table =3D { + .yes_ranges =3D mcp48feb02_writable_ranges, + .n_yes_ranges =3D ARRAY_SIZE(mcp48feb02_writable_ranges), +}; + +static const struct regmap_access_table mcp48feb02_volatile_table =3D { + .yes_ranges =3D mcp48feb02_volatile_ranges, + .n_yes_ranges =3D ARRAY_SIZE(mcp48feb02_volatile_ranges), +}; + +static const struct regmap_config mcp48feb02_regmap_config =3D { + .name =3D "mcp48feb02_regmap", + .reg_bits =3D 8, + .val_bits =3D 16, + .rd_table =3D &mcp48feb02_readable_table, + .wr_table =3D &mcp48feb02_writable_table, + .volatile_table =3D &mcp48feb02_volatile_table, + .max_register =3D MCP48FEB02_NV_GAIN_CTRL_I2C_SLAVE_REG_ADDR, + .read_flag_mask =3D READFLAG_MASK, + .cache_type =3D REGCACHE_MAPLE, + .val_format_endian =3D REGMAP_ENDIAN_BIG, +}; + +/* For devices that doesn't have nonvolatile memory */ +static const struct regmap_range mcp48fvb02_readable_ranges[] =3D { + regmap_reg_range(MCP48FEB02_DAC0_REG_ADDR, MCP48FEB02_WIPERLOCK_STATUS_RE= G_ADDR), +}; + +static const struct regmap_range mcp48fvb02_writable_ranges[] =3D { + regmap_reg_range(MCP48FEB02_DAC0_REG_ADDR, MCP48FEB02_WIPERLOCK_STATUS_RE= G_ADDR), +}; + +static const struct regmap_range mcp48fvb02_volatile_ranges[] =3D { + regmap_reg_range(MCP48FEB02_DAC0_REG_ADDR, MCP48FEB02_WIPERLOCK_STATUS_RE= G_ADDR), + regmap_reg_range(MCP48FEB02_DAC0_REG_ADDR, MCP48FEB02_WIPERLOCK_STATUS_RE= G_ADDR), +}; + +static const struct regmap_access_table mcp48fvb02_readable_table =3D { + .yes_ranges =3D mcp48fvb02_readable_ranges, + .n_yes_ranges =3D ARRAY_SIZE(mcp48fvb02_readable_ranges), +}; + +static const struct regmap_access_table mcp48fvb02_writable_table =3D { + .yes_ranges =3D mcp48fvb02_writable_ranges, + .n_yes_ranges =3D ARRAY_SIZE(mcp48fvb02_writable_ranges), +}; + +static const struct regmap_access_table mcp48fvb02_volatile_table =3D { + .yes_ranges =3D mcp48fvb02_volatile_ranges, + .n_yes_ranges =3D ARRAY_SIZE(mcp48fvb02_volatile_ranges), +}; + +static const struct regmap_config mcp48fvb02_regmap_config =3D { + .name =3D "mcp48fvb02_regmap", + .reg_bits =3D 8, + .val_bits =3D 16, + .rd_table =3D &mcp48fvb02_readable_table, + .wr_table =3D &mcp48fvb02_writable_table, + .volatile_table =3D &mcp48fvb02_volatile_table, + .max_register =3D MCP48FEB02_WIPERLOCK_STATUS_REG_ADDR, + .read_flag_mask =3D READFLAG_MASK, + .cache_type =3D REGCACHE_MAPLE, + .val_format_endian =3D REGMAP_ENDIAN_BIG, +}; + +static int mcp48feb02_write_to_eeprom(struct mcp48feb02_data *data, unsign= ed int reg, + unsigned int val) +{ + int eewa_val, ret; + + ret =3D regmap_read_poll_timeout(data->regmap, MCP48FEB02_GAIN_CTRL_STATU= S_REG_ADDR, + eewa_val, + !(eewa_val & MCP48FEB02_GAIN_BIT_STATUS_EEWA_MASK), + USEC_PER_MSEC, USEC_PER_MSEC * 5); + if (ret) + return ret; + + return regmap_write(data->regmap, reg, val); +} + +static ssize_t store_eeprom_store(struct device *dev, struct device_attrib= ute *attr, + const char *buf, size_t len) +{ + struct mcp48feb02_data *data =3D iio_priv(dev_to_iio_dev(dev)); + unsigned int i, val, val1, eewa_val; + bool state; + int ret; + + ret =3D kstrtobool(buf, &state); + if (ret) + return ret; + + if (!state) + return 0; + + /* + * Wait until the currently occurring EEPROM Write Cycle is completed. + * Only serial commands to the volatile memory are allowed. + */ + guard(mutex)(&data->lock); + + /* + * Verify DAC Wiper and DAC Configuration are unlocked. If both are disab= led, + * writing to EEPROM is available. + */ + ret =3D regmap_read(data->regmap, MCP48FEB02_WIPERLOCK_STATUS_REG_ADDR, &= val); + if (ret) + return ret; + + if (val) { + dev_err(dev, "DAC Wiper and DAC Configuration not are unlocked.\n"); + return -EINVAL; + } + + for_each_set_bit(i, &data->active_channels_mask, data->phys_channels) { + ret =3D mcp48feb02_write_to_eeprom(data, NV_REG_ADDR(i), + data->chdata[i].dac_data); + if (ret) + return ret; + } + + ret =3D regmap_read(data->regmap, MCP48FEB02_VREF_REG_ADDR, &val); + if (ret) + return ret; + + ret =3D mcp48feb02_write_to_eeprom(data, MCP48FEB02_NV_VREF_REG_ADDR, val= ); + if (ret) + return ret; + + ret =3D regmap_read(data->regmap, MCP48FEB02_POWER_DOWN_REG_ADDR, &val); + if (ret) + return ret; + + ret =3D mcp48feb02_write_to_eeprom(data, MCP48FEB02_NV_POWER_DOWN_REG_ADD= R, val); + if (ret) + return ret; + + ret =3D regmap_read_poll_timeout(data->regmap, MCP48FEB02_GAIN_CTRL_STATU= S_REG_ADDR, eewa_val, + !(eewa_val & MCP48FEB02_GAIN_BIT_STATUS_EEWA_MASK), + USEC_PER_MSEC, USEC_PER_MSEC * 5); + if (ret) + return ret; + + ret =3D regmap_read(data->regmap, MCP48FEB02_NV_GAIN_CTRL_I2C_SLAVE_REG_A= DDR, &val); + if (ret) + return ret; + + ret =3D regmap_read(data->regmap, MCP48FEB02_GAIN_CTRL_STATUS_REG_ADDR, &= val1); + if (ret) + return ret; + + ret =3D mcp48feb02_write_to_eeprom(data, MCP48FEB02_NV_GAIN_CTRL_I2C_SLAV= E_REG_ADDR, + (val1 & MCP48FEB02_GAIN_BITS_MASK) | + (val & MCP48FEB02_NV_I2C_SLAVE_ADDR_MASK)); + if (ret) + return ret; + + return len; +} + +static IIO_DEVICE_ATTR_WO(store_eeprom, 0); + +static struct attribute *mcp48feb02_attributes[] =3D { + &iio_dev_attr_store_eeprom.dev_attr.attr, + NULL +}; + +static const struct attribute_group mcp48feb02_attribute_group =3D { + .attrs =3D mcp48feb02_attributes, +}; + +static int mcp48feb02_suspend(struct device *dev) +{ + struct iio_dev *indio_dev =3D dev_get_drvdata(dev); + struct mcp48feb02_data *data =3D iio_priv(indio_dev); + int ret; + u8 ch; + + guard(mutex)(&data->lock); + + for_each_set_bit(ch, &data->active_channels_mask, data->phys_channels) { + u8 pd_mode; + + data->chdata[ch].powerdown =3D true; + pd_mode =3D data->chdata[ch].powerdown_mode + 1; + ret =3D regmap_update_bits(data->regmap, MCP48FEB02_POWER_DOWN_REG_ADDR, + DAC_CTRL_MASK(ch), DAC_CTRL_VAL(ch, pd_mode)); + if (ret) + return ret; + + ret =3D regmap_write(data->regmap, REG_ADDR(ch), data->chdata[ch].dac_da= ta); + if (ret) + return ret; + } + + return 0; +} + +static int mcp48feb02_resume(struct device *dev) +{ + struct iio_dev *indio_dev =3D dev_get_drvdata(dev); + struct mcp48feb02_data *data =3D iio_priv(indio_dev); + u8 ch; + + guard(mutex)(&data->lock); + + for_each_set_bit(ch, &data->active_channels_mask, data->phys_channels) { + int ret; + + data->chdata[ch].powerdown =3D false; + + ret =3D regmap_write(data->regmap, REG_ADDR(ch), data->chdata[ch].dac_da= ta); + if (ret) + return ret; + + ret =3D regmap_update_bits(data->regmap, MCP48FEB02_VREF_REG_ADDR, + DAC_CTRL_MASK(ch), + DAC_CTRL_VAL(ch, data->chdata[ch].ref_mode)); + if (ret) + return ret; + + ret =3D regmap_update_bits(data->regmap, MCP48FEB02_GAIN_CTRL_STATUS_REG= _ADDR, + DAC_GAIN_MASK(ch), + DAC_GAIN_VAL(ch, data->chdata[ch].use_2x_gain)); + if (ret) + return ret; + + ret =3D regmap_update_bits(data->regmap, MCP48FEB02_POWER_DOWN_REG_ADDR, + DAC_CTRL_MASK(ch), + DAC_CTRL_VAL(ch, MCP48FEB02_NORMAL_OPERATION)); + if (ret) + return ret; + } + + return 0; +} + +static int mcp48feb02_get_powerdown_mode(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan) +{ + struct mcp48feb02_data *data =3D iio_priv(indio_dev); + + return data->chdata[chan->address].powerdown_mode; +} + +static int mcp48feb02_set_powerdown_mode(struct iio_dev *indio_dev, const = struct iio_chan_spec *ch, + unsigned int mode) +{ + struct mcp48feb02_data *data =3D iio_priv(indio_dev); + + data->chdata[ch->address].powerdown_mode =3D mode; + + return 0; +} + +static ssize_t mcp48feb02_read_powerdown(struct iio_dev *indio_dev, uintpt= r_t private, + const struct iio_chan_spec *ch, char *buf) +{ + struct mcp48feb02_data *data =3D iio_priv(indio_dev); + + /* Print if channel is in a power-down mode or not */ + return sysfs_emit(buf, "%d\n", data->chdata[ch->address].powerdown); +} + +static ssize_t mcp48feb02_write_powerdown(struct iio_dev *indio_dev, uintp= tr_t private, + const struct iio_chan_spec *ch, const char *buf, + size_t len) +{ + struct mcp48feb02_data *data =3D iio_priv(indio_dev); + u32 reg =3D ch->address; + u8 tmp_pd_mode; + bool state; + int ret; + + guard(mutex)(&data->lock); + + ret =3D kstrtobool(buf, &state); + if (ret) + return ret; + + /* + * Set the channel to the specified power-down mode. Exiting power-down m= ode + * requires writing normal operation mode (0) to the channel-specific reg= ister bits. + */ + tmp_pd_mode =3D state ? (data->chdata[reg].powerdown_mode + 1) : MCP48FEB= 02_NORMAL_OPERATION; + ret =3D regmap_update_bits(data->regmap, MCP48FEB02_POWER_DOWN_REG_ADDR, + DAC_CTRL_MASK(reg), DAC_CTRL_VAL(reg, tmp_pd_mode)); + if (ret) + return ret; + + data->chdata[reg].powerdown =3D state; + + return len; +} + +static DEFINE_SIMPLE_DEV_PM_OPS(mcp48feb02_pm_ops, mcp48feb02_suspend, mcp= 48feb02_resume); + +static const struct iio_enum mcp48febxx_powerdown_mode_enum =3D { + .items =3D mcp48feb02_powerdown_modes, + .num_items =3D ARRAY_SIZE(mcp48feb02_powerdown_modes), + .get =3D mcp48feb02_get_powerdown_mode, + .set =3D mcp48feb02_set_powerdown_mode, +}; + +static const struct iio_chan_spec_ext_info mcp48feb02_ext_info[] =3D { + { + .name =3D "powerdown", + .read =3D mcp48feb02_read_powerdown, + .write =3D mcp48feb02_write_powerdown, + .shared =3D IIO_SEPARATE, + }, + IIO_ENUM("powerdown_mode", IIO_SEPARATE, &mcp48febxx_powerdown_mode_enum), + IIO_ENUM_AVAILABLE("powerdown_mode", IIO_SHARED_BY_TYPE, &mcp48febxx_powe= rdown_mode_enum), + { } +}; + +static const struct iio_chan_spec mcp48febxx_ch_template =3D { + .type =3D IIO_VOLTAGE, + .output =3D 1, + .indexed =3D 1, + .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), + .info_mask_separate_available =3D BIT(IIO_CHAN_INFO_SCALE), + .ext_info =3D mcp48feb02_ext_info, +}; + +static void mcp48feb02_init_scale(struct mcp48feb02_data *data, enum mcp48= feb02_scale scale, + int vref_uV, int scale_avail[]) +{ + u32 value_micro, value_int; + u64 tmp; + + /* vref_uV should not be negative */ + tmp =3D (u64)vref_uV * MILLI >> data->chip_features->resolution; + value_int =3D div_u64_rem(tmp, MICRO, &value_micro); + scale_avail[scale * 2] =3D value_int; + scale_avail[scale * 2 + 1] =3D value_micro; +} + +static int mcp48feb02_init_scales_avail(struct mcp48feb02_data *data, int = vdd_uV, + int vref_uV, int vref1_uV) +{ + int tmp_vref; + + mcp48feb02_init_scale(data, MCP48FEB02_SCALE_VDD, vdd_uV, data->scale); + + tmp_vref =3D data->use_vref ? vref_uV : MCP48FEB02_INTERNAL_BAND_GAP_uV; + mcp48feb02_init_scale(data, MCP48FEB02_SCALE_GAIN_X1, tmp_vref, data->sca= le); + mcp48feb02_init_scale(data, MCP48FEB02_SCALE_GAIN_X2, tmp_vref * 2, data-= >scale); + + if (data->phys_channels >=3D 4) { + mcp48feb02_init_scale(data, MCP48FEB02_SCALE_VDD, vdd_uV, data->scale_1); + + if (data->use_vref1) + tmp_vref =3D vref1_uV; + else + tmp_vref =3D MCP48FEB02_INTERNAL_BAND_GAP_uV; + + mcp48feb02_init_scale(data, MCP48FEB02_SCALE_GAIN_X1, + tmp_vref, data->scale_1); + mcp48feb02_init_scale(data, MCP48FEB02_SCALE_GAIN_X2, + tmp_vref * 2, data->scale_1); + } + + return 0; +} + +static int mcp48feb02_read_avail(struct iio_dev *indio_dev, struct iio_cha= n_spec const *ch, + const int **vals, int *type, int *length, long info) +{ + struct mcp48feb02_data *data =3D iio_priv(indio_dev); + + switch (info) { + case IIO_CHAN_INFO_SCALE: + switch (ch->type) { + case IIO_VOLTAGE: + if (data->phys_channels >=3D 4 && (ch->address % 2)) + *vals =3D data->scale_1; + else + *vals =3D data->scale; + + *length =3D 2 * MCP48FEB02_MAX_SCALES_CH; + *type =3D IIO_VAL_INT_PLUS_MICRO; + return IIO_AVAIL_LIST; + default: + return -EINVAL; + } + default: + return -EINVAL; + } +} + +static void mcp48feb02_get_scale(int ch, struct mcp48feb02_data *data, int= *val, int *val2) +{ + enum mcp48feb02_scale current_scale; + + if (data->chdata[ch].ref_mode =3D=3D MCP48FEB02_VREF_VDD) + current_scale =3D MCP48FEB02_SCALE_VDD; + else if (data->chdata[ch].use_2x_gain) + current_scale =3D MCP48FEB02_SCALE_GAIN_X2; + else + current_scale =3D MCP48FEB02_SCALE_GAIN_X1; + + if (data->phys_channels >=3D 4 && (ch % 2)) { + *val =3D data->scale_1[current_scale * 2]; + *val2 =3D data->scale_1[current_scale * 2 + 1]; + } else { + *val =3D data->scale[current_scale * 2]; + *val2 =3D data->scale[current_scale * 2 + 1]; + } +} + +static int mcp48feb02_check_scale(struct mcp48feb02_data *data, int val, i= nt val2, int scale[]) +{ + unsigned int i; + + for (i =3D 0; i < MCP48FEB02_MAX_SCALES_CH; i++) { + if (scale[i * 2] =3D=3D val && scale[i * 2 + 1] =3D=3D val2) + return i; + } + + return -EINVAL; +} + +static int mcp48feb02_ch_scale(struct mcp48feb02_data *data, int ch, int s= cale) +{ + int tmp_val, ret; + + if (scale =3D=3D MCP48FEB02_SCALE_VDD) { + tmp_val =3D MCP48FEB02_VREF_VDD; + } else if (data->phys_channels >=3D 4 && (ch % 2)) { + if (data->use_vref1) { + if (data->vref1_buffered) + tmp_val =3D MCP48FEB02_EXTERNAL_VREF_BUFFERED; + else + tmp_val =3D MCP48FEB02_EXTERNAL_VREF_UNBUFFERED; + } else { + tmp_val =3D MCP48FEB02_INTERNAL_BAND_GAP; + } + } else if (data->use_vref) { + if (data->vref_buffered) + tmp_val =3D MCP48FEB02_EXTERNAL_VREF_BUFFERED; + else + tmp_val =3D MCP48FEB02_EXTERNAL_VREF_UNBUFFERED; + } else { + tmp_val =3D MCP48FEB02_INTERNAL_BAND_GAP; + } + + ret =3D regmap_update_bits(data->regmap, MCP48FEB02_VREF_REG_ADDR, + DAC_CTRL_MASK(ch), DAC_CTRL_VAL(ch, tmp_val)); + if (ret) + return ret; + + data->chdata[ch].ref_mode =3D tmp_val; + + return 0; +} + +/* + * Setting the scale in order to choose between VDD and (Vref or Band Gap)= from the user + * space. The VREF pin is either an input or an output, therefore the user= cannot + * simultaneously connect an external voltage reference to the pin and sel= ect the + * internal Band Gap. + * When the DAC=E2=80=99s voltage reference is configured as the VREF pin,= the pin is an input. + * When the DAC=E2=80=99s voltage reference is configured as the internal = Band Gap, + * the VREF pin is an output. + * If Vref/Vref1 voltage is not available, then the internal Band Gap will= be used + * to calculate the values for the scale. + */ +static int mcp48feb02_set_scale(struct mcp48feb02_data *data, int ch, int = scale) +{ + int tmp_val, ret; + + ret =3D mcp48feb02_ch_scale(data, ch, scale); + if (ret) + return ret; + + if (scale =3D=3D MCP48FEB02_SCALE_GAIN_X2) + tmp_val =3D MCP48FEB02_GAIN_BIT_X2; + else + tmp_val =3D MCP48FEB02_GAIN_BIT_X1; + + ret =3D regmap_update_bits(data->regmap, MCP48FEB02_GAIN_CTRL_STATUS_REG_= ADDR, + DAC_GAIN_MASK(ch), DAC_GAIN_VAL(ch, tmp_val)); + if (ret) + return ret; + + data->chdata[ch].use_2x_gain =3D tmp_val; + + return 0; +} + +static int mcp48feb02_read_raw(struct iio_dev *indio_dev, struct iio_chan_= spec const *ch, + int *val, int *val2, long mask) +{ + struct mcp48feb02_data *data =3D iio_priv(indio_dev); + int ret; + + switch (mask) { + case IIO_CHAN_INFO_RAW: + ret =3D regmap_read(data->regmap, REG_ADDR(ch->address), val); + if (ret) + return ret; + return IIO_VAL_INT; + case IIO_CHAN_INFO_SCALE: + mcp48feb02_get_scale(ch->address, data, val, val2); + return IIO_VAL_INT_PLUS_MICRO; + default: + return -EINVAL; + } +} + +static int mcp48feb02_write_raw(struct iio_dev *indio_dev, struct iio_chan= _spec const *ch, + int val, int val2, long mask) +{ + struct mcp48feb02_data *data =3D iio_priv(indio_dev); + int *tmp_scale, ret; + + guard(mutex)(&data->lock); + + switch (mask) { + case IIO_CHAN_INFO_RAW: + ret =3D regmap_write(data->regmap, REG_ADDR(ch->address), val); + if (ret) + return ret; + + data->chdata[ch->address].dac_data =3D val; + return 0; + case IIO_CHAN_INFO_SCALE: + if (data->phys_channels >=3D 4 && (ch->address % 2)) + tmp_scale =3D data->scale_1; + else + tmp_scale =3D data->scale; + + ret =3D mcp48feb02_check_scale(data, val, val2, tmp_scale); + if (ret < 0) + return ret; + + return mcp48feb02_set_scale(data, ch->address, ret); + default: + return -EINVAL; + } +} + +static int mcp48feb02_read_label(struct iio_dev *indio_dev, struct iio_cha= n_spec const *ch, + char *label) +{ + struct mcp48feb02_data *data =3D iio_priv(indio_dev); + + return sysfs_emit(label, "%s\n", data->labels[ch->address]); +} + +static const struct iio_info mcp48feb02_info =3D { + .read_raw =3D mcp48feb02_read_raw, + .write_raw =3D mcp48feb02_write_raw, + .read_label =3D mcp48feb02_read_label, + .read_avail =3D &mcp48feb02_read_avail, + .attrs =3D &mcp48feb02_attribute_group, +}; + +static const struct iio_info mcp48fvb02_info =3D { + .read_raw =3D mcp48feb02_read_raw, + .write_raw =3D mcp48feb02_write_raw, + .read_label =3D mcp48feb02_read_label, + .read_avail =3D &mcp48feb02_read_avail, +}; + +static int mcp48feb02_parse_fw(struct iio_dev *indio_dev, + const struct mcp48feb02_features *chip_features) +{ + struct iio_chan_spec chanspec =3D mcp48febxx_ch_template; + struct mcp48feb02_data *data =3D iio_priv(indio_dev); + struct device *dev =3D regmap_get_device(data->regmap); + struct iio_chan_spec *channels; + u32 num_channels; + u8 chan_idx =3D 0; + + guard(mutex)(&data->lock); + + num_channels =3D device_get_child_node_count(dev); + if (num_channels > chip_features->phys_channels) + return dev_err_probe(dev, -EINVAL, "More channels than the chip supports= \n"); + + if (!num_channels) + return dev_err_probe(dev, -EINVAL, "No channel specified in the devicetr= ee.\n"); + + channels =3D devm_kcalloc(dev, num_channels, sizeof(*channels), GFP_KERNE= L); + if (!channels) + return -ENOMEM; + + device_for_each_child_node_scoped(dev, child) { + u32 reg =3D 0; + int ret; + + ret =3D fwnode_property_read_u32(child, "reg", ®); + if (ret) + return dev_err_probe(dev, ret, "Invalid channel number\n"); + + if (reg >=3D chip_features->phys_channels) + return dev_err_probe(dev, -EINVAL, + "The index of the channels does not match the chip\n"); + + set_bit(reg, &data->active_channels_mask); + + ret =3D fwnode_property_read_string(child, "label", &data->labels[reg]); + if (ret) + return dev_err_probe(dev, ret, "%pfw: invalid label\n", + fwnode_get_name(child)); + + chanspec.address =3D reg; + chanspec.channel =3D reg; + channels[chan_idx] =3D chanspec; + chan_idx++; + } + + indio_dev->num_channels =3D num_channels; + indio_dev->channels =3D channels; + indio_dev->modes =3D INDIO_DIRECT_MODE; + data->phys_channels =3D chip_features->phys_channels; + + data->vref_buffered =3D device_property_read_bool(dev, "microchip,vref-bu= ffered"); + + if (chip_features->have_ext_vref1) + data->vref1_buffered =3D device_property_read_bool(dev, "microchip,vref1= -buffered"); + + return 0; +} + +static int mcp48feb02_init_ctrl_regs(struct mcp48feb02_data *data) +{ + unsigned int i, vref_ch, gain_ch, pd_ch; + int ret; + + ret =3D regmap_read(data->regmap, MCP48FEB02_VREF_REG_ADDR, &vref_ch); + if (ret) + return ret; + + ret =3D regmap_read(data->regmap, MCP48FEB02_GAIN_CTRL_STATUS_REG_ADDR, &= gain_ch); + if (ret) + return ret; + + ret =3D regmap_read(data->regmap, MCP48FEB02_POWER_DOWN_REG_ADDR, &pd_ch); + if (ret) + return ret; + + gain_ch =3D gain_ch & MCP48FEB02_GAIN_BITS_MASK; + for_each_set_bit(i, &data->active_channels_mask, data->phys_channels) { + struct device *dev =3D regmap_get_device(data->regmap); + unsigned int pd_tmp; + + data->chdata[i].ref_mode =3D (vref_ch >> (2 * i)) & MCP48FEB02_DAC_CTRL_= MASK; + data->chdata[i].use_2x_gain =3D (gain_ch >> i) & MCP48FEB02_GAIN_BIT_MA= SK; + + /* + * Inform the user that the current voltage reference read from the vola= tile + * register of the chip is different from the one specified in the devic= e tree. + * Considering that the user cannot have an external voltage reference c= onnected + * to the pin and select the internal Band Gap at the same time, in orde= r to avoid + * miscofiguring the reference voltage, the volatile register will not b= e written. + * In order to overwrite the setting from volatile register with the one= from the + * device tree, the user needs to write the chosen scale. + */ + switch (data->chdata[i].ref_mode) { + case MCP48FEB02_INTERNAL_BAND_GAP: + if (data->phys_channels >=3D 4 && (i % 2) && data->use_vref1) { + dev_dbg(dev, "ch[%u]: was configured to use internal band gap", i); + dev_dbg(dev, "ch[%u]: reference voltage set to VREF1", i); + break; + } + if ((data->phys_channels < 4 || (data->phys_channels >=3D 4 && !(i % 2)= )) && + data->use_vref) { + dev_dbg(dev, "ch[%u]: was configured to use internal band gap", i); + dev_dbg(dev, "ch[%u]: reference voltage set to VREF", i); + break; + } + break; + case MCP48FEB02_EXTERNAL_VREF_UNBUFFERED: + case MCP48FEB02_EXTERNAL_VREF_BUFFERED: + if (data->phys_channels >=3D 4 && (i % 2) && !data->use_vref1) { + dev_dbg(dev, "ch[%u]: was configured to use VREF1", i); + dev_dbg(dev, + "ch[%u]: reference voltage set to internal band gap", i); + break; + } + if ((data->phys_channels < 4 || (data->phys_channels >=3D 4 && !(i % 2)= )) && + !data->use_vref) { + dev_dbg(dev, "ch[%u]: was configured to use VREF", i); + dev_dbg(dev, + "ch[%u]: reference voltage set to internal band gap", i); + break; + } + break; + } + + pd_tmp =3D (pd_ch >> (2 * i)) & MCP48FEB02_DAC_CTRL_MASK; + data->chdata[i].powerdown_mode =3D pd_tmp ? (pd_tmp - 1) : pd_tmp; + data->chdata[i].powerdown =3D !!(data->chdata[i].powerdown_mode); + } + + return 0; +} + +static int mcp48feb02_init_ch_scales(struct mcp48feb02_data *data, int vdd= _uV, + int vref_uV, int vref1_uV) +{ + unsigned int i; + + for_each_set_bit(i, &data->active_channels_mask, data->phys_channels) { + struct device *dev =3D regmap_get_device(data->regmap); + int ret; + + ret =3D mcp48feb02_init_scales_avail(data, vdd_uV, vref_uV, vref1_uV); + if (ret) + return dev_err_probe(dev, ret, "failed to init scales for ch %u\n", i); + } + + return 0; +} + +static int mcp48feb02_probe(struct spi_device *spi) +{ + const struct mcp48feb02_features *chip_features; + struct device *dev =3D &spi->dev; + struct mcp48feb02_data *data; + struct iio_dev *indio_dev; + int vref1_uV =3D 0; + int vref_uV =3D 0; + int vdd_uV; + int ret; + + indio_dev =3D devm_iio_device_alloc(dev, sizeof(*data)); + if (!indio_dev) + return -ENOMEM; + + data =3D iio_priv(indio_dev); + + chip_features =3D spi_get_device_match_data(spi); + if (!chip_features) + return -EINVAL; + + data->chip_features =3D chip_features; + + if (chip_features->have_eeprom) { + data->regmap =3D devm_regmap_init_spi(spi, &mcp48feb02_regmap_config); + indio_dev->info =3D &mcp48feb02_info; + } else { + data->regmap =3D devm_regmap_init_spi(spi, &mcp48fvb02_regmap_config); + indio_dev->info =3D &mcp48fvb02_info; + } + if (IS_ERR(data->regmap)) + return dev_err_probe(dev, PTR_ERR(data->regmap), "Error initializing spi= regmap\n"); + + indio_dev->name =3D chip_features->name; + + ret =3D mcp48feb02_parse_fw(indio_dev, chip_features); + if (ret) + return dev_err_probe(dev, ret, "Error parsing firmware data\n"); + + ret =3D devm_mutex_init(dev, &data->lock); + if (ret) + return ret; + + ret =3D devm_regulator_get_enable_read_voltage(dev, "vdd"); + if (ret < 0) + return ret; + + vdd_uV =3D ret; + + ret =3D devm_regulator_get_enable_read_voltage(dev, "vref"); + if (ret > 0) { + vref_uV =3D ret; + data->use_vref =3D true; + } else { + dev_dbg(dev, "using internal band gap as voltage reference.\n"); + dev_dbg(dev, "External Vref is unavailable.\n"); + } + + if (chip_features->have_ext_vref1) { + ret =3D devm_regulator_get_enable_read_voltage(dev, "vref1"); + if (ret > 0) { + vref1_uV =3D ret; + data->use_vref1 =3D true; + } else { + dev_dbg(dev, "using internal band gap as voltage reference 1.\n"); + dev_dbg(dev, "External Vref1 is unavailable.\n"); + } + } + + ret =3D mcp48feb02_init_ctrl_regs(data); + if (ret) + return dev_err_probe(dev, ret, "Error initialising vref register\n"); + + ret =3D mcp48feb02_init_ch_scales(data, vdd_uV, vref_uV, vref1_uV); + if (ret) + return ret; + + return devm_iio_device_register(dev, indio_dev); +} + +static const struct spi_device_id mcp48feb02_id[] =3D { + { "mcp48feb01", (kernel_ulong_t)&mcp48feb01_chip_features }, + { "mcp48feb02", (kernel_ulong_t)&mcp48feb02_chip_features }, + { "mcp48feb04", (kernel_ulong_t)&mcp48feb04_chip_features }, + { "mcp48feb08", (kernel_ulong_t)&mcp48feb08_chip_features }, + { "mcp48feb11", (kernel_ulong_t)&mcp48feb11_chip_features }, + { "mcp48feb12", (kernel_ulong_t)&mcp48feb12_chip_features }, + { "mcp48feb14", (kernel_ulong_t)&mcp48feb14_chip_features }, + { "mcp48feb18", (kernel_ulong_t)&mcp48feb18_chip_features }, + { "mcp48feb21", (kernel_ulong_t)&mcp48feb21_chip_features }, + { "mcp48feb22", (kernel_ulong_t)&mcp48feb22_chip_features }, + { "mcp48feb24", (kernel_ulong_t)&mcp48feb24_chip_features }, + { "mcp48feb28", (kernel_ulong_t)&mcp48feb28_chip_features }, + { "mcp48fvb01", (kernel_ulong_t)&mcp48fvb01_chip_features }, + { "mcp48fvb02", (kernel_ulong_t)&mcp48fvb02_chip_features }, + { "mcp48fvb04", (kernel_ulong_t)&mcp48fvb04_chip_features }, + { "mcp48fvb08", (kernel_ulong_t)&mcp48fvb08_chip_features }, + { "mcp48fvb11", (kernel_ulong_t)&mcp48fvb11_chip_features }, + { "mcp48fvb12", (kernel_ulong_t)&mcp48fvb12_chip_features }, + { "mcp48fvb14", (kernel_ulong_t)&mcp48fvb14_chip_features }, + { "mcp48fvb18", (kernel_ulong_t)&mcp48fvb18_chip_features }, + { "mcp48fvb21", (kernel_ulong_t)&mcp48fvb21_chip_features }, + { "mcp48fvb22", (kernel_ulong_t)&mcp48fvb22_chip_features }, + { "mcp48fvb24", (kernel_ulong_t)&mcp48fvb24_chip_features }, + { "mcp48fvb28", (kernel_ulong_t)&mcp48fvb28_chip_features }, + { } +}; +MODULE_DEVICE_TABLE(spi, mcp48feb02_id); + +static const struct of_device_id mcp48feb02_of_match[] =3D { + { .compatible =3D "microchip,mcp48feb01", .data =3D &mcp48feb01_chip_feat= ures }, + { .compatible =3D "microchip,mcp48feb02", .data =3D &mcp48feb02_chip_feat= ures }, + { .compatible =3D "microchip,mcp48feb04", .data =3D &mcp48feb04_chip_feat= ures }, + { .compatible =3D "microchip,mcp48feb08", .data =3D &mcp48feb08_chip_feat= ures }, + { .compatible =3D "microchip,mcp48feb11", .data =3D &mcp48feb11_chip_feat= ures }, + { .compatible =3D "microchip,mcp48feb12", .data =3D &mcp48feb12_chip_feat= ures }, + { .compatible =3D "microchip,mcp48feb14", .data =3D &mcp48feb14_chip_feat= ures }, + { .compatible =3D "microchip,mcp48feb18", .data =3D &mcp48feb18_chip_feat= ures }, + { .compatible =3D "microchip,mcp48feb21", .data =3D &mcp48feb21_chip_feat= ures }, + { .compatible =3D "microchip,mcp48feb22", .data =3D &mcp48feb22_chip_feat= ures }, + { .compatible =3D "microchip,mcp48feb24", .data =3D &mcp48feb24_chip_feat= ures }, + { .compatible =3D "microchip,mcp48feb28", .data =3D &mcp48feb28_chip_feat= ures }, + { .compatible =3D "microchip,mcp48fvb01", .data =3D &mcp48fvb01_chip_feat= ures }, + { .compatible =3D "microchip,mcp48fvb02", .data =3D &mcp48fvb02_chip_feat= ures }, + { .compatible =3D "microchip,mcp48fvb04", .data =3D &mcp48fvb04_chip_feat= ures }, + { .compatible =3D "microchip,mcp48fvb08", .data =3D &mcp48fvb08_chip_feat= ures }, + { .compatible =3D "microchip,mcp48fvb11", .data =3D &mcp48fvb11_chip_feat= ures }, + { .compatible =3D "microchip,mcp48fvb12", .data =3D &mcp48fvb12_chip_feat= ures }, + { .compatible =3D "microchip,mcp48fvb14", .data =3D &mcp48fvb14_chip_feat= ures }, + { .compatible =3D "microchip,mcp48fvb18", .data =3D &mcp48fvb18_chip_feat= ures }, + { .compatible =3D "microchip,mcp48fvb21", .data =3D &mcp48fvb21_chip_feat= ures }, + { .compatible =3D "microchip,mcp48fvb22", .data =3D &mcp48fvb22_chip_feat= ures }, + { .compatible =3D "microchip,mcp48fvb24", .data =3D &mcp48fvb24_chip_feat= ures }, + { .compatible =3D "microchip,mcp48fvb28", .data =3D &mcp48fvb28_chip_feat= ures }, + { } +}; +MODULE_DEVICE_TABLE(of, mcp48feb02_of_match); + +static struct spi_driver mcp48feb02_driver =3D { + .driver =3D { + .name =3D "mcp48feb02", + .of_match_table =3D mcp48feb02_of_match, + .pm =3D pm_sleep_ptr(&mcp48feb02_pm_ops), + }, + .probe =3D mcp48feb02_probe, + .id_table =3D mcp48feb02_id, +}; +module_spi_driver(mcp48feb02_driver); + +MODULE_AUTHOR("Ariana Lazar "); +MODULE_DESCRIPTION("IIO driver for MCP48FEB02 Multi-Channel DAC with SPI i= nterface"); +MODULE_LICENSE("GPL"); --=20 2.43.0