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Wed, 11 Feb 2026 13:34:43 +0100 (CET) From: Alexander Stein To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Peter Chen , Pawel Laszczak , Roger Quadros , Greg Kroah-Hartman , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Magnus Damm , Marek Vasut Cc: Alexander Stein , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-usb@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux@ew.tq-group.com Subject: [PATCH v2 1/5] dt-bindings: usb: cdns,usb3: support USB devices in DT Date: Wed, 11 Feb 2026 13:34:28 +0100 Message-ID: <20260211123436.1077513-2-alexander.stein@ew.tq-group.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260211123436.1077513-1-alexander.stein@ew.tq-group.com> References: <20260211123436.1077513-1-alexander.stein@ew.tq-group.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-cloud-security-sender: alexander.stein@ew.tq-group.com X-cloud-security-recipient: linux-kernel@vger.kernel.org X-cloud-security-crypt: load encryption module X-cloud-security-Mailarchiv: E-Mail archived for: alexander.stein@ew.tq-group.com X-cloud-security-Mailarchivtype: outbound X-cloud-security-Virusscan: CLEAN X-cloud-security-disclaimer: This E-Mail was scanned by E-Mailservice on mx-relay128-hz1.antispameurope.com with 4f9yYc4gf8zvb1m X-cloud-security-connect: he-nlb01-hz1.hornetsecurity.com[94.100.132.6], TLS=1, IP=94.100.132.6 X-cloud-security-Digest: 127a990275954f2aedbe66286a895387 X-cloud-security: scantime:2.345 DKIM-Signature: a=rsa-sha256; bh=ezwBTEGDVrkTw7utJMNRHdCflzlp+turEuzGuTHPmd0=; c=relaxed/relaxed; d=ew.tq-group.com; h=content-type:mime-version:subject:from:to:message-id:date; s=hse1; t=1770813310; v=1; b=MM0xqkRiSrFKu26hl3iDi6zqDIDgi7p5Sfk0Xew86JGsVJYnKJr3+wp8fucown9rKaNzYejb dwIfOYWy/++KKoore6nHbx0efQ2D9rnzxCuqVT7uEDYqgjrLmFUsXSrcQB56bo37m9XPcyzckiB r+LzVKbthc6XrqU7cHQs0cQzMIk3M6lkmf4zP6DQtMt5LDWyLb5nUrQyawqtippt5LrMWoE45xW u4zw/ufetswTWH4gLCxSkrS051xLyvV2EeF4yEl7cCpKbuY3PySaYdXdKkoK8aN0HLjp4IYnOU7 VAWEQq9mRlVaDuYYEk9KdSaEClx/I9OvxZyqX1FFIuLHA== Content-Type: text/plain; charset="utf-8" Reference usb-hxci.yaml in host mode in order to support on-board USB hubs. Signed-off-by: Alexander Stein Reviewed-by: Rob Herring (Arm) --- Changes in v2: * reference usb-xhci.yaml# directly (suggested by Rob) Documentation/devicetree/bindings/usb/cdns,usb3.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/usb/cdns,usb3.yaml b/Documen= tation/devicetree/bindings/usb/cdns,usb3.yaml index f454ddd9bbaa6..a199e5ba64161 100644 --- a/Documentation/devicetree/bindings/usb/cdns,usb3.yaml +++ b/Documentation/devicetree/bindings/usb/cdns,usb3.yaml @@ -85,6 +85,7 @@ required: =20 allOf: - $ref: usb-drd.yaml# + - $ref: usb-xhci.yaml# =20 unevaluatedProperties: false =20 --=20 2.43.0 From nobody Sat Apr 18 03:25:38 2026 Received: from mx-relay50-hz3.antispameurope.com (mx-relay50-hz3.antispameurope.com [94.100.134.239]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E57871D7995 for ; Wed, 11 Feb 2026 12:35:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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bh=p7pDwaK17CdUZh/u5Iy4Xmvwxf0XguEjLtkZgT9LWWU=; c=relaxed/relaxed; d=ew.tq-group.com; h=content-type:mime-version:subject:from:to:message-id:date; s=hse1; t=1770813310; v=1; b=CAM7zrWVMNAcDXkOgq0zqQgb2xiHKxpmA0VW+OTY7hwsxuINXjkmZ77k8wwPvNaL5W8sInAY Yb0ocNiEnNSNXsAcXv/BnVt4hsfLMn/86iEP5YA1AFYLDIDcXaWF6EnbPsr0vk1DW/XjyFcW9M9 tfMbZnY9meEzrgngR/2sK/iBHRz122CyehcOeeSadbrAgpeuY4C8vt0j+BmDZjNsliw7t6YNhNM kkUMP5IckN47AQR3oJNhOtauY+7Dy+aWtOqkJ2RcJXqMs9b0h1c1u/Ts52lWyFb+C9ZHvB1BLi7 zRNcxg0u6ITeZaJGBDlHNx8fRyFQ/SUH4+pDk6bS4i02A== Content-Type: text/plain; charset="utf-8" IRQ mapping is already present. Add the missing DMA interrupt. This is similar to commit 0b4c46f9ad79c ("arm64: dts: imx8qm-ss-hsio: Wire up DMA IRQ for PCIe") Signed-off-by: Alexander Stein --- Changes in v2: * None arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi b/arch/arm64= /boot/dts/freescale/imx8qm-ss-hsio.dtsi index bd6e0aa27efe9..f2c94cdb682b9 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi @@ -20,8 +20,9 @@ pcie0: pciea: pcie@5f000000 { ranges =3D <0x81000000 0 0x00000000 0x4ff80000 0 0x00010000>, <0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; #interrupt-cells =3D <1>; - interrupts =3D ; - interrupt-names =3D "msi"; + interrupts =3D , + ; + interrupt-names =3D "msi", "dma"; #address-cells =3D <3>; #size-cells =3D <2>; clocks =3D <&pciea_lpcg IMX_LPCG_CLK_6>, --=20 2.43.0 From nobody Sat Apr 18 03:25:38 2026 Received: from mx-relay95-hz2.antispameurope.com (mx-relay95-hz2.antispameurope.com [94.100.136.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5E104313287 for ; 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bh=ls/S0m9WGUgqWCy8vJncgSdsx/isbkuq3kh3sRBurJc=; c=relaxed/relaxed; d=ew.tq-group.com; h=content-type:mime-version:subject:from:to:message-id:date; s=hse1; t=1770813305; v=1; b=NP7Vz1R3MLOAA8x2mEoE54BvoJFZu3wMDMn3VmUYzkObCp0EIAj3SpUUXMBciLsE9W0hhL5C qFQKqGQ118EwQSrHlp2zLCg7WmkKBskoNBX10sBV7lvosJ2MVZZ8DDqOec7u4ZWvu+4/AsE9B8M v6foBJQqGbk7H50D42L/RUqWtoBBwYHeaBKO27TQxxrsnyVJ5yD5vn8VYfm/DaTq81Jhe6Ti6ql zevIkGINTIdU/ENe4iCFvJBlhfiH7g185dwbi4aKMoMEDhGpKDz5IU3+DfX+XxIW+vQg/uNGxik WjVvI+bN3D5g8FsUcgCwBALRiC0/LlDFJI+CvvhbE0Cmg== Content-Type: text/plain; charset="utf-8" TQMa8x is a SOM family using NXP i.MX8QM CPU family MBa8x is an evaluation mainboard for this SOM. Signed-off-by: Markus Niebel Signed-off-by: Alexander Stein Reviewed-by: Rob Herring (Arm) --- Changes in v2: * Collected Rob's R-b Documentation/devicetree/bindings/arm/fsl.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation= /devicetree/bindings/arm/fsl.yaml index 5716d701292cf..ad6edd75c4ff7 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1420,6 +1420,16 @@ properties: - const: tq,imx8dxp-tqma8xdps # TQ-Systems GmbH TQMa= 8XDPS SOM - const: fsl,imx8dxp =20 + - description: + TQMa8x is a series of SOM featuring NXP i.MX8 system-on-chip + variants. It is designed to be clicked on different carrier boar= ds + MBa8x is the starterkit + items: + - enum: + - tq,imx8qm-tqma8qm-mba8x # TQ-Systems GmbH TQMa8QM SOM on= MBa8x + - const: tq,imx8qm-tqma8qm # TQ-Systems GmbH TQMa8QM SOM + - const: fsl,imx8qm + - description: i.MX8ULP based Boards items: - enum: --=20 2.43.0 From nobody Sat Apr 18 03:25:38 2026 Received: from mx-relay28-hz2.antispameurope.com (mx-relay28-hz2.antispameurope.com [94.100.136.228]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 636EE314D1A for ; Wed, 11 Feb 2026 12:36:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=94.100.136.228 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770813372; cv=pass; b=J85lOBJd7pfHX3/Ba6h/avTmBn7KhX06Vi8UkpkqxWkJOif951IagBfIw0uXPwrccRvUBQnGQlGzaMtCDAogSUBk9Gu/xZDXT03BMqJiaZZVfl3ruTJZTLJYz6cRrpZdPHS+o/gZTEJTuFEYSRuaHGiTvknbBEc9WbpBa5WXdc4= ARC-Message-Signature: i=2; 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Wed, 11 Feb 2026 13:35:16 +0100 Received: from steina-w.tq-net.de (host-82-135-125-110.customer.m-online.net [82.135.125.110]) (Authenticated sender: alexander.stein@ew.tq-group.com) by smtp-out02-hz1.hornetsecurity.com (Postfix) with ESMTPSA id C11945A1333; Wed, 11 Feb 2026 13:34:49 +0100 (CET) From: Alexander Stein To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Peter Chen , Pawel Laszczak , Roger Quadros , Greg Kroah-Hartman , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Magnus Damm , Marek Vasut , Frank Li Cc: Alexander Stein , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-usb@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux@ew.tq-group.com Subject: [PATCH v2 4/5] arm64: dts: freescale: add initial device tree for TQMa8x Date: Wed, 11 Feb 2026 13:34:31 +0100 Message-ID: <20260211123436.1077513-5-alexander.stein@ew.tq-group.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260211123436.1077513-1-alexander.stein@ew.tq-group.com> References: <20260211123436.1077513-1-alexander.stein@ew.tq-group.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-cloud-security-sender: alexander.stein@ew.tq-group.com X-cloud-security-recipient: linux-kernel@vger.kernel.org X-cloud-security-crypt: load encryption module X-cloud-security-Mailarchiv: E-Mail archived for: alexander.stein@ew.tq-group.com X-cloud-security-Mailarchivtype: outbound X-cloud-security-Virusscan: CLEAN X-cloud-security-disclaimer: This E-Mail was scanned by E-Mailservice on mx-relay28-hz2.antispameurope.com with 4f9yYl0nDlz1QNZy X-cloud-security-connect: he-nlb01-hz1.hornetsecurity.com[94.100.132.6], TLS=1, IP=94.100.132.6 X-cloud-security-Digest: 3427502e0e251c62168e56b279964177 X-cloud-security: scantime:2.054 DKIM-Signature: a=rsa-sha256; bh=E6oSjXXSV/K8M0NRTvuCWaGAuZ8lWgYMAk8/fzWQAw0=; c=relaxed/relaxed; d=ew.tq-group.com; h=content-type:mime-version:subject:from:to:message-id:date; s=hse1; t=1770813316; v=1; b=H4u73Z3zS0e7XI9GZcYmWPqo/TSR4er1ltrEj8uUJ6Su/QglVmRhhj+vk9SIP0lS13mTXEbU dGjS28qFQfjoMz7Aoui1VPRlvVbV/viLQ6FpzcGf8B70BuLUqGPY0vsalv80Yc53ITHQgaG8cPf dbN6NnbsVRApXTdIzIiT6acFXNzoO1JEmPA8XIC57gYE9nllz/X5VofV+wuvSXfgRzlR5wFCMtX STsZt+hswgFBTwtWHp7+6W1rXXrfX6o8d5zhTxPrZna4jPguXU5LOgoDeldTDb/Rrzl2DBOFMiJ Cl8soVOeMIzov/hLrKaFd615zW/kf83CGToZrYICsdKTw== Content-Type: text/plain; charset="utf-8" This adds support for TQMa8QM module on MBa8x board, based on i.MX8 SoC. Signed-off-by: Alexander Stein --- Changes in v2: * Improved commit message to include more information. * Updated copyright year * Added bindings includes directly used * Removed Ethernet magic packet wakeup * Enbaled SATA interface * Reworked PCIe reference clocking * Aligned pinmux/padctrl alignments arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx8qm-tqma8qm-mba8x.dts | 908 ++++++++++++++++++ .../boot/dts/freescale/imx8qm-tqma8qm.dtsi | 318 ++++++ 3 files changed, 1227 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-tqma8qm-mba8x.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-tqma8qm.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/f= reescale/Makefile index ef9a9d865b445..5d54a713d5600 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -374,6 +374,7 @@ dtb-$(CONFIG_ARCH_MXC) +=3D imx8qm-apalis-v1.1-eval-v1.= 2.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8qm-apalis-v1.1-ixora-v1.1.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8qm-apalis-v1.1-ixora-v1.2.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8qm-mek.dtb +dtb-$(CONFIG_ARCH_MXC) +=3D imx8qm-tqma8qm-mba8x.dtb =20 imx8qm-mek-ov5640-csi0-dtbs :=3D imx8qm-mek.dtb imx8qm-mek-ov5640-csi0.dtbo dtb-${CONFIG_ARCH_MXC} +=3D imx8qm-mek-ov5640-csi0.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8qm-tqma8qm-mba8x.dts b/arch/= arm64/boot/dts/freescale/imx8qm-tqma8qm-mba8x.dts new file mode 100644 index 0000000000000..ce5a4657c4230 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-tqma8qm-mba8x.dts @@ -0,0 +1,908 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2019-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + */ + +/dts-v1/; + +#include +#include +#include +#include +#include + +#include "imx8qm-tqma8qm.dtsi" + +/ { + model =3D "TQ-Systems i.MX8QM TQMa8QM on MBa8x"; + compatible =3D "tq,imx8qm-tqma8qm-mba8x", "tq,imx8qm-tqma8qm", "fsl,imx8q= m"; + + aliases { + rtc0 =3D &pcf85063; + rtc1 =3D &rtc; + }; + + chosen { + stdout-path =3D &lpuart0; + }; + + adc { + compatible =3D "iio-hwmon"; + io-channels =3D <&adc0 0>, <&adc0 1>, <&adc0 2>; + }; + + clk_xtal25: clk-xtal25 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <25000000>; + }; + + fan0: pwm-fan { + compatible =3D "pwm-fan"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pwmfan>; + fan-supply =3D <®_pwm_fan>; + #cooling-cells =3D <2>; + /* typical 25 kHz -> 40.000 nsec */ + pwms =3D <&lsio_pwm3 0 40000 PWM_POLARITY_INVERTED>; + cooling-levels =3D <0 32 64 128 196 240>; + pulses-per-revolution =3D <2>; + interrupt-parent =3D <&lsio_gpio2>; + interrupts =3D <20 IRQ_TYPE_EDGE_FALLING>; + status =3D "disabled"; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_gpiokeys>; + autorepeat; + + switch-1 { + label =3D "SWITCH_A"; + linux,code =3D ; + gpios =3D <&lsio_gpio2 11 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + switch-2 { + label =3D "SWITCH_B"; + linux,code =3D ; + gpios =3D <&lsio_gpio1 0 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + + gpio-leds { + compatible =3D "gpio-leds"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_gpioled>; + + user-led0 { + color =3D ; + function =3D LED_FUNCTION_HEARTBEAT; + gpios =3D <&lsio_gpio5 20 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "heartbeat"; + }; + + user-led1 { + color =3D ; + function =3D LED_FUNCTION_STATUS; + gpios =3D <&lsio_gpio5 19 GPIO_ACTIVE_HIGH>; + default-state =3D "on"; + }; + }; + + reg_mba8x_v3v3: regulator-mba8x-v3v3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "V_3V3_MB"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + }; + + reg_mba8x_12v: regulator-mba8x-12v { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_reg_mba8x_12v>; + regulator-name =3D "MBa8x-V12"; + regulator-min-microvolt =3D <12000000>; + regulator-max-microvolt =3D <12000000>; + enable-active-high; + gpio =3D <&lsio_gpio1 2 GPIO_ACTIVE_HIGH>; + }; + + reg_pwm_fan: regulator-pwm-fan { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_regpwmfan>; + regulator-name =3D "FAN_PWR"; + regulator-min-microvolt =3D <12000000>; + regulator-max-microvolt =3D <12000000>; + gpio =3D <&lsio_gpio2 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply =3D <®_mba8x_12v>; + }; + + reg_usb_phy: regulator-usb-phy { + compatible =3D "regulator-fixed"; + regulator-max-microvolt =3D <3000000>; + regulator-min-microvolt =3D <3000000>; + regulator-name =3D "usb-phy-dummy"; + }; + + reg_v1v5_pcie: regulator-v1v5-pcie { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_reg_pcie_v1v5>; + regulator-name =3D "V_1V5_MPCIE"; + regulator-min-microvolt =3D <1500000>; + regulator-max-microvolt =3D <1500000>; + vin-supply =3D <®_mba8x_v3v3>; + enable-active-high; + gpio =3D <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>; + regulator-always-on; + }; + + reg_vref_v1v8: regulator-vref-v1v8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "VREF_V1V8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-always-on; + }; + + reg_v1v8: regulator-v1v8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "MBa8x-V1V8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-always-on; + }; + + reg_v3v3_pcie: regulator-v3v3-pcie { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_reg_pcie_v3v3>; + regulator-name =3D "V_3V3_MPCIE"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <®_mba8x_v3v3>; + enable-active-high; + gpio =3D <&lsio_gpio1 1 GPIO_ACTIVE_HIGH>; + regulator-always-on; + }; + + reg_v3v3_sd: regulator-v3v3-sd { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_reg_v3v3_sd>; + regulator-name =3D "V3V3_SD"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <®_mba8x_v3v3>; + gpio =3D <&lsio_gpio4 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + off-on-delay-us =3D <200000>; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + decoder_boot: decoder-boot@84000000 { + reg =3D <0 0x84000000 0 0x2000000>; + no-map; + }; + + encoder1_boot: encoder1-boot@86000000 { + reg =3D <0 0x86000000 0 0x200000>; + no-map; + }; + + encoder2_boot: encoder2-boot@86200000 { + reg =3D <0 0x86200000 0 0x200000>; + no-map; + }; + + decoder_rpc: decoder-rpc@92000000 { + reg =3D <0 0x92000000 0 0x100000>; + no-map; + }; + + encoder1_rpc: encoder1-rpc@92100000 { + reg =3D <0 0x92100000 0 0x700000>; + no-map; + }; + + encoder2_rpc: encoder1-rpc@92800000 { + reg =3D <0 0x92800000 0 0x700000>; + no-map; + }; + + /* + * global autoconfigured region for contiguous allocations + * must not exceed memory size and region + */ + linux,cma { + compatible =3D "shared-dma-pool"; + reusable; + size =3D <0 0x3c000000>; + alloc-ranges =3D <0 0x96000000 0 0x3c000000>; + linux,cma-default; + }; + }; + + sound { + compatible =3D "fsl,imx-audio-tlv320aic32x4"; + model =3D "tqm-tlv320aic32"; + ssi-controller =3D <&sai1>; + audio-codec =3D <&tlv320aic3x04>; + audio-routing =3D + "IN3_L", "Mic Jack", + "Mic Jack", "Mic Bias", + "IN1_L", "Line In Jack", + "IN1_R", "Line In Jack", + "Line Out Jack", "LOL", + "Line Out Jack", "LOR"; + }; + + sound-hdmi { + compatible =3D "fsl,imx-audio-hdmi"; + model =3D "imx-audio-dp"; + audio-cpu =3D <&sai5>; + hdmi-out; + }; + + thermal-zones { + cpu0-thermal { + trips { + soc_active0_0: trip-active0 { + temperature =3D <40000>; + hysteresis =3D <5000>; + type =3D "active"; + }; + + soc_active0_1: trip-active1 { + temperature =3D <48000>; + hysteresis =3D <3000>; + type =3D "active"; + }; + + soc_active0_2: trip-active2 { + temperature =3D <60000>; + hysteresis =3D <10000>; + type =3D "active"; + }; + }; + + cooling-maps { + map1 { + trip =3D <&soc_active0_0>; + cooling-device =3D <&fan0 1 1>; + }; + + map2 { + trip =3D <&soc_active0_1>; + cooling-device =3D <&fan0 2 2>; + }; + + map3 { + trip =3D <&soc_active0_2>; + cooling-device =3D <&fan0 3 3>; + }; + }; + }; + + cpu1-thermal { + trips { + soc_active1_0: trip-active0 { + temperature =3D <40000>; + hysteresis =3D <5000>; + type =3D "active"; + }; + + soc_active1_1: trip-active1 { + temperature =3D <48000>; + hysteresis =3D <3000>; + type =3D "active"; + }; + + soc_active1_2: trip-active2 { + temperature =3D <60000>; + hysteresis =3D <10000>; + type =3D "active"; + }; + }; + + cooling-maps { + map1 { + trip =3D <&soc_active1_0>; + cooling-device =3D <&fan0 1 1>; + }; + + map2 { + trip =3D <&soc_active1_1>; + cooling-device =3D <&fan0 2 2>; + }; + + map3 { + trip =3D <&soc_active1_2>; + cooling-device =3D <&fan0 3 3>; + }; + }; + }; + }; +}; + +&fec1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_fec1>; + phy-mode =3D "rgmii-id"; + phy-handle =3D <ðphy0>; + nvmem-cells =3D <&fec_mac0>; + nvmem-cell-names =3D "mac-address"; + status =3D "okay"; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + ethphy0: ethernet-phy@0 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_ethphy0>; + ti,rx-internal-delay =3D ; + ti,tx-internal-delay =3D ; + ti,fifo-depth =3D ; + ti,dp83867-rxctrl-strap-quirk; + ti,clk-output-sel =3D ; + reset-gpios =3D <&lsio_gpio2 6 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <500000>; + reset-deassert-us =3D <50000>; + enet-phy-lane-no-swap; + interrupt-parent =3D <&lsio_gpio2>; + interrupts =3D <8 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + +&fec2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_fec2>; + phy-mode =3D "rgmii-id"; + phy-handle =3D <ðphy3>; + nvmem-cells =3D <&fec_mac1>; + nvmem-cell-names =3D "mac-address"; + status =3D "okay"; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + ethphy3: ethernet-phy@3 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <3>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_ethphy3>; + ti,rx-internal-delay =3D ; + ti,tx-internal-delay =3D ; + ti,fifo-depth =3D ; + ti,dp83867-rxctrl-strap-quirk; + ti,clk-output-sel =3D ; + reset-gpios =3D <&lsio_gpio2 4 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <500000>; + reset-deassert-us =3D <50000>; + enet-phy-lane-no-swap; + }; + }; +}; + +&flexcan1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_flexcan1>; + xceiver-supply =3D <®_mba8x_v3v3>; + status =3D "okay"; +}; + +&flexcan2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_flexcan2>; + xceiver-supply =3D <®_mba8x_v3v3>; + status =3D "okay"; +}; + +&hsio_phy { + fsl,hsio-cfg =3D "pciea-pcieb-sata"; + fsl,refclk-pad-mode =3D "input"; + status =3D "okay"; +}; + +/* no refclock gating */ +&hsio_refa_clk { + compatible =3D "fixed-factor-clock"; + clocks =3D <&pcieclk 0>; + clock-div =3D <1>; + clock-mult =3D <1>; + /delete-property/ enable-gpios; +}; + +&hsio_refb_clk { + compatible =3D "fixed-factor-clock"; + clocks =3D <&pcieclk 0>; + clock-div =3D <1>; + clock-mult =3D <1>; + /delete-property/ enable-gpios; +}; + +&i2c1 { + tlv320aic3x04: audio-codec@18 { + compatible =3D "ti,tlv320aic32x4"; + reg =3D <0x18>; + clocks =3D <&mclkout0_lpcg IMX_LPCG_CLK_0>; + clock-names =3D "mclk"; + assigned-clocks =3D <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg IMX_LPCG_CLK_0>; + assigned-clock-rates =3D <786432000>, <49152000>, <12288000>, <12288000>; + ldoin-supply =3D <®_mba8x_v3v3>; + iov-supply =3D <®_v1v8>; + }; + + sensor1: temperature-sensor@1c { + compatible =3D "nxp,se97b", "jedec,jc-42.4-temp"; + reg =3D <0x1c>; + }; + + eeprom2: eeprom@54 { + compatible =3D "nxp,se97b", "atmel,24c02"; + reg =3D <0x54>; + pagesize =3D <16>; + vcc-supply =3D <®_mba8x_v3v3>; + }; + + pcieclk: clock-generator@68 { + compatible =3D "renesas,9fgv0441"; + reg =3D <0x68>; + clocks =3D <&clk_xtal25>; + #clock-cells =3D <1>; + }; +}; + +&lpspi0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_lpspi0 &pinctrl_lpspi0_cs>; + cs-gpios =3D <&lsio_gpio3 5 GPIO_ACTIVE_LOW>, <&lsio_gpio3 6 GPIO_ACTIVE_= LOW>; + status =3D "okay"; +}; + +&lpspi1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_lpspi1 &pinctrl_lpspi1_cs>; + cs-gpios =3D <&lsio_gpio3 24 GPIO_ACTIVE_LOW>, <&lsio_gpio3 25 GPIO_ACTIV= E_LOW>; + status =3D "okay"; +}; + +&lpspi2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_lpspi2 &pinctrl_lpspi2_cs>; + cs-gpios =3D <&lsio_gpio3 10 GPIO_ACTIVE_LOW>, <&lsio_gpio3 11 GPIO_ACTIV= E_LOW>; + status =3D "okay"; +}; + +&lpuart0 { /* console */ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_lpuart0>; + status =3D "okay"; +}; + +&lpuart1 { /* X62 pin header */ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_lpuart1>; + status =3D "okay"; +}; + +&lpuart2 { /* mikroBUS */ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_lpuart2>; + status =3D "okay"; +}; + +&lsio_gpio2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_gpio2>; + gpio-line-names =3D "", "", "", "", + "", "PCIE0_DISABLE#", "", ""; + + pcie0-wdisable1-hog { + gpio-hog; + gpios =3D <5 0>; + output-high; + line-name =3D "PCIE0_DISABLE#"; + }; + + pcie-clk-pd-hog { + gpio-hog; + gpios =3D <10 0>; + output-high; + line-name =3D "PCIE_CLK_PD#"; + }; +}; + +&lsio_pwm3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_lsio_pwm3>; + status =3D "okay"; +}; + +&pciea { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pciea>; + phys =3D <&hsio_phy 0 PHY_TYPE_PCIE 0>; + phy-names =3D "pcie-phy"; + reset-gpio =3D <&lsio_gpio4 29 GPIO_ACTIVE_LOW>; + status =3D "okay"; +}; + +&pcieb { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pcieb>; + phys =3D <&hsio_phy 1 PHY_TYPE_PCIE 1>; + phy-names =3D "pcie-phy"; + reset-gpio =3D <&lsio_gpio5 0 GPIO_ACTIVE_LOW>; + status =3D "okay"; +}; + +&sai1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_sai1>; + assigned-clocks =3D <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai1_lpcg IMX_LPCG_CLK_0>; + assigned-clock-rates =3D <786432000>, <49152000>, <12288000>, <49152000>; + status =3D "okay"; +}; + +&sai5 { + status =3D "okay"; +}; + +&sai5_lpcg { + status =3D "okay"; +}; + +&sata { + status =3D "okay"; +}; + +&usbphy1 { + phy-3p0-supply =3D <®_usb_phy>; + status =3D "okay"; +}; + +&usbotg1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_usbotg1>; + srp-disable; + hnp-disable; + adp-disable; + power-active-high; + over-current-active-low; + dr_mode =3D "otg"; + status =3D "okay"; +}; + +&usb3_phy { + status =3D "okay"; +}; + +&usbotg3 { + /* over-current disabled by default */ + status =3D "okay"; +}; + +&usbotg3_cdns3 { + dr_mode =3D "host"; + #address-cells =3D <1>; + #size-cells =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_usbhub>; + status =3D "okay"; + + hub_2_0: hub@1 { + compatible =3D "usb451,8142"; + reg =3D <1>; + peer-hub =3D <&hub_3_0>; + reset-gpios =3D <&lsio_gpio2 7 GPIO_ACTIVE_LOW>; + vdd-supply =3D <®_mba8x_v3v3>; + }; + + hub_3_0: hub@2 { + compatible =3D "usb451,8140"; + reg =3D <2>; + peer-hub =3D <&hub_2_0>; + reset-gpios =3D <&lsio_gpio2 7 GPIO_ACTIVE_LOW>; + vdd-supply =3D <®_mba8x_v3v3>; + }; +}; + +&usdhc2 { + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 =3D <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 =3D <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width =3D <4>; + cd-gpios =3D <&lsio_gpio5 22 GPIO_ACTIVE_LOW>; + wp-gpios =3D <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>; + vmmc-supply =3D <®_v3v3_sd>; + no-mmc; + no-sdio; + status =3D "okay"; +}; + +&iomuxc { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_gpio>; + + pinctrl_adc0: adc0grp { + fsl,pins =3D , + ; + }; + + pinctrl_ethphy0: ethphy0grp { + fsl,pins =3D , + ; + }; + + pinctrl_ethphy3: ethphy3grp { + fsl,pins =3D ; + }; + + pinctrl_fec1: fec1grp { + fsl,pins =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_fec2: fec2grp { + fsl,pins =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_flexcan1: flexcan0grp { + fsl,pins =3D , + ; + }; + + pinctrl_flexcan2: flexcan1grp { + fsl,pins =3D , + ; + }; + + pinctrl_gpio: pingpiogrp { + fsl,pins =3D /* GPIO0_05 on X62:26 */ + , + /* GPIO1_14 on X64:21 */ + , + /* GPIO1_15 on X64:23 */ + , + /* GPIO2_17 on X63:37 */ + , + /* GPIO2_21 on X63:39 */ + , + /* GPIO4_12 on X61:24 */ + , + /* GPIO4_11 on X61:26 */ + , + /* GPIO4_10 on X61:28 */ + , + /* GPIO4_09 on X61:30 */ + , + /* GPIO5_23 on X62:24 */ + , + /* GPIO5_24 on X61:15 */ + , + /* GPIO5_25 on X61:17 */ + , + /* GPIO5_26 on X61:19 */ + , + /* GPIO5_27 on X61:21 */ + , + /* GPIO5_28 on X61:23 */ + , + /* GPIO5_29 on X61:25 */ + ; + }; + + pinctrl_gpio2: gpio2grp { + fsl,pins =3D , + ; + }; + + pinctrl_gpiokeys: gpiokeysgrp { + fsl,pins =3D , + ; + }; + + pinctrl_gpioled: gpioledgrp { + fsl,pins =3D , + ; + }; + + pinctrl_lpspi0: lpspi0grp { + fsl,pins =3D , + , + ; + }; + + pinctrl_lpspi0_cs: lpspi0csgrp { + fsl,pins =3D , + ; + }; + + pinctrl_lpspi1: lpspi1grp { + fsl,pins =3D , + , + ; + }; + + pinctrl_lpspi1_cs: lpspi1csgrp { + fsl,pins =3D , + ; + }; + + pinctrl_lpspi2: lpspi2grp { + fsl,pins =3D , + , + ; + }; + + pinctrl_lpspi2_cs: lpspi2sgrp { + fsl,pins =3D , + ; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins =3D , + , + , + ; + }; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins =3D , + , + , + ; + }; + + pinctrl_lpuart2: lpuart2grp { + fsl,pins =3D , + ; + }; + + pinctrl_lsio_pwm3: lsiopwm3grp { + fsl,pins =3D ; + }; + + pinctrl_pciea: pcieagrp { + fsl,pins =3D , + , + ; + }; + + pinctrl_pcieb: pciebgrp { + fsl,pins =3D , + , + ; + }; + + pinctrl_pwmfan: pwmfangrp { + fsl,pins =3D ; + }; + + pinctrl_reg_mba8x_12v: mba12vgrp { + fsl,pins =3D ; + }; + + pinctrl_reg_pcie_v1v5: regpcie1v5grp { + fsl,pins =3D ; + }; + + pinctrl_reg_pcie_v3v3: regpcie3v3grp { + fsl,pins =3D ; + }; + + pinctrl_regpwmfan: regpwmfangrp { + fsl,pins =3D ; + }; + + pinctrl_reg_v3v3_sd: reg3v3sdgrp { + fsl,pins =3D ; + }; + + pinctrl_sai1: sai1grp { + fsl,pins =3D , + , + , + , + , + ; + }; + + pinctrl_usbotg1: usbotg1grp { + fsl,pins =3D , + ; + }; + + pinctrl_usbhub: usbhubgrp { + fsl,pins =3D ; + }; + + pinctrl_usdhc2_gpio: usdhc2-gpiogrp { + fsl,pins =3D , + ; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins =3D , + , + , + , + , + , + ; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins =3D , + , + , + , + , + , + ; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins =3D , + , + , + , + , + , + ; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-tqma8qm.dtsi b/arch/arm64= /boot/dts/freescale/imx8qm-tqma8qm.dtsi new file mode 100644 index 0000000000000..d94605c999915 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-tqma8qm.dtsi @@ -0,0 +1,318 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2019-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + */ + +#include +#include +#include + +#include "imx8qm.dtsi" + +/ { + model =3D "TQ-Systems i.MX8QM TQMa8QM"; + compatible =3D "tq,imx8qm-tqma8qm", "fsl,imx8qm"; + + memory@80000000 { + device_type =3D "memory"; + /* + * DRAM base addr, size : 1024 MiB DRAM + * should be corrected by bootloader + */ + reg =3D <0x00000000 0x80000000 0 0x40000000>; + }; + + reg_tqma8x_v3v3: regulator-tqma8x-v3v3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "V_3V3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + }; + + /* SW7 controlled by SCU */ + reg_1v8_io1: regulator-v1v8-io1 { + compatible =3D "regulator-fixed"; + regulator-name =3D "V_1V8_IO1"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-always-on; + }; + + /* LDO4 controlled by SCU */ + reg_3v3_emmc: regulator-v3v3-emmc { + compatible =3D "regulator-fixed"; + regulator-name =3D "V_3V3_EMMC"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + }; +}; + +&acm { + status =3D "okay"; +}; + +&adc0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_adc0>; + vref-supply =3D <®_vref_v1v8>; + status =3D "okay"; +}; + +/* TQMa8QM only uses industrial grade, reduce trip points accordingly */ +&cpu_alert0 { + temperature =3D <95000>; +}; + +&cpu_crit0 { + temperature =3D <100000>; +}; + +&cpu_alert1 { + temperature =3D <95000>; +}; + +&cpu_crit1 { + temperature =3D <100000>; +}; + +&gpu_alert0 { + temperature =3D <95000>; +}; + +&gpu_crit0 { + temperature =3D <100000>; +}; + +&gpu_alert1 { + temperature =3D <95000>; +}; + +&gpu_crit1 { + temperature =3D <100000>; +}; + +&drc_alert0 { + temperature =3D <95000>; +}; + +&drc_crit0 { + temperature =3D <100000>; +}; +/* end of temperature grade adjustments */ + +&flexspi0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_flexspi0>; + status =3D "okay"; + + flash0: flash@0 { + compatible =3D "jedec,spi-nor"; + reg =3D <0>; + spi-max-frequency =3D <66000000>; + spi-tx-bus-width =3D <4>; + spi-rx-bus-width =3D <4>; + vcc-supply =3D <®_1v8_io1>; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + }; + }; +}; + +&i2c1 { + clock-frequency =3D <400000>; + pinctrl-names =3D "default", "gpio"; + pinctrl-0 =3D <&pinctrl_lpi2c1>; + pinctrl-1 =3D <&pinctrl_lpi2c1gpio>; + scl-gpios =3D <&lsio_gpio0 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios =3D <&lsio_gpio0 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status =3D "okay"; + + se97: temperature-sensor@1b { + compatible =3D "nxp,se97b", "jedec,jc-42.4-temp"; + reg =3D <0x1b>; + }; + + pcf85063: rtc@51 { + compatible =3D "nxp,pcf85063a"; + reg =3D <0x51>; + quartz-load-femtofarads =3D <7000>; + }; + + at24c02: eeprom@53 { + compatible =3D "nxp,se97b", "atmel,24c02"; + reg =3D <0x53>; + pagesize =3D <16>; + read-only; + vcc-supply =3D <®_tqma8x_v3v3>; + }; + + m24c64: eeprom@57 { + compatible =3D "atmel,24c64"; + reg =3D <0x57>; + pagesize =3D <32>; + vcc-supply =3D <®_tqma8x_v3v3>; + }; +}; + +&mu_m0 { + status =3D "okay"; +}; + +&mu1_m0 { + status =3D "okay"; +}; + +&mu2_m0 { + status =3D "okay"; +}; + +&thermal_zones { + pmic0-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <2000>; + thermal-sensors =3D <&tsens IMX_SC_R_PMIC_0>; + + trips { + pmic_alert0: trip0 { + temperature =3D <110000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + pmic_crit0: trip1 { + temperature =3D <125000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&pmic_alert0>; + cooling-device =3D + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&usdhc1 { + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc1>; + pinctrl-1 =3D <&pinctrl_usdhc1_100mhz>; + pinctrl-2 =3D <&pinctrl_usdhc1_200mhz>; + bus-width =3D <8>; + vmmc-supply =3D <®_3v3_emmc>; + vqmmc-supply =3D <®_1v8_io1>; + no-sd; + no-sdio; + non-removable; + status =3D "okay"; +}; + +&vpu { + compatible =3D "nxp,imx8qm-vpu"; + status =3D "okay"; +}; + +&vpu_core0 { + memory-region =3D <&decoder_boot>, <&decoder_rpc>; + status =3D "okay"; +}; + +&vpu_core1 { + memory-region =3D <&encoder1_boot>, <&encoder1_rpc>; + status =3D "okay"; +}; + +&vpu_core2 { + memory-region =3D <&encoder2_boot>, <&encoder2_rpc>; + status =3D "okay"; +}; + +&iomuxc { + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins =3D , + ; + }; + + pinctrl_lpi2c1gpio: lpi2c1gpiogrp { + fsl,pins =3D , + ; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins =3D , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins =3D , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins =3D , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; 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Wed, 11 Feb 2026 13:41:56 +0100 (CET) From: Alexander Stein To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Peter Chen , Pawel Laszczak , Roger Quadros , Greg Kroah-Hartman , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Magnus Damm , Marek Vasut , Frank Li Cc: Alexander Stein , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-usb@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux@ew.tq-group.com Subject: [PATCH v2 5/5] arm64: dts: imx8qm-tqma8qm-mba8x: Disable Cortex-A72 cluster Date: Wed, 11 Feb 2026 13:41:53 +0100 Message-ID: <20260211124154.1080135-1-alexander.stein@ew.tq-group.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260211123436.1077513-1-alexander.stein@ew.tq-group.com> References: <20260211123436.1077513-1-alexander.stein@ew.tq-group.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-cloud-security-sender: alexander.stein@ew.tq-group.com X-cloud-security-recipient: linux-kernel@vger.kernel.org X-cloud-security-crypt: load encryption module X-cloud-security-Mailarchiv: E-Mail archived for: alexander.stein@ew.tq-group.com X-cloud-security-Mailarchivtype: outbound X-cloud-security-Virusscan: CLEAN X-cloud-security-disclaimer: This E-Mail was scanned by E-Mailservice on mx-relay24-hz1.antispameurope.com with 4f9yjx5Qnhz2ff2J X-cloud-security-connect: he-nlb01-hz1.hornetsecurity.com[94.100.132.6], TLS=1, IP=94.100.132.6 X-cloud-security-Digest: ebb129c93538d71a139afec21e2b08e4 X-cloud-security: scantime:1.798 DKIM-Signature: a=rsa-sha256; bh=6py1FlyDVN3cYWCSXt10KIIllpLulnoSlCJdgJBjOeY=; c=relaxed/relaxed; d=ew.tq-group.com; h=content-type:mime-version:subject:from:to:message-id:date; s=hse1; t=1770813743; v=1; b=S+6DBMDw9PqxtKtQKzySJJj83RCyG94z7LRCJ9kXA3Ru5SXp0E9QWQkekFcoEdrziFPwZSh7 HT7iulNBWY+6miv8KfGx/I/l5T3OlSAQMzb+Wdmsv/DkHi5QM3m0sSm9luxBpC14SSGqOrJO+H0 E5vKphzFuhLhkE/ghRJ0krYEE8azF02xz/siyeFpvmWI1/2WALao1xRj90XOgygUN1d38Bykhdh 0XrT1RKyr+Ra9005N8NkqN81bQyP2AnqIfd3WtV9zWQvekA+crE8dnM4HMh6V2KWoKr5nlugABI ficddo1mf6G2JjQGp8BnzwpTk7n0TWKXHk61gcMAkwFTw== Content-Type: text/plain; charset="utf-8" Due to missing workaround for "ERR050104: Arm/A53: Cache coherency issue" disable the whole Cortex-A72 cluster. Signed-off-by: Alexander Stein --- Changes in v2: * None .../dts/freescale/imx8qm-tqma8qm-mba8x.dts | 39 ------------------- .../boot/dts/freescale/imx8qm-tqma8qm.dtsi | 13 +++++-- 2 files changed, 10 insertions(+), 42 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8qm-tqma8qm-mba8x.dts b/arch/= arm64/boot/dts/freescale/imx8qm-tqma8qm-mba8x.dts index ce5a4657c4230..25274cc76fc56 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-tqma8qm-mba8x.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-tqma8qm-mba8x.dts @@ -297,45 +297,6 @@ map3 { }; }; }; - - cpu1-thermal { - trips { - soc_active1_0: trip-active0 { - temperature =3D <40000>; - hysteresis =3D <5000>; - type =3D "active"; - }; - - soc_active1_1: trip-active1 { - temperature =3D <48000>; - hysteresis =3D <3000>; - type =3D "active"; - }; - - soc_active1_2: trip-active2 { - temperature =3D <60000>; - hysteresis =3D <10000>; - type =3D "active"; - }; - }; - - cooling-maps { - map1 { - trip =3D <&soc_active1_0>; - cooling-device =3D <&fan0 1 1>; - }; - - map2 { - trip =3D <&soc_active1_1>; - cooling-device =3D <&fan0 2 2>; - }; - - map3 { - trip =3D <&soc_active1_2>; - cooling-device =3D <&fan0 3 3>; - }; - }; - }; }; }; =20 diff --git a/arch/arm64/boot/dts/freescale/imx8qm-tqma8qm.dtsi b/arch/arm64= /boot/dts/freescale/imx8qm-tqma8qm.dtsi index d94605c999915..f0e398eb2aad7 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-tqma8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-tqma8qm.dtsi @@ -15,6 +15,13 @@ / { model =3D "TQ-Systems i.MX8QM TQMa8QM"; compatible =3D "tq,imx8qm-tqma8qm", "fsl,imx8qm"; =20 + /* Due to missing workaround for ERR050104 */ + cpus { + /delete-node/ cpu-map; + /delete-node/ cpu@100; + /delete-node/ cpu@101; + }; + memory@80000000 { device_type =3D "memory"; /* @@ -174,6 +181,8 @@ &mu2_m0 { }; =20 &thermal_zones { + /delete-node/ cpu1-thermal; + pmic0-thermal { polling-delay-passive =3D <250>; polling-delay =3D <2000>; @@ -199,9 +208,7 @@ map0 { <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; --=20 2.43.0