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[211.75.127.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3567e9fb4bfsm1632089a91.8.2026.02.11.02.07.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Feb 2026 02:07:19 -0800 (PST) Received: from hqs-appsw-a2o.mp600.macronix.com (unknown [172.17.236.67]) by twhmp6px (Postfix) with ESMTPS id E8D704136074; Wed, 11 Feb 2026 18:07:16 +0800 (CST) From: Cheng Ming Lin To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Tudor Ambarus , Mikhail Kshevetskiy , Pablo Martin-Gomez , Tianling Shen , Pratyush Yadav , linux-mtd@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, alvinzhou@mxic.com.tw, Cheng Ming Lin Subject: [PATCH v5 1/3] dt-bindings: mtd: spinand: Add randomizer enable/disable properties Date: Wed, 11 Feb 2026 18:05:51 +0800 Message-Id: <20260211100553.907585-2-linchengming884@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260211100553.907585-1-linchengming884@gmail.com> References: <20260211100553.907585-1-linchengming884@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Cheng Ming Lin Add "nand-randomizer-enable" and "nand-randomizer-disable" boolean properties. These properties allow enabling or disabling the randomizer feature via the device tree. According to JEDEC standard JESD22-A117E, no single data pattern represents a universal worst-case for all NAND flash failure mechanisms. Different patterns, such as fully programmed, checkerboard, or mostly erased, can disproportionately stress specific cells (e.g., programmed, erased, or those influenced by adjacent states). Given that no fixed pattern can cover all scenarios, the use of a randomized data pattern is a practical and effective mitigation strategy. Our hardware implements a randomizer feature that scrambles user data before it is written to the flash and restores the original data upon read. This ensures the data stored on the media is more evenly distributed, thus reducing pattern-dependent degradation. This is especially crucial for preventing errors caused by unbalanced data (e.g., all zeros or all ones) in blocks with high program/erase (P/E) cycle counts. Ultimately, the randomizer improves the long-term reliability and endurance of the flash device. Please refer to the following link for randomizer feature: Link: https://www.mxic.com.tw/Lists/ApplicationNote/Attachments/2151/AN1051= V1-The%20Introduction%20of%20Randomizer%20Feature%20on%20MX30xFxG28AD_MX35x= FxG24AD. Signed-off-by: Cheng Ming Lin --- Documentation/devicetree/bindings/mtd/nand-chip.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/mtd/nand-chip.yaml b/Documen= tation/devicetree/bindings/mtd/nand-chip.yaml index 609d4a4ddd80..2fcbc4b73e95 100644 --- a/Documentation/devicetree/bindings/mtd/nand-chip.yaml +++ b/Documentation/devicetree/bindings/mtd/nand-chip.yaml @@ -67,6 +67,14 @@ properties: the secure regions present. $ref: /schemas/types.yaml#/definitions/uint64-matrix =20 + nand-randomizer-enable: + description: Enable the randomizer feature. + type: boolean + + nand-randomizer-disable: + description: Disable the randomizer feature. + type: boolean + required: - reg =20 --=20 2.25.1 From nobody Sat Apr 18 03:32:15 2026 Received: from mail-pf1-f177.google.com (mail-pf1-f177.google.com [209.85.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D06A52E2679 for ; Wed, 11 Feb 2026 10:07:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.177 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770804442; cv=none; b=bCnwwGm3/+1TVDM8VLItIVk+hQ8V2xcIUsvrnPtQclQKWH80KmST5dS2xSY7Ep6YWlzqZTEGvFVI/cO1EeKTb3GR3eYgAB+WE+ecTTd17BpbRoTnAg4IW+6bXq2c346wzh4GWqMEFdNFiLqFLhoEeMYhkN4tKwg3MkLoDGJhabk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770804442; c=relaxed/simple; bh=v4g17XTvElKdVLEgPCsbP97+935hoEqDNl0aXrDNwmQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=VDIe6I56o+3+bx3EZlVGng66nNAovzpexQ4+T/jHOw2VLwm6/sXtQcaNdzRJJBfHQLEeFxhgpJxKK3QESS+4rdJsPmSIl5D6vBv8P4nPNd/i3P1L/Zay41rflJwS6uah6DYArhnw1rpFIR1XE8AWEVlM3v8XPR50DobLDD2mMqw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=NmkWJvRJ; arc=none smtp.client-ip=209.85.210.177 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="NmkWJvRJ" Received: by mail-pf1-f177.google.com with SMTP id d2e1a72fcca58-824484dba4dso1513207b3a.0 for ; Wed, 11 Feb 2026 02:07:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1770804439; x=1771409239; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Vez69047uDXOuQc71G6ik4HtqOr3/TvZvcnrZ5g7CFU=; b=NmkWJvRJBh6E6wOl+Rt+TRSGULt4OIDhLbcQ3KKAmFs8AIY0vyi7edlr854aULz1n9 56d+zLfqipANw48XQyYeBLTbpBbaDskv1Y50kjIbW+jIaZZH3mNyS/0TC3gsT1zlBOfq /KHB1I35rSJJ6SeioL3GbWXYOzVCgbZREQsZFvL7221Ddv/Q5tenTeMExlvz40XcpRvN DxLrbYrBJcgwhqIygkk4z+Q2mEyOwUxHoP6lMQPUtF8yQJf+5AwDiLRww9gePe3ZU4jP wdA1aXiwIoa0rjuFA6iB3m/R9axCTh1MxycrphLCOExj0O4BWr9hTzUum3XDqAIcefFB D8Bw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770804439; x=1771409239; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=Vez69047uDXOuQc71G6ik4HtqOr3/TvZvcnrZ5g7CFU=; b=ZFnbJEjlTi456kmS5zKwmyfJ1XlyO9ZOoq98mbEoqdNA1Ua0DCi2dwP6OPmb1Y2k3C THAE6duqq8is+c+XecO5ThkLpC0G1uTIG8g6zgu1EfFt0O0zCYO3uyHUlyrjmQ8amG/V 9QgUN2Z7D1xSrCuvzp6o7KZuoYIwXEi4Z6ZfbZlrdXO3DCngGwtbhhppT5zSUCGFBIBo T9JLo34RKmspQXMOmUaGR1K+nryEU4SQgtngnsgYcOI70vXMVZcb78SZxvtPdWHDI513 AQNp/hKxiLJs98BGmc6qdIfVahInjYD94049Km7MYQjDgX6PnRTX8eWHsgKm71md7OXO YV3Q== X-Forwarded-Encrypted: i=1; AJvYcCXz5dssN5BhFU5fPljb23bapixa+tAyH5BMszXxztxtqmfZyL5pyCCfU9KaQ4Y2sW0+bkcBcpVpnEcheJg=@vger.kernel.org X-Gm-Message-State: AOJu0YxiINwtrzY2du7oygxQUs0X4DLQS4XTCswXsrY3JSWGFmm3/QKW lIJIIMwo0nk5AV8rBjhKsJ58AryUQyiNltcv/4kh99Iej45wPmlLxFxg X-Gm-Gg: AZuq6aIIdxtPharwRfPwvPEhod4IGSTWmMv+aJTUMdjp+AQRXdwau9JWI6SCdlGuRPT FjLO4oddbuvdIV1OEswImvGrjpX+lL3k6lN4RulmY0D5/iqCAC9OT6qR46ZI0AM485vhHfJxtgH 5ZTw+hioa3JFHudrESGX2Cp/3pigiRbwPEHNuroKJ+K8v/h4EpzqsA5yxfr3/UCNruDftQBndbn kT+TE6I2axA7U+HcjuIZXmClUUqQIFI9nrDVhfycR6+uOBUO5LhJkQscnkQdloWjj4qcJhVI3WT nk1d92dG+eINGaRxzUKDSx6A2v7JvLFRVCeEsP70D3r6S2DWWljGZ5m3+zypB/YwmJ1ZtlFfnCO Z/lgAqXjhrZXSQPS0sWW1H5GuIgRxxRrkO2ERa9lEvZq7Wj63rRivWESWTqaznXGU69mlbhAhZU hckTIPnu3NWGlj/WAwUMFhID7rDryzUYRkT3x/UdOJO6IRZw== X-Received: by 2002:a05:6a00:6b93:20b0:824:936a:46bb with SMTP id d2e1a72fcca58-824936a55c2mr2508812b3a.20.1770804438987; Wed, 11 Feb 2026 02:07:18 -0800 (PST) Received: from twhmp6px (mxsmtp211.mxic.com.tw. [211.75.127.162]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-8249e7d600dsm1721184b3a.34.2026.02.11.02.07.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Feb 2026 02:07:18 -0800 (PST) Received: from hqs-appsw-a2o.mp600.macronix.com (unknown [172.17.236.67]) by twhmp6px (Postfix) with ESMTPS id EF2FD4136075; Wed, 11 Feb 2026 18:07:16 +0800 (CST) From: Cheng Ming Lin To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Tudor Ambarus , Mikhail Kshevetskiy , Pablo Martin-Gomez , Tianling Shen , Pratyush Yadav , linux-mtd@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, alvinzhou@mxic.com.tw, Cheng Ming Lin Subject: [PATCH v5 2/3] mtd: spi-nand: Add support for randomizer Date: Wed, 11 Feb 2026 18:05:52 +0800 Message-Id: <20260211100553.907585-3-linchengming884@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260211100553.907585-1-linchengming884@gmail.com> References: <20260211100553.907585-1-linchengming884@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Cheng Ming Lin This patch adds support for the randomizer feature. It introduces a 'set_randomizer' callback in 'struct spinand_info' and 'struct spinand_device'. If a driver implements this callback, the core will invoke it during device initialization (spinand_init) to enable or disable the randomizer feature based on the device tree configuration. Signed-off-by: Cheng Ming Lin --- drivers/mtd/nand/spi/core.c | 27 +++++++++++++++++++++++++++ include/linux/mtd/spinand.h | 9 +++++++++ 2 files changed, 36 insertions(+) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index d207286572d8..d6b12d05c346 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -1218,6 +1218,29 @@ static int spinand_create_dirmaps(struct spinand_dev= ice *spinand) return 0; } =20 +static int spinand_randomizer_init(struct spinand_device *spinand) +{ + struct device_node *np =3D spinand->spimem->spi->dev.of_node; + bool enable =3D false; + int ret; + + if (!spinand->set_randomizer) + return 0; + + if (of_property_read_bool(np, "nand-enable-randomizer")) + enable =3D true; + else if (of_property_read_bool(np, "nand-disable-randomizer")) + enable =3D false; + else + return 0; + + ret =3D spinand->set_randomizer(spinand, enable); + if (ret) + return ret; + + return 0; +} + static const struct nand_ops spinand_ops =3D { .erase =3D spinand_erase, .markbad =3D spinand_markbad, @@ -1412,6 +1435,7 @@ int spinand_match_and_init(struct spinand_device *spi= nand, spinand->user_otp =3D &table[i].user_otp; spinand->read_retries =3D table[i].read_retries; spinand->set_read_retry =3D table[i].set_read_retry; + spinand->set_randomizer =3D table[i].set_randomizer; =20 op =3D spinand_select_op_variant(spinand, info->op_variants.read_cache); @@ -1588,6 +1612,9 @@ static int spinand_init(struct spinand_device *spinan= d) * ECC initialization must have happened previously. */ spinand_cont_read_init(spinand); + ret =3D spinand_randomizer_init(spinand); + if (ret) + goto err_cleanup_nanddev; =20 mtd->_read_oob =3D spinand_mtd_read; mtd->_write_oob =3D spinand_mtd_write; diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index ce76f5c632e1..e01315a71222 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -501,6 +501,7 @@ struct spinand_user_otp { * @user_otp: SPI NAND user OTP info. * @read_retries: the number of read retry modes supported * @set_read_retry: enable/disable read retry for data recovery + * @set_randomizer: enable/disable randomizer support * * Each SPI NAND manufacturer driver should have a spinand_info table * describing all the chips supported by the driver. @@ -527,6 +528,8 @@ struct spinand_info { unsigned int read_retries; int (*set_read_retry)(struct spinand_device *spinand, unsigned int read_retry); + int (*set_randomizer)(struct spinand_device *spinand, + bool enable); }; =20 #define SPINAND_ID(__method, ...) \ @@ -580,6 +583,9 @@ struct spinand_info { .read_retries =3D __read_retries, \ .set_read_retry =3D __set_read_retry =20 +#define SPINAND_RANDOMIZER(__set_randomizer) \ + .set_randomizer =3D __set_randomizer + #define SPINAND_INFO(__model, __id, __memorg, __eccreq, __op_variants, \ __flags, ...) \ { \ @@ -635,6 +641,7 @@ struct spinand_dirmap { * @user_otp: SPI NAND user OTP info. * @read_retries: the number of read retry modes supported * @set_read_retry: Enable/disable the read retry feature + * @set_randomizer: Enable/disable the randomizer feature */ struct spinand_device { struct nand_device base; @@ -668,6 +675,8 @@ struct spinand_device { bool cont_read_possible; int (*set_cont_read)(struct spinand_device *spinand, bool enable); + int (*set_randomizer)(struct spinand_device *spinand, + bool enable); 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[211.75.127.162]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-8249e366a98sm1999109b3a.3.2026.02.11.02.07.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Feb 2026 02:07:19 -0800 (PST) Received: from hqs-appsw-a2o.mp600.macronix.com (unknown [172.17.236.67]) by twhmp6px (Postfix) with ESMTPS id 01FF84136078; Wed, 11 Feb 2026 18:07:17 +0800 (CST) From: Cheng Ming Lin To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Tudor Ambarus , Mikhail Kshevetskiy , Pablo Martin-Gomez , Tianling Shen , Pratyush Yadav , linux-mtd@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, alvinzhou@mxic.com.tw, Cheng Ming Lin Subject: [PATCH v5 3/3] mtd: spi-nand: macronix: Enable randomizer support Date: Wed, 11 Feb 2026 18:05:53 +0800 Message-Id: <20260211100553.907585-4-linchengming884@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260211100553.907585-1-linchengming884@gmail.com> References: <20260211100553.907585-1-linchengming884@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Cheng Ming Lin Implement the 'set_randomizer' callback for Macronix SPI NAND chips. The randomizer is enabled by setting bit 1 of the Configuration Register (address 0x10). This patch adds support for the following chips: - MX35LFxG24AD series - MX35UFxG24AD series When the randomizer is enabled, data is scrambled internally during program operations and automatically descrambled during read operations. This helps reduce bit errors caused by program disturbance. Signed-off-by: Cheng Ming Lin --- drivers/mtd/nand/spi/macronix.c | 46 +++++++++++++++++++++++++-------- 1 file changed, 35 insertions(+), 11 deletions(-) diff --git a/drivers/mtd/nand/spi/macronix.c b/drivers/mtd/nand/spi/macroni= x.c index edf63b9996cf..3a9ab146426b 100644 --- a/drivers/mtd/nand/spi/macronix.c +++ b/drivers/mtd/nand/spi/macronix.c @@ -14,6 +14,8 @@ #define MACRONIX_ECCSR_BF_LAST_PAGE(eccsr) FIELD_GET(GENMASK(3, 0), eccsr) #define MACRONIX_ECCSR_BF_ACCUMULATED_PAGES(eccsr) FIELD_GET(GENMASK(7, 4)= , eccsr) #define MACRONIX_CFG_CONT_READ BIT(2) +#define MACRONIX_CFG_RANDOMIZER_EN BIT(1) +#define MACRONIX_FEATURE_ADDR_RANDOMIZER 0x10 #define MACRONIX_FEATURE_ADDR_READ_RETRY 0x70 #define MACRONIX_NUM_READ_RETRY_MODES 5 =20 @@ -146,7 +148,7 @@ static int macronix_set_cont_read(struct spinand_device= *spinand, bool enable) * Return: 0 on success, a negative error code otherwise. */ static int macronix_set_read_retry(struct spinand_device *spinand, - unsigned int retry_mode) + unsigned int retry_mode) { struct spi_mem_op op =3D SPINAND_SET_FEATURE_1S_1S_1S_OP(MACRONIX_FEATURE= _ADDR_READ_RETRY, spinand->scratchbuf); @@ -155,6 +157,18 @@ static int macronix_set_read_retry(struct spinand_devi= ce *spinand, return spi_mem_exec_op(spinand->spimem, &op); } =20 +static int macronix_set_randomizer(struct spinand_device *spinand, bool en= able) +{ + int ret; + + ret =3D spinand_write_reg_op(spinand, MACRONIX_FEATURE_ADDR_RANDOMIZER, + enable ? MACRONIX_CFG_RANDOMIZER_EN : 0); + if (ret) + return ret; + + return 0; +} + static const struct spinand_info macronix_spinand_table[] =3D { SPINAND_INFO("MX35LF1GE4AB", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x12), @@ -213,7 +227,8 @@ static const struct spinand_info macronix_spinand_table= [] =3D { SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL), SPINAND_READ_RETRY(MACRONIX_NUM_READ_RETRY_MODES, - macronix_set_read_retry)), + macronix_set_read_retry), + SPINAND_RANDOMIZER(macronix_set_randomizer)), SPINAND_INFO("MX35LF2G24AD", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x24, 0x03), NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1), @@ -225,7 +240,8 @@ static const struct spinand_info macronix_spinand_table= [] =3D { SPINAND_HAS_PROG_PLANE_SELECT_BIT, SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL), SPINAND_READ_RETRY(MACRONIX_NUM_READ_RETRY_MODES, - macronix_set_read_retry)), + macronix_set_read_retry), + SPINAND_RANDOMIZER(macronix_set_randomizer)), SPINAND_INFO("MX35LF2G24AD-Z4I8", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x64, 0x03), NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), @@ -236,7 +252,8 @@ static const struct spinand_info macronix_spinand_table= [] =3D { SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL), SPINAND_READ_RETRY(MACRONIX_NUM_READ_RETRY_MODES, - macronix_set_read_retry)), + macronix_set_read_retry), + SPINAND_RANDOMIZER(macronix_set_randomizer)), SPINAND_INFO("MX35LF4G24AD", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x35, 0x03), NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 2, 1, 1), @@ -248,7 +265,8 @@ static const struct spinand_info macronix_spinand_table= [] =3D { SPINAND_HAS_PROG_PLANE_SELECT_BIT, SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL), SPINAND_READ_RETRY(MACRONIX_NUM_READ_RETRY_MODES, - macronix_set_read_retry)), + macronix_set_read_retry), + SPINAND_RANDOMIZER(macronix_set_randomizer)), SPINAND_INFO("MX35LF4G24AD-Z4I8", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x75, 0x03), NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), @@ -259,7 +277,8 @@ static const struct spinand_info macronix_spinand_table= [] =3D { SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL), SPINAND_READ_RETRY(MACRONIX_NUM_READ_RETRY_MODES, - macronix_set_read_retry)), + macronix_set_read_retry), + SPINAND_RANDOMIZER(macronix_set_randomizer)), SPINAND_INFO("MX31LF1GE4BC", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x1e), NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), @@ -305,7 +324,8 @@ static const struct spinand_info macronix_spinand_table= [] =3D { SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, macronix_ecc_get_status), SPINAND_READ_RETRY(MACRONIX_NUM_READ_RETRY_MODES, - macronix_set_read_retry)), + macronix_set_read_retry), + SPINAND_RANDOMIZER(macronix_set_randomizer)), SPINAND_INFO("MX35UF4G24AD-Z4I8", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xf5, 0x03), NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), @@ -317,7 +337,8 @@ static const struct spinand_info macronix_spinand_table= [] =3D { SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, macronix_ecc_get_status), SPINAND_READ_RETRY(MACRONIX_NUM_READ_RETRY_MODES, - macronix_set_read_retry)), + macronix_set_read_retry), + SPINAND_RANDOMIZER(macronix_set_randomizer)), SPINAND_INFO("MX35UF4GE4AD", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xb7, 0x03), NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), @@ -355,7 +376,8 @@ static const struct spinand_info macronix_spinand_table= [] =3D { SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, macronix_ecc_get_status), SPINAND_READ_RETRY(MACRONIX_NUM_READ_RETRY_MODES, - macronix_set_read_retry)), + macronix_set_read_retry), + SPINAND_RANDOMIZER(macronix_set_randomizer)), SPINAND_INFO("MX35UF2G24AD-Z4I8", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xe4, 0x03), NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), @@ -367,7 +389,8 @@ static const struct spinand_info macronix_spinand_table= [] =3D { SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, macronix_ecc_get_status), SPINAND_READ_RETRY(MACRONIX_NUM_READ_RETRY_MODES, - macronix_set_read_retry)), + macronix_set_read_retry), + SPINAND_RANDOMIZER(macronix_set_randomizer)), SPINAND_INFO("MX35UF2GE4AD", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa6, 0x03), NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), @@ -413,7 +436,8 @@ static const struct spinand_info macronix_spinand_table= [] =3D { SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, macronix_ecc_get_status), SPINAND_READ_RETRY(MACRONIX_NUM_READ_RETRY_MODES, - macronix_set_read_retry)), + macronix_set_read_retry), + SPINAND_RANDOMIZER(macronix_set_randomizer)), SPINAND_INFO("MX35UF1GE4AD", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x96, 0x03), NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), --=20 2.25.1