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Wed, 11 Feb 2026 01:11:38 -0800 (PST) Received: from hu-okukatla-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c6e1981512bsm1521481a12.31.2026.02.11.01.11.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Feb 2026 01:11:37 -0800 (PST) From: Odelu Kukatla To: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: Raviteja Laggyshetty , Odelu Kukatla , Dmitry Baryshkov , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mike Tipton Subject: [PATCH v2 1/3] dt-bindings: interconnect: qcom,qcs615-rpmh: add clocks property to enable QoS Date: Wed, 11 Feb 2026 14:41:10 +0530 Message-ID: <20260211091112.3285626-2-odelu.kukatla@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260211091112.3285626-1-odelu.kukatla@oss.qualcomm.com> References: <20260211091112.3285626-1-odelu.kukatla@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; 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For that node, driver must enable the corresponding clock(s) before accessing the registers. Add the 'clocks' property so the driver can obtain and enable the required clock(s). Only interconnects that have clock=E2=80=91gated QoS register interface use this property; it is not applicable to all interconnect nodes. Signed-off-by: Odelu Kukatla --- .../interconnect/qcom,qcs615-rpmh.yaml | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,qcs615-rpm= h.yaml b/Documentation/devicetree/bindings/interconnect/qcom,qcs615-rpmh.ya= ml index e06404828824..42679deb4607 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,qcs615-rpmh.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,qcs615-rpmh.yaml @@ -34,6 +34,10 @@ properties: reg: maxItems: 1 =20 + clocks: + minItems: 4 + maxItems: 4 + required: - compatible =20 @@ -53,6 +57,37 @@ allOf: required: - reg =20 + - if: + properties: + compatible: + contains: + enum: + - qcom,qcs615-aggre1-noc + then: + properties: + clocks: + items: + - description: aggre UFS PHY AXI clock + - description: aggre USB2 SEC AXI clock + - description: aggre USB3 PRIM AXI clock + - description: RPMH CC IPA clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,qcs615-camnoc-virt + - qcom,qcs615-config-noc + - qcom,qcs615-dc-noc + - qcom,qcs615-gem-noc + - qcom,qcs615-mc-virt + - qcom,qcs615-mmss-noc + - qcom,qcs615-system-noc + then: + properties: + clocks: false + unevaluatedProperties: false =20 examples: @@ -69,3 +104,14 @@ examples: #interconnect-cells =3D <2>; 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charset="utf-8" Enable QoS configuration for master ports with predefined priority and urgency forwarding. Signed-off-by: Odelu Kukatla Reviewed-by: Dmitry Baryshkov --- drivers/interconnect/qcom/qcs615.c | 247 +++++++++++++++++++++++++++++ 1 file changed, 247 insertions(+) diff --git a/drivers/interconnect/qcom/qcs615.c b/drivers/interconnect/qcom= /qcs615.c index 797956eb6ff5..017a6017421f 100644 --- a/drivers/interconnect/qcom/qcs615.c +++ b/drivers/interconnect/qcom/qcs615.c @@ -142,6 +142,12 @@ static struct qcom_icc_node qhm_qdss_bam =3D { .name =3D "qhm_qdss_bam", .channels =3D 1, .buswidth =3D 4, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xc000 }, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D { &qns_a1noc_snoc }, }; @@ -150,6 +156,12 @@ static struct qcom_icc_node qhm_qspi =3D { .name =3D "qhm_qspi", .channels =3D 1, .buswidth =3D 4, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x17000 }, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D { &qns_a1noc_snoc }, }; @@ -158,6 +170,12 @@ static struct qcom_icc_node qhm_qup0 =3D { .name =3D "qhm_qup0", .channels =3D 1, .buswidth =3D 4, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x10000 }, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D { &qns_a1noc_snoc }, }; @@ -166,6 +184,12 @@ static struct qcom_icc_node qhm_qup1 =3D { .name =3D "qhm_qup1", .channels =3D 1, .buswidth =3D 4, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x12000 }, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D { &qns_a1noc_snoc }, }; @@ -174,6 +198,12 @@ static struct qcom_icc_node qnm_cnoc =3D { .name =3D "qnm_cnoc", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x4000 }, + .prio =3D 2, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_a1noc_snoc }, }; @@ -182,6 +212,12 @@ static struct qcom_icc_node qxm_crypto =3D { .name =3D "qxm_crypto", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x5000 }, + .prio =3D 2, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_a1noc_snoc }, }; @@ -190,6 +226,12 @@ static struct qcom_icc_node qxm_ipa =3D { .name =3D "qxm_ipa", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x6000 }, + .prio =3D 2, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_lpass_snoc }, }; @@ -198,6 +240,12 @@ static struct qcom_icc_node xm_emac_avb =3D { .name =3D "xm_emac_avb", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xa000 }, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D { &qns_a1noc_snoc }, }; @@ -206,6 +254,12 @@ static struct qcom_icc_node xm_pcie =3D { .name =3D "xm_pcie", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x13000 }, + .prio =3D 0, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D { &qns_pcie_snoc }, }; @@ -214,6 +268,12 @@ static struct qcom_icc_node xm_qdss_etr =3D { .name =3D "xm_qdss_etr", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xb000 }, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D { &qns_a1noc_snoc }, }; @@ -222,6 +282,12 @@ static struct qcom_icc_node xm_sdc1 =3D { .name =3D "xm_sdc1", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xe000 }, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D { &qns_a1noc_snoc }, }; @@ -230,6 +296,12 @@ static struct qcom_icc_node xm_sdc2 =3D { .name =3D "xm_sdc2", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x16000 }, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D { &qns_a1noc_snoc }, }; @@ -238,6 +310,12 @@ static struct qcom_icc_node xm_ufs_mem =3D { .name =3D "xm_ufs_mem", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x11000 }, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D { &qns_a1noc_snoc }, }; @@ -246,6 +324,12 @@ static struct qcom_icc_node xm_usb2 =3D { .name =3D "xm_usb2", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x15000 }, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D { &qns_a1noc_snoc }, }; @@ -254,6 +338,12 @@ static struct qcom_icc_node xm_usb3_0 =3D { .name =3D "xm_usb3_0", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xd000 }, + .prio =3D 2, + .urg_fwd =3D 0, + }, .num_links =3D 1, .link_nodes =3D { &qns_a1noc_snoc }, }; @@ -356,6 +446,12 @@ static struct qcom_icc_node acm_apps =3D { .name =3D "acm_apps", .channels =3D 1, .buswidth =3D 16, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0x2e000, 0x2e100 }, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 3, .link_nodes =3D { &qns_gem_noc_snoc, &qns_llcc, &qns_sys_pcie }, @@ -365,6 +461,12 @@ static struct qcom_icc_node acm_gpu_tcu =3D { .name =3D "acm_gpu_tcu", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x36000 }, + .prio =3D 6, + .urg_fwd =3D 0, + }, .num_links =3D 2, .link_nodes =3D { &qns_gem_noc_snoc, &qns_llcc }, }; @@ -373,6 +475,12 @@ static struct qcom_icc_node acm_sys_tcu =3D { .name =3D "acm_sys_tcu", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x37000 }, + .prio =3D 6, + .urg_fwd =3D 0, + }, .num_links =3D 2, .link_nodes =3D { &qns_gem_noc_snoc, &qns_llcc }, }; @@ -389,6 +497,12 @@ static struct qcom_icc_node qnm_gpu =3D { .name =3D "qnm_gpu", .channels =3D 2, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0x34000, 0x34080 }, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 2, .link_nodes =3D { &qns_gem_noc_snoc, &qns_llcc }, }; @@ -397,6 +511,12 @@ static struct qcom_icc_node qnm_mnoc_hf =3D { .name =3D "qnm_mnoc_hf", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x2f000 }, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_llcc }, }; @@ -405,6 +525,12 @@ static struct qcom_icc_node qnm_mnoc_sf =3D { .name =3D "qnm_mnoc_sf", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x35000 }, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 2, .link_nodes =3D { &qns_gem_noc_snoc, &qns_llcc }, }; @@ -413,6 +539,12 @@ static struct qcom_icc_node qnm_snoc_gc =3D { .name =3D "qnm_snoc_gc", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x31000 }, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_llcc }, }; @@ -421,6 +553,12 @@ static struct qcom_icc_node qnm_snoc_sf =3D { .name =3D "qnm_snoc_sf", .channels =3D 1, .buswidth =3D 16, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x30000 }, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_llcc }, }; @@ -445,6 +583,12 @@ static struct qcom_icc_node qxm_camnoc_hf0 =3D { .name =3D "qxm_camnoc_hf0", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xa000 }, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_hf }, }; @@ -453,6 +597,12 @@ static struct qcom_icc_node qxm_camnoc_hf1 =3D { .name =3D "qxm_camnoc_hf1", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xb000 }, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_hf }, }; @@ -461,6 +611,12 @@ static struct qcom_icc_node qxm_camnoc_sf =3D { .name =3D "qxm_camnoc_sf", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x9000 }, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns2_mem_noc }, }; @@ -469,6 +625,12 @@ static struct qcom_icc_node qxm_mdp0 =3D { .name =3D "qxm_mdp0", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xc000 }, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns_mem_noc_hf }, }; @@ -477,6 +639,12 @@ static struct qcom_icc_node qxm_rot =3D { .name =3D "qxm_rot", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xe000 }, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns2_mem_noc }, }; @@ -485,6 +653,12 @@ static struct qcom_icc_node qxm_venus0 =3D { .name =3D "qxm_venus0", .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xf000 }, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns2_mem_noc }, }; @@ -493,6 +667,12 @@ static struct qcom_icc_node qxm_venus_arm9 =3D { .name =3D "qxm_venus_arm9", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x11000 }, + .prio =3D 0, + .urg_fwd =3D 1, + }, .num_links =3D 1, .link_nodes =3D { &qns2_mem_noc }, }; @@ -559,6 +739,12 @@ static struct qcom_icc_node qxm_pimem =3D { .name =3D "qxm_pimem", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xc000 }, + .prio =3D 2, + .urg_fwd =3D 1, + }, .num_links =3D 2, .link_nodes =3D { &qns_memnoc_gc, &qxs_imem }, }; @@ -567,6 +753,12 @@ static struct qcom_icc_node xm_gic =3D { .name =3D "xm_gic", .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xd000 }, + .prio =3D 2, + .urg_fwd =3D 1, + }, .num_links =3D 2, .link_nodes =3D { &qns_memnoc_gc, &qxs_imem }, }; @@ -1213,11 +1405,21 @@ static struct qcom_icc_node * const aggre1_noc_node= s[] =3D { [SLAVE_SERVICE_A2NOC] =3D &srvc_aggre2_noc, }; =20 +static const struct regmap_config qcs615_aggre1_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x3f200, + .fast_io =3D true, +}; + static const struct qcom_icc_desc qcs615_aggre1_noc =3D { + .config =3D &qcs615_aggre1_noc_regmap_config, .nodes =3D aggre1_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), .bcms =3D aggre1_noc_bcms, .num_bcms =3D ARRAY_SIZE(aggre1_noc_bcms), + .qos_requires_clocks =3D true, }; =20 static struct qcom_icc_bcm * const camnoc_virt_bcms[] =3D { @@ -1289,7 +1491,16 @@ static struct qcom_icc_node * const config_noc_nodes= [] =3D { [SLAVE_SERVICE_CNOC] =3D &srvc_cnoc, }; =20 +static const struct regmap_config qcs615_config_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x5080, + .fast_io =3D true, +}; + static const struct qcom_icc_desc qcs615_config_noc =3D { + .config =3D &qcs615_config_noc_regmap_config, .nodes =3D config_noc_nodes, .num_nodes =3D ARRAY_SIZE(config_noc_nodes), .bcms =3D config_noc_bcms, @@ -1302,7 +1513,16 @@ static struct qcom_icc_node * const dc_noc_nodes[] = =3D { [SLAVE_LLCC_CFG] =3D &qhs_llcc, }; =20 +static const struct regmap_config qcs615_dc_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x3200, + .fast_io =3D true, +}; + static const struct qcom_icc_desc qcs615_dc_noc =3D { + .config =3D &qcs615_dc_noc_regmap_config, .nodes =3D dc_noc_nodes, .num_nodes =3D ARRAY_SIZE(dc_noc_nodes), }; @@ -1331,7 +1551,16 @@ static struct qcom_icc_node * const gem_noc_nodes[] = =3D { [SLAVE_SERVICE_GEM_NOC] =3D &srvc_gemnoc, }; =20 +static const struct regmap_config qcs615_gem_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x3e200, + .fast_io =3D true, +}; + static const struct qcom_icc_desc qcs615_gem_noc =3D { + .config =3D &qcs615_gem_noc_regmap_config, .nodes =3D gem_noc_nodes, .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), .bcms =3D gem_noc_bcms, @@ -1376,7 +1605,16 @@ static struct qcom_icc_node * const mmss_noc_nodes[]= =3D { [SLAVE_SERVICE_MNOC] =3D &srvc_mnoc, }; =20 +static const struct regmap_config qcs615_mmss_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x1c100, + .fast_io =3D true, +}; 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Wed, 11 Feb 2026 01:11:47 -0800 (PST) X-Received: by 2002:a05:6a21:6f0a:b0:392:e5eb:f0e with SMTP id adf61e73a8af0-39417fb11e3mr5175913637.65.1770801106936; Wed, 11 Feb 2026 01:11:46 -0800 (PST) Received: from hu-okukatla-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c6e1981512bsm1521481a12.31.2026.02.11.01.11.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Feb 2026 01:11:46 -0800 (PST) From: Odelu Kukatla To: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: Raviteja Laggyshetty , Odelu Kukatla , Dmitry Baryshkov , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mike Tipton Subject: [PATCH v2 3/3] arm64: dts: qcom: talos: Add clocks for QoS configuration Date: Wed, 11 Feb 2026 14:41:12 +0530 Message-ID: <20260211091112.3285626-4-odelu.kukatla@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260211091112.3285626-1-odelu.kukatla@oss.qualcomm.com> References: <20260211091112.3285626-1-odelu.kukatla@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjExMDA3NCBTYWx0ZWRfX4a7Jkiw5ZWLy Gtd4zcriUR/FcLw1D19z6eYc452P5M0hcRXdlLijYpbeuBNh9WUj9XlaYlPU0yCyYpxnQ0eef+8 2zb2Mj+Q5/SVMiEt8knqatE4ARPVh0aVbBt0ck/FqaQ5T+3ygXuUEgBLt/Q6XgIfvmowcNr858O mC4O+DQGIBqxBMS2eRJl5NIx5y0ZcdN7E3wszYpiUl3XWk+V67ZwOO8iOC5eHvdJCJYesEm6mXN Ou3XdYVzWhpLz6h6y9X0OoDgQQi1Vsi4mohEhvu9a0JInmGLguw6d1E29V8iKQT79+TtmKTc2GG 94JJKYSdUxbyYrsq/cH7Od31eopzUZKyFLGguXb5taI0vywKAwT7+RkP8BiA0nvWIiPl7eHsXLr ANsezp/h9GaPPA/WdGZCdfgdrgnN2Qp4v1CiWOIOYfuXcTB9NqEdu8WhTAjn0t1+scSSbWsv7yC OPKGgz9qNTXWbsjrqsQ== X-Authority-Analysis: v=2.4 cv=R64O2NRX c=1 sm=1 tr=0 ts=698c47d4 cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=EUspDBNiAAAA:8 a=7s_9-EB0MOrke_GCL94A:9 a=x9snwWr2DeNwDh03kgHS:22 X-Proofpoint-GUID: kOUoQiAY-qXTmFH17UgI9YkgZ_lcLN3Q X-Proofpoint-ORIG-GUID: kOUoQiAY-qXTmFH17UgI9YkgZ_lcLN3Q X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-10_03,2026-02-10_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 bulkscore=0 phishscore=0 lowpriorityscore=0 clxscore=1015 adultscore=0 suspectscore=0 impostorscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602110074 Content-Type: text/plain; charset="utf-8" Add clocks which need to be enabled for configuring QoS on talos SoC. Signed-off-by: Odelu Kukatla Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/talos.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom= /talos.dtsi index 75716b4a58d6..232232b02265 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -1234,6 +1234,10 @@ aggre1_noc: interconnect@1700000 { compatible =3D "qcom,qcs615-aggre1-noc"; #interconnect-cells =3D <2>; qcom,bcm-voters =3D <&apps_bcm_voter>; + clocks =3D <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_USB2_SEC_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&rpmhcc RPMH_IPA_CLK>; }; =20 mmss_noc: interconnect@1740000 { --=20 2.43.0