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Wed, 11 Feb 2026 01:48:02 -0800 (PST) Received: from hu-arakshit-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-35662f6b84dsm7526640a91.10.2026.02.11.01.47.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Feb 2026 01:48:02 -0800 (PST) From: Abhinaba Rakshit Date: Wed, 11 Feb 2026 15:17:44 +0530 Subject: [PATCH v5 1/4] dt-bindings: crypto: ice: add operating-points-v2 property for QCOM ICE Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260211-enable-ufs-ice-clock-scaling-v5-1-221c520a1f2e@oss.qualcomm.com> References: <20260211-enable-ufs-ice-clock-scaling-v5-0-221c520a1f2e@oss.qualcomm.com> In-Reply-To: <20260211-enable-ufs-ice-clock-scaling-v5-0-221c520a1f2e@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Manivannan Sadhasivam , "James E.J. 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ICE clock management was handled by the storage drivers in legacy bindings, so the ICE driver itself had no mechanism for clock scaling. With the introduction of the new standalone ICE device node, clock control must now be performed directly by the ICE driver. Enabling operating-points-v2 allows the driver to describe and manage the frequency and voltage requirements for proper DVFS operation. Signed-off-by: Abhinaba Rakshit Acked-by: Rob Herring (Arm) --- .../bindings/crypto/qcom,inline-crypto-engine.yaml | 26 ++++++++++++++++++= ++++ 1 file changed, 26 insertions(+) diff --git a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-en= gine.yaml b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-eng= ine.yaml index c3408dcf5d2057270a732fe0e6744f4aa6496e06..50bcf3309b9fa0a3f727f010301= 670e5de58366f 100644 --- a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.ya= ml +++ b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.ya= ml @@ -30,6 +30,11 @@ properties: clocks: maxItems: 1 =20 + operating-points-v2: true + + opp-table: + type: object + required: - compatible - reg @@ -46,5 +51,26 @@ examples: "qcom,inline-crypto-engine"; reg =3D <0x01d88000 0x8000>; clocks =3D <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + + operating-points-v2 =3D <&ice_opp_table>; + + ice_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-100000000 { + opp-hz =3D /bits/ 64 <100000000>; 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Miller" , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, Abhinaba Rakshit X-Mailer: b4 0.14.2 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjExMDA3OSBTYWx0ZWRfX/qbNjRyp9YK4 HqeUbO2BBAnEhD+tYA9AoiRnM/0ERDIF408Vm7jq3lZfQUY9+8FdLvHh8UiV8on/zGldPE4ihwK KzyEpmfESGHEHKucl/uHmp5NTsbUDmK7hfucLXfHGvAW+6SrpdW5w2FDnIs1qfHuORHJrsC3Nm2 5z14lctc8XUmKonxQWPYMeZLr9siws16noUGQD3NX0apGyr3O6G5oXYShNxKLnpOIas9PJ/oXBk 3C4gmipuoCbmXDdlPMNncGUZyoP+FcMfY+aV2cduIMFlCU5q7/mUOlj6ZlDZvfn5qFauyq+Tm5O OgRurFGm/9ho2pEhdD60R2lPkahosvFwqncIxF66FT8Z5uWl53NdduZ9mgX2cB3kQ9LCO4VBBFq UdrZ7lODe47lV5DlnNK1Gnm2O6c1cgsBXU0jCfssvPJQUYVr+4ALlcebPcNLPpf4STcpy10Eu/v 0p9/SU1bLLQksotxZcw== X-Authority-Analysis: v=2.4 cv=R64O2NRX c=1 sm=1 tr=0 ts=698c505a cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=EUspDBNiAAAA:8 a=JZEC_EQWKO-DjWEl64AA:9 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-GUID: PVlLoZZgz5eJlpJ_limfaxPviKKL1lzS X-Proofpoint-ORIG-GUID: PVlLoZZgz5eJlpJ_limfaxPviKKL1lzS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-10_03,2026-02-10_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 bulkscore=0 phishscore=0 lowpriorityscore=0 clxscore=1015 adultscore=0 suspectscore=0 impostorscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602110079 Register optional operation-points-v2 table for ICE device and aquire its minimum and maximum frequency during ICE device probe. Introduce clock scaling API qcom_ice_scale_clk which scale ICE core clock based on the target frequency provided and if a valid OPP-table is registered. Use flags (if provided) to decide on the rounding of the clock freq against OPP-table. Incase no flags are provided use default behaviour (CEIL incase of scale_up and FLOOR incase of ~scale_up). Disable clock scaling if OPP-table is not registered. When an ICE-device specific OPP table is available, use the PM OPP framework to manage frequency scaling and maintain proper power-domain constraints. Also, ensure to drop the votes in suspend to prevent power/thermal retention. Subsequently restore the frequency in resume from core_clk_freq which stores the last ICE core clock operating frequency. Signed-off-by: Abhinaba Rakshit --- drivers/soc/qcom/ice.c | 132 +++++++++++++++++++++++++++++++++++++++++++++= ++-- include/soc/qcom/ice.h | 5 ++ 2 files changed, 134 insertions(+), 3 deletions(-) diff --git a/drivers/soc/qcom/ice.c b/drivers/soc/qcom/ice.c index b203bc685cadd21d6f96eb1799963a13db4b2b72..0bdc64db414a7028653c0f33279= 88b1554788fcf 100644 --- a/drivers/soc/qcom/ice.c +++ b/drivers/soc/qcom/ice.c @@ -16,6 +16,7 @@ #include #include #include +#include =20 #include =20 @@ -111,6 +112,10 @@ struct qcom_ice { bool use_hwkm; bool hwkm_init_complete; u8 hwkm_version; + unsigned long max_freq; + unsigned long min_freq; + unsigned long core_clk_freq; + bool has_opp; }; =20 static bool qcom_ice_check_supported(struct qcom_ice *ice) @@ -310,12 +315,17 @@ int qcom_ice_resume(struct qcom_ice *ice) struct device *dev =3D ice->dev; int err; =20 + /* Restore the ICE core clk freq */ + if (ice->has_opp && ice->core_clk_freq) + dev_pm_opp_set_rate(ice->dev, ice->core_clk_freq); + err =3D clk_prepare_enable(ice->core_clk); if (err) { dev_err(dev, "failed to enable core clock (%d)\n", err); return err; } + qcom_ice_hwkm_init(ice); return qcom_ice_wait_bist_status(ice); } @@ -324,6 +334,11 @@ EXPORT_SYMBOL_GPL(qcom_ice_resume); int qcom_ice_suspend(struct qcom_ice *ice) { clk_disable_unprepare(ice->core_clk); + + /* Drop the clock votes while suspend */ + if (ice->has_opp) + dev_pm_opp_set_rate(ice->dev, 0); + ice->hwkm_init_complete =3D false; =20 return 0; @@ -549,10 +564,79 @@ int qcom_ice_import_key(struct qcom_ice *ice, } EXPORT_SYMBOL_GPL(qcom_ice_import_key); =20 +/** + * qcom_ice_scale_clk() - Scale ICE clock for DVFS-aware operations + * @ice: ICE driver data + * @target_freq: requested frequency in Hz + * @scale_up: If @flags is 0, choose ceil (true) or floor (false) + * @flags: Rounding policy (ICE_CLOCK_ROUND_*); overrides @scale_up + * + * Clamps @target_freq to the OPP range (min/max), selects an OPP per roun= ding + * policy, then applies it via dev_pm_opp_set_rate() (including voltage/PD + * changes). + * + * Return: 0 on success; -EOPNOTSUPP if no OPP table; or error from + * dev_pm_opp_set_rate()/OPP lookup. + */ +int qcom_ice_scale_clk(struct qcom_ice *ice, unsigned long target_freq, + bool scale_up, unsigned int flags) +{ + int ret; + unsigned long ice_freq =3D target_freq; + struct dev_pm_opp *opp; + + if (!ice->has_opp) + return -EOPNOTSUPP; + + /* Clamp the freq to max if target_freq is beyond supported frequencies */ + if (ice->max_freq && target_freq >=3D ice->max_freq) { + ice_freq =3D ice->max_freq; + goto scale_clock; + } + + /* Clamp the freq to min if target_freq is below supported frequencies */ + if (ice->min_freq && target_freq <=3D ice->min_freq) { + ice_freq =3D ice->min_freq; + goto scale_clock; + } + + switch (flags) { + case ICE_CLOCK_ROUND_CEIL: + opp =3D dev_pm_opp_find_freq_ceil_indexed(ice->dev, &ice_freq, 0); + break; + case ICE_CLOCK_ROUND_FLOOR: + opp =3D dev_pm_opp_find_freq_floor_indexed(ice->dev, &ice_freq, 0); + break; + default: + if (scale_up) + opp =3D dev_pm_opp_find_freq_ceil_indexed(ice->dev, &ice_freq, 0); + else + opp =3D dev_pm_opp_find_freq_floor_indexed(ice->dev, &ice_freq, 0); + break; + } + + if (IS_ERR(opp)) + return -EINVAL; + dev_pm_opp_put(opp); + +scale_clock: + + ret =3D dev_pm_opp_set_rate(ice->dev, ice_freq); + if (!ret) + ice->core_clk_freq =3D ice_freq; + + return ret; +} +EXPORT_SYMBOL_GPL(qcom_ice_scale_clk); + static struct qcom_ice *qcom_ice_create(struct device *dev, - void __iomem *base) + void __iomem *base, + bool is_legacy_binding) { struct qcom_ice *engine; + struct dev_pm_opp *opp; + int err; + unsigned long rate; =20 if (!qcom_scm_is_available()) return ERR_PTR(-EPROBE_DEFER); @@ -584,6 +668,48 @@ static struct qcom_ice *qcom_ice_create(struct device = *dev, if (IS_ERR(engine->core_clk)) return ERR_CAST(engine->core_clk); =20 + /* + * Register the OPP table only when ICE is described as a standalone + * device node. Older platforms place ICE inside the storage controller + * node, so they don't need an OPP table here, as they are handled in + * storage controller. + */ + if (!is_legacy_binding) { + /* OPP table is optional */ + err =3D devm_pm_opp_of_add_table(dev); + if (err && err !=3D -ENODEV) { + dev_err(dev, "Invalid OPP table in Device tree\n"); + return ERR_PTR(err); + } + engine->has_opp =3D (err =3D=3D 0); + + if (!engine->has_opp) + dev_info(dev, "ICE OPP table is not registered\n"); + } + + if (engine->has_opp) { + /* Find the ICE core clock min frequency */ + rate =3D 0; + opp =3D dev_pm_opp_find_freq_ceil_indexed(dev, &rate, 0); + if (IS_ERR(opp)) { + dev_warn(dev, "Unable to find ICE core clock min freq\n"); + } else { + engine->min_freq =3D rate; + dev_pm_opp_put(opp); + } + + /* Find the ICE core clock max frequency */ + rate =3D ULONG_MAX; + opp =3D dev_pm_opp_find_freq_floor_indexed(dev, &rate, 0); + if (IS_ERR(opp)) { + dev_warn(dev, "Unable to find ICE core clock max freq\n"); + } else { + engine->max_freq =3D rate; + dev_pm_opp_put(opp); + } + } + + engine->core_clk_freq =3D clk_get_rate(engine->core_clk); if (!qcom_ice_check_supported(engine)) return ERR_PTR(-EOPNOTSUPP); =20 @@ -628,7 +754,7 @@ static struct qcom_ice *of_qcom_ice_get(struct device *= dev) return ERR_CAST(base); =20 /* create ICE instance using consumer dev */ - return qcom_ice_create(&pdev->dev, base); + return qcom_ice_create(&pdev->dev, base, true); } =20 /* @@ -725,7 +851,7 @@ static int qcom_ice_probe(struct platform_device *pdev) return PTR_ERR(base); } =20 - engine =3D qcom_ice_create(&pdev->dev, base); + engine =3D qcom_ice_create(&pdev->dev, base, false); if (IS_ERR(engine)) return PTR_ERR(engine); =20 diff --git a/include/soc/qcom/ice.h b/include/soc/qcom/ice.h index 4bee553f0a59d86ec6ce20f7c7b4bce28a706415..055edf3a704ff25a608a880cf9b= e35363f8a02d3 100644 --- a/include/soc/qcom/ice.h +++ b/include/soc/qcom/ice.h @@ -9,6 +9,9 @@ #include #include =20 +#define ICE_CLOCK_ROUND_CEIL BIT(1) +#define ICE_CLOCK_ROUND_FLOOR BIT(2) + struct qcom_ice; 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This ensures that the ICE operates at an appropriate frequency when the UFS clocks are scaled up or down, improving performance and maintaining stability for crypto operations. Acked-by: Manivannan Sadhasivam Signed-off-by: Abhinaba Rakshit --- drivers/ufs/host/ufs-qcom.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 8d119b3223cbdaa3297d2beabced0962a1a847d5..00cb9cde760380e7e4213095b9c= 66657a23b13ee 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -305,6 +305,15 @@ static int ufs_qcom_ice_prepare_key(struct blk_crypto_= profile *profile, return qcom_ice_prepare_key(host->ice, lt_key, lt_key_size, eph_key); } =20 +static int ufs_qcom_ice_scale_clk(struct ufs_qcom_host *host, unsigned lon= g target_freq, + bool scale_up, unsigned int flags) +{ + if (host->hba->caps & UFSHCD_CAP_CRYPTO) + return qcom_ice_scale_clk(host->ice, target_freq, scale_up, flags); + + return 0; +} + static const struct blk_crypto_ll_ops ufs_qcom_crypto_ops =3D { .keyslot_program =3D ufs_qcom_ice_keyslot_program, .keyslot_evict =3D ufs_qcom_ice_keyslot_evict, @@ -339,6 +348,12 @@ static void ufs_qcom_config_ice_allocator(struct ufs_q= com_host *host) { } =20 +static int ufs_qcom_ice_scale_clk(struct ufs_qcom_host *host, unsigned lon= g target_freq, + bool scale_up, unsigned int flags) +{ + return 0; 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Wed, 11 Feb 2026 01:48:19 -0800 (PST) X-Received: by 2002:a17:90b:2f0b:b0:354:7be4:a250 with SMTP id 98e67ed59e1d1-3567f7ab2f1mr1563830a91.12.1770803299475; Wed, 11 Feb 2026 01:48:19 -0800 (PST) Received: from hu-arakshit-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-35662f6b84dsm7526640a91.10.2026.02.11.01.48.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Feb 2026 01:48:19 -0800 (PST) From: Abhinaba Rakshit Date: Wed, 11 Feb 2026 15:17:47 +0530 Subject: [PATCH v5 4/4] soc: qcom: ice: Set ICE clk to TURBO on probe Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260211-enable-ufs-ice-clock-scaling-v5-4-221c520a1f2e@oss.qualcomm.com> References: <20260211-enable-ufs-ice-clock-scaling-v5-0-221c520a1f2e@oss.qualcomm.com> In-Reply-To: <20260211-enable-ufs-ice-clock-scaling-v5-0-221c520a1f2e@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Manivannan Sadhasivam , "James E.J. Bottomley" , "Martin K. Petersen" , Neeraj Soni , Herbert Xu , "David S. Miller" , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, Abhinaba Rakshit X-Mailer: b4 0.14.2 X-Authority-Analysis: v=2.4 cv=GM4F0+NK c=1 sm=1 tr=0 ts=698c5064 cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=EUspDBNiAAAA:8 a=u1bwIIJuvd_SIhYoViIA:9 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-GUID: g2_urT_HJ8WxOW44le7594wHx7dXfgmc X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjExMDA3OSBTYWx0ZWRfXx74bNuvIzLI7 sP1ay/uqgZMebNJOs7GpgFKg4UlB4wV+8NGKTDqHrQ+bnbey945SY+z7HdAKKU3X/ZeRURnCIEv S+lyLnVw/NS6Jm16kBH0zGFDjUaS4Lo8hUXKfwJnLbM08cagDulkSEtYFH6Bjwl5eukRMhlM3Kp w/i69DPvP6EeLB3CtJx/agX+A9uqRVULDKpkZyhmUlqXFOva84kp1D4f+10pbcfgDT+c4GvxTXW p9voX0UfI1Pht9oPB0lFqXdAkffXW/+QyLv21eI4Llo7yielooM02RCDe2HWwKp8nOZI6NeXD2s 4UHkGtnA6lXatTuTD3BJXB/FBbR8FVoVHaLW0O/YOEH1IS1T9a26L+G72g8ylTXc+9Ya80Kr8zw 33/zTE2qvlqQXAVKUQGNvgpUx/AhBpf9402oatrx3BdeHzDIQBcyxUyTH7jjbK+A3WuJDwlgkhH i7YtQfFLWtcj7agjWbg== X-Proofpoint-ORIG-GUID: g2_urT_HJ8WxOW44le7594wHx7dXfgmc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-10_03,2026-02-10_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 priorityscore=1501 spamscore=0 clxscore=1015 malwarescore=0 lowpriorityscore=0 bulkscore=0 adultscore=0 suspectscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602110079 MMC controller lacks a clock scaling mechanism, unlike the UFS controller. By default, the MMC controller is set to TURBO mode during probe, but the ICE clock remains at XO frequency, leading to read/write performance degradation on eMMC. To address this, set the ICE clock to TURBO during probe to align it with the controller clock. This ensures consistent performance and avoids mismatches between the controller and ICE clock frequencies. For platforms where ICE is represented as a separate device, use the OPP framework to vote for TURBO mode, maintaining proper voltage and power domain constraints. Signed-off-by: Abhinaba Rakshit --- drivers/soc/qcom/ice.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/soc/qcom/ice.c b/drivers/soc/qcom/ice.c index 0bdc64db414a7028653c0f3327988b1554788fcf..3b69b5673ea93fa927e62a7f4b5= ae52878d564c8 100644 --- a/drivers/soc/qcom/ice.c +++ b/drivers/soc/qcom/ice.c @@ -707,6 +707,11 @@ static struct qcom_ice *qcom_ice_create(struct device = *dev, engine->max_freq =3D rate; dev_pm_opp_put(opp); } + + /* Vote for maximum clock rate for maximum performance */ + err =3D dev_pm_opp_set_rate(dev, INT_MAX); + if (err) + dev_warn(dev, "Failed boosting the ICE clk to TURBO\n"); } =20 engine->core_clk_freq =3D clk_get_rate(engine->core_clk); --=20 2.34.1