From nobody Wed Feb 11 08:11:32 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C1C252750FB for ; Tue, 10 Feb 2026 16:11:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770739863; cv=none; b=A11nYdf7YWo67JenW/bBCjG1cx94/ogTE4iF3HppZrPbTS/6KQqSaZPrmVa3H3XNCbf3JsylchXpjiC3362uxfXiPL4mEtm30O0eNr42RGFavbuNH1haeJWqwW1wKoA99c6fKN1dBEGyIc1aea6aMCAa2enrgH09Y91X3lt4V7w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770739863; c=relaxed/simple; bh=sxy32P8HIxHKnYKQHdnSnY7aFQZW/vJtIrqe78JcBgk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=e7TJahfg6vusn99vTvh7xf2lAF+cKoSL6ncLOhOLmXEhhRCy2XTkwbjNPZi1drQnj8kC4GaBt3BVa/NJ7EiEr1n/Ukq9zsdAfiPVoQqmki0JHEWpMtgJidok7ffcrJ6sP9WtFFxUfAegYc+babnk3p8DWe2gFnUA1AjQEIsMMrI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=cI0aHo7q; arc=none smtp.client-ip=198.175.65.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="cI0aHo7q" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1770739862; x=1802275862; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=sxy32P8HIxHKnYKQHdnSnY7aFQZW/vJtIrqe78JcBgk=; b=cI0aHo7qqMCITI/1MSl5TtFWzGGJ8W/xFato568na3oxQvmhSOKIqUPa +I1HUO2E0psRAx4/iQlko6pdRE1FNtXjMQElbmRRwb95EhdCKGQHIkqJy 4SXgq7YdicjsNxY0xaJ8RS8LaSTZxtPxRk27eoYOVrtWDqbennFSrP6SB N+9psdRlQ7Jc89As0gwqAYYB2za8RdpU0JQer+yAkosK2TyWw7fCvANX4 JeDKxj0DDhPbkIhKsVkIaM55rCEVeiiXV2fYAWdULxE+mYpE6bn37+/K6 hR2peo4Qd9/yREOoVJYO5dod12Y6tzlFQik2pujNQ/5ZSm1cxbs6RiovI A==; X-CSE-ConnectionGUID: ekfQX+BaTRqgDNrAB7F7cw== X-CSE-MsgGUID: KTKDMAduR2uobTveejQdjA== X-IronPort-AV: E=McAfee;i="6800,10657,11697"; a="94514470" X-IronPort-AV: E=Sophos;i="6.21,283,1763452800"; d="scan'208";a="94514470" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Feb 2026 08:11:01 -0800 X-CSE-ConnectionGUID: OMZqizb5TemXGv8PQnemEw== X-CSE-MsgGUID: 1UNICd7FSIGrF47Qg6sUOw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,283,1763452800"; d="scan'208";a="211594022" Received: from black.igk.intel.com ([10.91.253.5]) by fmviesa008.fm.intel.com with ESMTP; 10 Feb 2026 08:10:59 -0800 Received: by black.igk.intel.com (Postfix, from userid 1003) id 7E1919B; Tue, 10 Feb 2026 17:10:58 +0100 (CET) From: Andy Shevchenko To: linux-kernel@vger.kernel.org, Oleksij Rempel Cc: Mark Brown , Greg Kroah-Hartman , "Rafael J. Wysocki" , Danilo Krummrich Subject: [PATCH v1 2/3] regcache: Split regcache_count_cacheable_registers() helper Date: Tue, 10 Feb 2026 17:09:09 +0100 Message-ID: <20260210161058.53093-3-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260210161058.53093-1-andriy.shevchenko@linux.intel.com> References: <20260210161058.53093-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The introduced helper allows to check for the non-cacheable configurations earlier during initialisation. Signed-off-by: Andy Shevchenko --- drivers/base/regmap/regcache.c | 30 +++++++++++++++++++----------- 1 file changed, 19 insertions(+), 11 deletions(-) diff --git a/drivers/base/regmap/regcache.c b/drivers/base/regmap/regcache.c index 1d55f43ff081..0a78ab0dc9fb 100644 --- a/drivers/base/regmap/regcache.c +++ b/drivers/base/regmap/regcache.c @@ -42,13 +42,10 @@ void regcache_sort_defaults(struct reg_default *default= s, unsigned int ndefaults } EXPORT_SYMBOL_GPL(regcache_sort_defaults); =20 -static int regcache_hw_init(struct regmap *map) +static int regcache_count_cacheable_registers(struct regmap *map) { - int i, j; - int ret; int count; - unsigned int reg, val; - void *tmp_buf; + int i; =20 /* calculate the size of reg_defaults */ for (count =3D 0, i =3D 0; i < map->num_reg_defaults_raw; i++) @@ -57,10 +54,18 @@ static int regcache_hw_init(struct regmap *map) count++; =20 /* all registers are unreadable or volatile, so just bypass */ - if (!count) { + if (!count) map->cache_bypass =3D true; - return 0; - } + + return count; +} + +static int regcache_hw_init(struct regmap *map, int count) +{ + int i, j; + int ret; + unsigned int reg, val; + void *tmp_buf; =20 map->num_reg_defaults =3D count; map->reg_defaults =3D kmalloc_array(count, sizeof(struct reg_default), @@ -130,6 +135,7 @@ static int regcache_hw_init(struct regmap *map) =20 int regcache_init(struct regmap *map, const struct regmap_config *config) { + int count =3D 0; int ret; int i; void *tmp_buf; @@ -194,15 +200,17 @@ int regcache_init(struct regmap *map, const struct re= gmap_config *config) return -ENOMEM; map->reg_defaults =3D tmp_buf; } else if (map->num_reg_defaults_raw) { + count =3D regcache_count_cacheable_registers(map); + if (map->cache_bypass) + return 0; + /* Some devices such as PMICs don't have cache defaults, * we cope with this by reading back the HW registers and * crafting the cache defaults by hand. */ - ret =3D regcache_hw_init(map); + ret =3D regcache_hw_init(map, count); if (ret < 0) return ret; - if (map->cache_bypass) - return 0; } =20 if (!map->max_register_is_set && map->num_reg_defaults_raw) { --=20 2.50.1