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Tue, 10 Feb 2026 07:53:54 -0800 (PST) Received: from hu-swatagar-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a952221b4csm149305465ad.89.2026.02.10.07.53.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Feb 2026 07:53:54 -0800 (PST) From: Swati Agarwal To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Swati Agarwal Subject: [PATCH 1/2] arm64: dts: qcom: monaco-evk: Enable GPIO expander interrupt for Monaco EVK Date: Tue, 10 Feb 2026 21:23:28 +0530 Message-Id: <20260210155329.3044455-2-swati.agarwal@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260210155329.3044455-1-swati.agarwal@oss.qualcomm.com> References: <20260210155329.3044455-1-swati.agarwal@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: 4IDUEi7IicVsZXNBb6U23wJdrnCv-EaS X-Proofpoint-ORIG-GUID: 4IDUEi7IicVsZXNBb6U23wJdrnCv-EaS X-Authority-Analysis: v=2.4 cv=YrIChoYX c=1 sm=1 tr=0 ts=698b5493 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=EUspDBNiAAAA:8 a=eeKseBlHB-RYfX28oeEA:9 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjEwMDEzMiBTYWx0ZWRfX3Y8OBii1RPBn GcFUXJMDZK7jIzvKlQl4QoJBrdlfqrsGR71cpoNDr0al6TMd64wxxBhFB3ARItzr3R1RRRTAScu xBx8/wne7Kqp3r3W73Jt9hohGPZKaubT5RD7sByDMlSAjbaS03CP+BG2hqDJZ+BKRalDxVa6j1i LJz75fpRYrGBM1SIAf8BHBhc6jIweBiKBwMtRngzfuOOl6NKUGCGRyLhsYa/MhOD9u/02MRIkDr tY5dafmGRr8ta85kO5nCAlHXp/mGX012+XBYXD5S4GZIyJDWO7bUYi8DfidynNRnnbIjNiV5ki9 cO7LP7BivTMI7IHuFcF/4SwllXuzKOxxzXnesra2pm2hyXdcFEzs0J9uC4pYOutQJN/qVDH/9St ckOATUNHGDGmmS3I4AG5ldvDuQPfVb0T6dG90cfhqMCQAx6npVIYw1sW0c8AsptlfhVmKFZWLJw /xidNy8qUWc5YhWIeng== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-10_01,2026-02-10_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 bulkscore=0 adultscore=0 clxscore=1015 impostorscore=0 lowpriorityscore=0 priorityscore=1501 phishscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602100132 Content-Type: text/plain; charset="utf-8" Enable PCA9538 expander as interrupt controller on Monaco EVK and configure the corresponding TLMM pins via pinctrl to operate as GPIO inputs with internal pull-ups. Signed-off-by: Swati Agarwal --- arch/arm64/boot/dts/qcom/monaco-evk.dts | 77 +++++++++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco-evk.dts b/arch/arm64/boot/dts/= qcom/monaco-evk.dts index 565418b86b2a..03af9bbcacc9 100644 --- a/arch/arm64/boot/dts/qcom/monaco-evk.dts +++ b/arch/arm64/boot/dts/qcom/monaco-evk.dts @@ -362,6 +362,11 @@ expander0: gpio@38 { reg =3D <0x38>; #gpio-cells =3D <2>; gpio-controller; + #interrupt-cells =3D <2>; + interrupt-controller; + interrupts-extended =3D <&tlmm 56 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 =3D <&expander0_int>; + pinctrl-names =3D "default"; }; =20 expander1: gpio@39 { @@ -369,6 +374,11 @@ expander1: gpio@39 { reg =3D <0x39>; #gpio-cells =3D <2>; gpio-controller; + #interrupt-cells =3D <2>; + interrupt-controller; + interrupts-extended =3D <&tlmm 16 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 =3D <&expander1_int>; + pinctrl-names =3D "default"; }; =20 expander2: gpio@3a { @@ -376,6 +386,11 @@ expander2: gpio@3a { reg =3D <0x3a>; #gpio-cells =3D <2>; gpio-controller; + #interrupt-cells =3D <2>; + interrupt-controller; + interrupts-extended =3D <&tlmm 95 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 =3D <&expander2_int>; + pinctrl-names =3D "default"; }; =20 expander3: gpio@3b { @@ -383,6 +398,11 @@ expander3: gpio@3b { reg =3D <0x3b>; #gpio-cells =3D <2>; gpio-controller; + #interrupt-cells =3D <2>; + interrupt-controller; + interrupts-extended =3D <&tlmm 24 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 =3D <&expander3_int>; + pinctrl-names =3D "default"; }; =20 expander4: gpio@3c { @@ -390,6 +410,11 @@ expander4: gpio@3c { reg =3D <0x3c>; #gpio-cells =3D <2>; gpio-controller; + #interrupt-cells =3D <2>; + interrupt-controller; + interrupts-extended =3D <&tlmm 96 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 =3D <&expander4_int>; + pinctrl-names =3D "default"; }; =20 expander5: gpio@3d { @@ -397,6 +422,11 @@ expander5: gpio@3d { reg =3D <0x3d>; #gpio-cells =3D <2>; gpio-controller; + #interrupt-cells =3D <2>; + interrupt-controller; + interrupts-extended =3D <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 =3D <&expander5_int>; + pinctrl-names =3D "default"; }; =20 expander6: gpio@3e { @@ -404,6 +434,11 @@ expander6: gpio@3e { reg =3D <0x3e>; #gpio-cells =3D <2>; gpio-controller; + #interrupt-cells =3D <2>; + interrupt-controller; + interrupts-extended =3D <&tlmm 52 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 =3D <&expander6_int>; + pinctrl-names =3D "default"; }; }; =20 @@ -495,6 +530,48 @@ tpm@0 { =20 &tlmm { =20 + expander0_int: expander0-int-state { + pins =3D "gpio56"; + function =3D "gpio"; + bias-pull-up; + }; + + expander1_int: expander1-int-state { + pins =3D "gpio16"; + function =3D "gpio"; + bias-pull-up; + }; + + expander2_int: expander2-int-state { + pins =3D "gpio95"; + function =3D "gpio"; + bias-pull-up; + }; + + expander3_int: expander3-int-state { + pins =3D "gpio24"; + function =3D "gpio"; + bias-pull-up; + }; + + expander4_int: expander4-int-state { + pins =3D "gpio96"; + function =3D "gpio"; + bias-pull-up; + }; + + expander5_int: expander5-int-state { + pins =3D "gpio3"; + function =3D "gpio"; + bias-pull-up; + }; + + expander6_int: expander6-int-state { + pins =3D "gpio52"; + function =3D "gpio"; + bias-pull-up; + }; + pcie0_default_state: pcie0-default-state { wake-pins { pins =3D "gpio0"; --=20 2.34.1