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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-483209c1a64sm114179175e9.12.2026.02.10.04.51.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Feb 2026 04:51:00 -0800 (PST) From: Peter Maydell To: linux-serial@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Greg Kroah-Hartman , Jiri Slaby , Thomas Gleixner , Arnd Bergmann , Russell King , Miaoqian Lin Subject: [PATCH] serial: amba-pl011: Enable UART in earlycon setup Date: Tue, 10 Feb 2026 12:50:59 +0000 Message-ID: <20260210125100.223138-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently the PL011 driver only enables the UART (by setting UARTEN in REG_CR) in pl011_startup(), so if it is used for earlycon it is relying on the bootrom/firmware having left the UART enabled. There's no particular reason not to actively enable the UART before using it for earlycon, and the earlycon handling for e.g. the 8250 UART sets up the UART in its setup function, so follow that in the PL011. This allows use of earlycon with a UART that the firmware hasn't already been using for its own output, but the main motivation is that QEMU will otherwise log a message complaining that the guest is trying to write to a UART it never enabled. Signed-off-by: Peter Maydell Acked-by: Arnd Bergmann --- NB: I have tested this under QEMU, but I do not have any real PL011-using hardware to hand to test with. --- drivers/tty/serial/amba-pl011.c | 35 ++++++++++++++++++++++++++++++--- 1 file changed, 32 insertions(+), 3 deletions(-) diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl01= 1.c index 7f17d288c807..462a8c380059 100644 --- a/drivers/tty/serial/amba-pl011.c +++ b/drivers/tty/serial/amba-pl011.c @@ -2700,6 +2700,37 @@ static int pl011_early_read(struct console *con, cha= r *s, unsigned int n) */ static int __init pl011_early_console_setup(struct earlycon_device *device, const char *opt) +{ + unsigned int cr; + + if (!device->port.membase) + return -ENODEV; + + device->con->write =3D pl011_early_write; + device->con->read =3D pl011_early_read; + + if (device->port.iotype =3D=3D UPIO_MEM32) + cr =3D readl(device->port.membase + UART011_CR); + else + cr =3D readw(device->port.membase + UART011_CR); + cr &=3D UART011_CR_RTS | UART011_CR_DTR; + cr |=3D UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE; + if (device->port.iotype =3D=3D UPIO_MEM32) + writel(cr, device->port.membase + UART011_CR); + else + writew(cr, device->port.membase + UART011_CR); + + return 0; +} + +OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup); + +/* + * The SBSA UART has no defined control register and is assumed to + * be pre-enabled by firmware, so we do not write to UART011_CR. + */ +static int __init sbsa_uart_early_console_setup(struct earlycon_device *de= vice, + const char *opt) { if (!device->port.membase) return -ENODEV; @@ -2710,9 +2741,7 @@ static int __init pl011_early_console_setup(struct ea= rlycon_device *device, return 0; } =20 -OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup); - -OF_EARLYCON_DECLARE(pl011, "arm,sbsa-uart", pl011_early_console_setup); +OF_EARLYCON_DECLARE(pl011, "arm,sbsa-uart", sbsa_uart_early_console_setup); =20 /* * On Qualcomm Datacenter Technologies QDF2400 SOCs affected by --=20 2.43.0