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charset="utf-8" The Mezzanine is an hardware expansion add-on board designed to be stacked on top of Monaco EVK. It has following peripherals : - 4x Type A USB ports in host mode. - TC9563 PCIe switch, which has following three downstream ports (DSP) : - 1st DSP connects M.2 E-key connector for connecting WLAN endpoints. - 2nd DSP connects M.2 B-key connector for connecting cellular modems. - 3rd DSP with support for Dual Ethernet ports. - EEPROM. - LVDS Display. - 2*mini DP. Add support for following peripherals : - TC9563 PCIe Switch. - EEPROM. Written with inputs from : Krishna Chaitanya Chundru - PCIe Monish Chunara - EEPROM. Signed-off-by: Umang Chheda Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/Makefile | 4 + .../boot/dts/qcom/monaco-evk-mezzanine.dtso | 189 ++++++++++++++++++ 2 files changed, 193 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/monaco-evk-mezzanine.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index f80b5d9cf1e8..009e50c145e9 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -45,6 +45,10 @@ lemans-evk-el2-dtbs :=3D lemans-evk.dtb lemans-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) +=3D lemans-evk-el2.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D milos-fairphone-fp6.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D monaco-evk.dtb + +monaco-evk-mezzanine-dtbs :=3D monaco-evk.dtb monaco-evk-mezzanine.dtbo + +dtb-$(CONFIG_ARCH_QCOM) +=3D monaco-evk-mezzanine.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8216-samsung-fortuna3g.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8916-acer-a1-724.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8916-alcatel-idol347.dtb diff --git a/arch/arm64/boot/dts/qcom/monaco-evk-mezzanine.dtso b/arch/arm6= 4/boot/dts/qcom/monaco-evk-mezzanine.dtso new file mode 100644 index 000000000000..7811bd9e7ea6 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/monaco-evk-mezzanine.dtso @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + model =3D "Qualcomm Technologies, Inc. Monaco-EVK Mezzanine"; + + vreg_0p9: regulator-vreg-0p9 { + compatible =3D "regulator-fixed"; + regulator-name =3D "VREG_0P9"; + + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + regulator-always-on; + regulator-boot-on; + + vin-supply =3D <&vreg_3p3>; + }; + + vreg_1p8: regulator-vreg-1p8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "VREG_1P8"; + + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-always-on; + regulator-boot-on; + + vin-supply =3D <&vreg_4p2>; + }; + + vreg_3p3: regulator-vreg-3p3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "VREG_3P3"; + + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + regulator-boot-on; + + vin-supply =3D <&vreg_4p2>; + }; + + vreg_4p2: regulator-vreg-4p2 { + compatible =3D "regulator-fixed"; + regulator-name =3D "VREG_4P2"; + + regulator-min-microvolt =3D <4200000>; + regulator-max-microvolt =3D <4200000>; + regulator-always-on; + regulator-boot-on; + + vin-supply =3D <&vreg_sys_pwr>; + }; + + vreg_sys_pwr: regulator-vreg-sys-pwr { + compatible =3D "regulator-fixed"; + regulator-name =3D "VREG_SYS_PWR"; + + regulator-min-microvolt =3D <24000000>; + regulator-max-microvolt =3D <24000000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&i2c15 { + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "okay"; + + eeprom1: eeprom@52 { + compatible =3D "giantec,gt24c256c", "atmel,24c256"; + reg =3D <0x52>; + pagesize =3D <64>; + + nvmem-layout { + compatible =3D "fixed-layout"; + #address-cells =3D <1>; + #size-cells =3D <1>; + }; + }; +}; + +&pcie0 { + iommu-map =3D <0x0 &pcie_smmu 0x0 0x1>, + <0x100 &pcie_smmu 0x1 0x1>, + <0x208 &pcie_smmu 0x2 0x1>, + <0x210 &pcie_smmu 0x3 0x1>, + <0x218 &pcie_smmu 0x4 0x1>, + <0x300 &pcie_smmu 0x5 0x1>, + <0x400 &pcie_smmu 0x6 0x1>, + <0x500 &pcie_smmu 0x7 0x1>, + <0x501 &pcie_smmu 0x8 0x1>; +}; + +&pcieport0 { + #address-cells =3D <3>; + #size-cells =3D <2>; + + pcie@0,0 { + compatible =3D "pci1179,0623"; + reg =3D <0x10000 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + device_type =3D "pci"; + ranges; + bus-range =3D <0x2 0xff>; + + vddc-supply =3D <&vreg_0p9>; + vdd18-supply =3D <&vreg_1p8>; + vdd09-supply =3D <&vreg_0p9>; + vddio1-supply =3D <&vreg_1p8>; + vddio2-supply =3D <&vreg_1p8>; + vddio18-supply =3D <&vreg_1p8>; + + i2c-parent =3D <&i2c15 0x77>; + + resx-gpios =3D <&tlmm 124 GPIO_ACTIVE_LOW>; + + pinctrl-0 =3D <&tc9563_resx_n>; + pinctrl-names =3D "default"; + + pcie@1,0 { + reg =3D <0x20800 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + device_type =3D "pci"; + ranges; + bus-range =3D <0x3 0xff>; + }; + + pcie@2,0 { + reg =3D <0x21000 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + device_type =3D "pci"; + ranges; + bus-range =3D <0x4 0xff>; + }; + + pcie@3,0 { + reg =3D <0x21800 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + ranges; + bus-range =3D <0x5 0xff>; + + pci@0,0 { + reg =3D <0x50000 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + ranges; + }; + + pci@0,1 { + reg =3D <0x50100 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + ranges; + }; + }; + }; +}; + +&tlmm { + tc9563_resx_n: tc9563-resx-state { + pins =3D "gpio124"; + function =3D "gpio"; + + bias-disable; + input-disable; + output-enable; + power-source =3D <0>; + }; +}; -- 2.34.1