From nobody Sun Apr 5 16:28:59 2026 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D6B41DFFD for ; Tue, 10 Feb 2026 08:03:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770710590; cv=none; b=CmVIwzCbU3iLPaBvdSFBwJPEQ/wIEuRdOUMYNxZW1Quw6tws64P3BuU8JHgNaq26tt76eGxq5sQAwf+4+5U8LU0JRerR9dnVaMTOBdsLSczoQhJ7Yt3snO6eYYULGI0AjMLczLMQdsmKt+V7cnA23jgqI/Dc6ZvMog4mMUXmPVs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770710590; c=relaxed/simple; bh=BlNS11HeVK3yuwnkEXIHnW+M2wN/MkMjtamfKuvRdSU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Kk0ip7m0axmz/pRMjZ5hGmctb/RSky47jvSBm1E9DR855y0o6emC2fgwVIHOk0LaGGUPpYeEU/ngMe9nfJoVsPYdaOdI68WPKu/yfJSFLczUS+DlcNs8HCqcJwue/XYHeBSVCOkAAHnN7kLsl9bdKjcWv8PN+zlOxBY+HKVB4Xs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b=txQulDfn; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b="txQulDfn" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-Type; bh=wUZC+ngs+W45WbsV0KL78teH7AsjVk5K7jc4yhcKDqs=; b=txQulDfnBtVB6bCnQyxS3vkJIC +VxnZFAGlyF/ETMchEf9mrYRTcobcalC29Mqq4mPM7defREH6XIyiolRcDe6YQZvOygPRDh4tEGPe AQ8pmHvasOpPzgKxIpT8hXczmYhrSxoBFfS3qAsM4UIosGqd2l4wDuWVffnp0pePTtjQXH3KeluO2 I1koHCpQzHxSiVImYyjdbOT1a+4+oKfk9sIDLYjDTD9qPMiz6ZLsZOBnvtL7m1Vr2RCAMruGBxrol MsJr8u5IcHlh5BnKcCZo+JmakZWcdfx+8Lww/ld/krKHtqxKy0+HzrwnTjA1lLp2jMLsVNJwRu8Xm V6kcqi2w==; Received: from i53875a81.versanet.de ([83.135.90.129] helo=phil..) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1vpii9-007v2y-DL; Tue, 10 Feb 2026 09:03:06 +0100 From: Heiko Stuebner To: heiko@sntech.de Cc: quentin.schulz@cherry.de, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Heiko Stuebner Subject: [PATCH v2 2/4] arm64: dts: rockchip: use gated-fixed-clock for pcie-refclk on rk3588-tiger Date: Tue, 10 Feb 2026 09:03:00 +0100 Message-ID: <20260210080303.680403-3-heiko@sntech.de> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20260210080303.680403-1-heiko@sntech.de> References: <20260210080303.680403-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Heiko Stuebner Using a combination of fixed clock and gpio-gate clock works but does not describe the actual hardware. Use the gated-fixed-clock binding to describe this in a nicer way. Signed-off-by: Heiko Stuebner Reviewed-by: Quentin Schulz Reviewed-by: Shawn Lin --- .../arm64/boot/dts/rockchip/rk3588-tiger.dtsi | 19 +++++-------------- 1 file changed, 5 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi b/arch/arm64/bo= ot/dts/rockchip/rk3588-tiger.dtsi index 27269b7b08aa..b4b8f305935f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi @@ -47,23 +47,14 @@ led-1 { }; }; =20 - /* - * 100MHz reference clock for PCIe peripherals from PI6C557-05BLE - * clock generator. - * The clock output is gated via the OE pin on the clock generator. - * This is modeled as a fixed-clock plus a gpio-gate-clock. - */ - pcie_refclk_gen: pcie-refclk-gen-clock { - compatible =3D "fixed-clock"; + /* 100MHz PCIe reference clock from PI6C557-05BLE */ + pcie_refclk: pcie-clock-generator { + compatible =3D "gated-fixed-clock"; #clock-cells =3D <0>; clock-frequency =3D <100000000>; - }; - - pcie_refclk: pcie-refclk-clock { - compatible =3D "gpio-gate-clock"; - clocks =3D <&pcie_refclk_gen>; - #clock-cells =3D <0>; + clock-output-names =3D "pcie-refclk-clock"; enable-gpios =3D <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; /* PCIE30X4_CLKREQN_M= 1_L */ + vdd-supply =3D <&vcca_3v3_s0>; }; =20 vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { --=20 2.47.2