From nobody Tue Apr 7 10:47:33 2026 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D78833555B for ; Tue, 10 Feb 2026 08:03:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770710591; cv=none; b=VPras20x2BDfsMDydC4P4t2eonH1Z3Mh7w2w73M313myvtmpjXiAgXIOeyQ+mIbri2BPOz7rBoHrTVOnMdCS7PiZnKTsY4pMpLabrdPtovEkVlC3h86Xqpn5DhHtyD+Rsa3N3HW14LeCbVn94oHQeSZoCUH1pTiIrMTtduXwA5Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770710591; c=relaxed/simple; bh=JA9LhsK9zcrYqNcA2bMMXw1FwSoGqQOoEnSJ6BIDfII=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FHAk/ivPfcc1xDY+9PDc5BGXOrVmu6pjpObY+yh8ogMIJTRG0JmsesCRJu6GWGHgDheatGyoATzRQrK1ilivuc3tez4WDOqucxre32dkqyty8WijJvWnl2F67exMSLILWsWN4TEOO5TY0T8xcT6ASz52z9mftQgA2FISb7Ewl/I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b=0dTSpJzT; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b="0dTSpJzT" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-Type; bh=7qvgpQOKdKnYsnRxJ2HEXeDXCKwUZaclRd3sIgObCp4=; b=0dTSpJzT4IpVeF6s0WLsiTg/ug 2Ui/AnsUzoh29Vx8yOuDQZdLQIkd6g7ReDS/ww8yA68sExn6U0WcYwKCq3/MzKryvxnCW8XLZVBpD JsRw+k19mqhQ+Yt7Q0ivTdI4VI0enaHX1vcMh4lOgUFE/njhpEODR6aa8ZJeUtgW6JwWRHF6jBPDe FCezRob952WQKH7HCyyGCZvdp0RSpvLR32OlfuO7m9A1/CZZe7AmIECu7FJ/G7vtnLpp22TMfkASP KK6UnCLKJYwsJ12zR9m/3v2QBkN/GKbzUYWY5IeywNpR0IGakQx6KsDXmI5qKaGYyvsJPeAsBa02u OvjYyuOQ==; Received: from i53875a81.versanet.de ([83.135.90.129] helo=phil..) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1vpii9-007v2y-2o; Tue, 10 Feb 2026 09:03:05 +0100 From: Heiko Stuebner To: heiko@sntech.de Cc: quentin.schulz@cherry.de, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Heiko Stuebner Subject: [PATCH v2 1/4] arm64: dts: rockchip: use gated-fixed-clock for pcie-refclk on rk3588-jaguar Date: Tue, 10 Feb 2026 09:02:59 +0100 Message-ID: <20260210080303.680403-2-heiko@sntech.de> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20260210080303.680403-1-heiko@sntech.de> References: <20260210080303.680403-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Heiko Stuebner Using a combination of fixed clock and gpio-gate clock works but does not describe the actual hardware. Use the gated-fixed-clock binding to describe this in a nicer way. Signed-off-by: Heiko Stuebner Reviewed-by: Quentin Schulz Reviewed-by: Shawn Lin --- .../arm64/boot/dts/rockchip/rk3588-jaguar.dts | 19 +++++-------------- 1 file changed, 5 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts b/arch/arm64/bo= ot/dts/rockchip/rk3588-jaguar.dts index 952affaf455c..e21ad7575cb6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts @@ -86,25 +86,16 @@ led-1 { }; }; =20 - /* - * 100MHz reference clock for PCIe peripherals from PI6C557-05BLE - * clock generator. - * The clock output is gated via the OE pin on the clock generator. - * This is modeled as a fixed-clock plus a gpio-gate-clock. - */ - pcie_refclk_gen: pcie-refclk-gen-clock { - compatible =3D "fixed-clock"; + /* 100MHz PCIe reference clock from PI6C557-05BLE */ + pcie_refclk: pcie-clock-generator { + compatible =3D "gated-fixed-clock"; #clock-cells =3D <0>; clock-frequency =3D <100000000>; - }; - - pcie_refclk: pcie-refclk-clock { - compatible =3D "gpio-gate-clock"; - clocks =3D <&pcie_refclk_gen>; - #clock-cells =3D <0>; + clock-output-names =3D "pcie-refclk-clock"; enable-gpios =3D <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>; /* PCIE30X4_CLKREQN_M0= */ pinctrl-names =3D "default"; pinctrl-0 =3D <&pcie30x4_clkreqn_m0>; + vdd-supply =3D <&vcca_3v3_s0>; }; =20 pps { --=20 2.47.2