From nobody Sun Apr 5 13:19:41 2026 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D78833555B for ; Tue, 10 Feb 2026 08:03:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770710591; cv=none; b=VPras20x2BDfsMDydC4P4t2eonH1Z3Mh7w2w73M313myvtmpjXiAgXIOeyQ+mIbri2BPOz7rBoHrTVOnMdCS7PiZnKTsY4pMpLabrdPtovEkVlC3h86Xqpn5DhHtyD+Rsa3N3HW14LeCbVn94oHQeSZoCUH1pTiIrMTtduXwA5Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770710591; c=relaxed/simple; bh=JA9LhsK9zcrYqNcA2bMMXw1FwSoGqQOoEnSJ6BIDfII=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FHAk/ivPfcc1xDY+9PDc5BGXOrVmu6pjpObY+yh8ogMIJTRG0JmsesCRJu6GWGHgDheatGyoATzRQrK1ilivuc3tez4WDOqucxre32dkqyty8WijJvWnl2F67exMSLILWsWN4TEOO5TY0T8xcT6ASz52z9mftQgA2FISb7Ewl/I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b=0dTSpJzT; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b="0dTSpJzT" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-Type; bh=7qvgpQOKdKnYsnRxJ2HEXeDXCKwUZaclRd3sIgObCp4=; b=0dTSpJzT4IpVeF6s0WLsiTg/ug 2Ui/AnsUzoh29Vx8yOuDQZdLQIkd6g7ReDS/ww8yA68sExn6U0WcYwKCq3/MzKryvxnCW8XLZVBpD JsRw+k19mqhQ+Yt7Q0ivTdI4VI0enaHX1vcMh4lOgUFE/njhpEODR6aa8ZJeUtgW6JwWRHF6jBPDe FCezRob952WQKH7HCyyGCZvdp0RSpvLR32OlfuO7m9A1/CZZe7AmIECu7FJ/G7vtnLpp22TMfkASP KK6UnCLKJYwsJ12zR9m/3v2QBkN/GKbzUYWY5IeywNpR0IGakQx6KsDXmI5qKaGYyvsJPeAsBa02u OvjYyuOQ==; Received: from i53875a81.versanet.de ([83.135.90.129] helo=phil..) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1vpii9-007v2y-2o; Tue, 10 Feb 2026 09:03:05 +0100 From: Heiko Stuebner To: heiko@sntech.de Cc: quentin.schulz@cherry.de, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Heiko Stuebner Subject: [PATCH v2 1/4] arm64: dts: rockchip: use gated-fixed-clock for pcie-refclk on rk3588-jaguar Date: Tue, 10 Feb 2026 09:02:59 +0100 Message-ID: <20260210080303.680403-2-heiko@sntech.de> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20260210080303.680403-1-heiko@sntech.de> References: <20260210080303.680403-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Heiko Stuebner Using a combination of fixed clock and gpio-gate clock works but does not describe the actual hardware. Use the gated-fixed-clock binding to describe this in a nicer way. Signed-off-by: Heiko Stuebner Reviewed-by: Quentin Schulz Reviewed-by: Shawn Lin --- .../arm64/boot/dts/rockchip/rk3588-jaguar.dts | 19 +++++-------------- 1 file changed, 5 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts b/arch/arm64/bo= ot/dts/rockchip/rk3588-jaguar.dts index 952affaf455c..e21ad7575cb6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts @@ -86,25 +86,16 @@ led-1 { }; }; =20 - /* - * 100MHz reference clock for PCIe peripherals from PI6C557-05BLE - * clock generator. - * The clock output is gated via the OE pin on the clock generator. - * This is modeled as a fixed-clock plus a gpio-gate-clock. - */ - pcie_refclk_gen: pcie-refclk-gen-clock { - compatible =3D "fixed-clock"; + /* 100MHz PCIe reference clock from PI6C557-05BLE */ + pcie_refclk: pcie-clock-generator { + compatible =3D "gated-fixed-clock"; #clock-cells =3D <0>; clock-frequency =3D <100000000>; - }; - - pcie_refclk: pcie-refclk-clock { - compatible =3D "gpio-gate-clock"; - clocks =3D <&pcie_refclk_gen>; - #clock-cells =3D <0>; + clock-output-names =3D "pcie-refclk-clock"; enable-gpios =3D <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>; /* PCIE30X4_CLKREQN_M0= */ pinctrl-names =3D "default"; pinctrl-0 =3D <&pcie30x4_clkreqn_m0>; + vdd-supply =3D <&vcca_3v3_s0>; }; =20 pps { --=20 2.47.2 From nobody Sun Apr 5 13:19:41 2026 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D6B41DFFD for ; Tue, 10 Feb 2026 08:03:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770710590; cv=none; b=CmVIwzCbU3iLPaBvdSFBwJPEQ/wIEuRdOUMYNxZW1Quw6tws64P3BuU8JHgNaq26tt76eGxq5sQAwf+4+5U8LU0JRerR9dnVaMTOBdsLSczoQhJ7Yt3snO6eYYULGI0AjMLczLMQdsmKt+V7cnA23jgqI/Dc6ZvMog4mMUXmPVs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770710590; c=relaxed/simple; bh=BlNS11HeVK3yuwnkEXIHnW+M2wN/MkMjtamfKuvRdSU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Kk0ip7m0axmz/pRMjZ5hGmctb/RSky47jvSBm1E9DR855y0o6emC2fgwVIHOk0LaGGUPpYeEU/ngMe9nfJoVsPYdaOdI68WPKu/yfJSFLczUS+DlcNs8HCqcJwue/XYHeBSVCOkAAHnN7kLsl9bdKjcWv8PN+zlOxBY+HKVB4Xs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b=txQulDfn; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b="txQulDfn" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-Type; bh=wUZC+ngs+W45WbsV0KL78teH7AsjVk5K7jc4yhcKDqs=; b=txQulDfnBtVB6bCnQyxS3vkJIC +VxnZFAGlyF/ETMchEf9mrYRTcobcalC29Mqq4mPM7defREH6XIyiolRcDe6YQZvOygPRDh4tEGPe AQ8pmHvasOpPzgKxIpT8hXczmYhrSxoBFfS3qAsM4UIosGqd2l4wDuWVffnp0pePTtjQXH3KeluO2 I1koHCpQzHxSiVImYyjdbOT1a+4+oKfk9sIDLYjDTD9qPMiz6ZLsZOBnvtL7m1Vr2RCAMruGBxrol MsJr8u5IcHlh5BnKcCZo+JmakZWcdfx+8Lww/ld/krKHtqxKy0+HzrwnTjA1lLp2jMLsVNJwRu8Xm V6kcqi2w==; Received: from i53875a81.versanet.de ([83.135.90.129] helo=phil..) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1vpii9-007v2y-DL; Tue, 10 Feb 2026 09:03:06 +0100 From: Heiko Stuebner To: heiko@sntech.de Cc: quentin.schulz@cherry.de, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Heiko Stuebner Subject: [PATCH v2 2/4] arm64: dts: rockchip: use gated-fixed-clock for pcie-refclk on rk3588-tiger Date: Tue, 10 Feb 2026 09:03:00 +0100 Message-ID: <20260210080303.680403-3-heiko@sntech.de> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20260210080303.680403-1-heiko@sntech.de> References: <20260210080303.680403-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Heiko Stuebner Using a combination of fixed clock and gpio-gate clock works but does not describe the actual hardware. Use the gated-fixed-clock binding to describe this in a nicer way. Signed-off-by: Heiko Stuebner Reviewed-by: Quentin Schulz Reviewed-by: Shawn Lin --- .../arm64/boot/dts/rockchip/rk3588-tiger.dtsi | 19 +++++-------------- 1 file changed, 5 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi b/arch/arm64/bo= ot/dts/rockchip/rk3588-tiger.dtsi index 27269b7b08aa..b4b8f305935f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi @@ -47,23 +47,14 @@ led-1 { }; }; =20 - /* - * 100MHz reference clock for PCIe peripherals from PI6C557-05BLE - * clock generator. - * The clock output is gated via the OE pin on the clock generator. - * This is modeled as a fixed-clock plus a gpio-gate-clock. - */ - pcie_refclk_gen: pcie-refclk-gen-clock { - compatible =3D "fixed-clock"; + /* 100MHz PCIe reference clock from PI6C557-05BLE */ + pcie_refclk: pcie-clock-generator { + compatible =3D "gated-fixed-clock"; #clock-cells =3D <0>; clock-frequency =3D <100000000>; - }; - - pcie_refclk: pcie-refclk-clock { - compatible =3D "gpio-gate-clock"; - clocks =3D <&pcie_refclk_gen>; - #clock-cells =3D <0>; + clock-output-names =3D "pcie-refclk-clock"; enable-gpios =3D <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; /* PCIE30X4_CLKREQN_M= 1_L */ + vdd-supply =3D <&vcca_3v3_s0>; }; =20 vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { --=20 2.47.2 From nobody Sun Apr 5 13:19:41 2026 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 60CA233A9C3 for ; Tue, 10 Feb 2026 08:03:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770710591; cv=none; b=bbqM8WndoGRsYTo3RL8cINZjS7rEGY80p4rPWR2/K1Y9aUXOohyr8NwRZCHxSV1VxDs9h69VloPKlkk946gokCGGPMcDfrxukeMmIbqhMq+f4igLQn7lz9lrhIgD6aoIsy5gGBgxL/6SGy//NccPLRh4rhNdulQK8u4nAmAthqM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770710591; c=relaxed/simple; bh=mZ8SZKIdq85Lt8xu5ckZ4RuUdytfLfyFZDstaxBr5R8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=tNDxx0E+ZhuAcE/91Was/UsfkcAEgsLEUoTMkjHjVLxcbEjf54aUmJ+xyDRLvjgaQA8xV2EpFqdzuSbDZJLnKWJcd4RJ1CK/+nLT6xyySiVtCRb92FI4offqgJ3HOxwlHfY6EmUDs3ib4/VTpp7hnIbSqJ42fuHHOp8xRsR519A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b=KVo5b7Qu; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b="KVo5b7Qu" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-Type; bh=hPrpzvTn1blb4qvw6DL7D5C3Jr1Z/N7sP9GBJ7rtElw=; b=KVo5b7QusLcPKb/wBk3t0TR+We xQU4M534hilk9BP7T6Wv0OQZ+RiUpTvfJ59lwe2WosXm8u/XfsrPqaCe/BukuQktKb0ZAl2p5Gz8A 7MbLAe3I8iVc1b1L/JaXeGcwsucG0t8pB613fEA6/kcvoYRU8unJ3k7xIOvX0FpY5SBdqGE55jLoo 47lxFzuin+OMM0TcL+v3snq75ZvRc8w0J3zTiBthcTE3P4Aw6E20LJQeLdnu1iPs1a3o9o3/T8RuG 74OOtWOqrRjOmrpMeWL9vEHfyx9lh54tWkHUABy1tbZ17Ea3nb6Wd3/ANMankKkstFFf4ZGa+GWpo Sg+GCQaQ==; Received: from i53875a81.versanet.de ([83.135.90.129] helo=phil..) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1vpii9-007v2y-NY; Tue, 10 Feb 2026 09:03:06 +0100 From: Heiko Stuebner To: heiko@sntech.de Cc: quentin.schulz@cherry.de, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Heiko Stuebner Subject: [PATCH v2 3/4] arm64: dts: rockchip: add pinctrl for clk-generator GPIO on rk3588-tiger Date: Tue, 10 Feb 2026 09:03:01 +0100 Message-ID: <20260210080303.680403-4-heiko@sntech.de> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20260210080303.680403-1-heiko@sntech.de> References: <20260210080303.680403-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Heiko Stuebner While specific driver in the Linux-Kernel handles GPIOs gracefully without matching pinctrl entries, this might not be true for other operating systems. So having pinctrl entries makes the hardware-description more complete. The somewhat similar rk3588-jaguar board has a pinctrl entry already, so also add one for rk3588-tiger. Reviewed-by: Quentin Schulz Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi b/arch/arm64/bo= ot/dts/rockchip/rk3588-tiger.dtsi index b4b8f305935f..a0e97481afb7 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi @@ -54,6 +54,8 @@ pcie_refclk: pcie-clock-generator { clock-frequency =3D <100000000>; clock-output-names =3D "pcie-refclk-clock"; enable-gpios =3D <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; /* PCIE30X4_CLKREQN_M= 1_L */ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie30x4_clkreqn_m1_l>; vdd-supply =3D <&vcca_3v3_s0>; }; =20 @@ -353,6 +355,12 @@ module_led_pin: module-led-pin { }; }; =20 + pcie30x4 { + pcie30x4_clkreqn_m1_l: pcie30x4-clkreqn-m1-l { + rockchip,pins =3D <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + usb3 { usb3_id: usb3-id { rockchip,pins =3D --=20 2.47.2 From nobody Sun Apr 5 13:19:41 2026 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D7001917ED for ; Tue, 10 Feb 2026 08:03:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770710590; cv=none; b=b+KUiSdIFYwITlYVOpAFsazr7MzIc0SOnzpQA7kwa/MBO9h3z6ioUafFhXjfjrH+x2Zyb/WgdiSN3/Kk3p5oMqCXIC9qoxK6R1Ac+krsT5XO0vt7qAwJZzZzrNojGbCJ+hJ/qZ0RNofxfj/MNBSHxIzRjidOAZqgBrku13f0P9s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770710590; c=relaxed/simple; bh=XpXaq+6a9NjyExw0z8tT4j7XlfPYvYhH0OCMxGJi0u8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=X5+xyzQX3XRH/SVgx4scvanVlzkf5repc1ptl6Y+vK8jtEvAE8yvnscPnJFobZFw7oDmO9E43jNt8gnKEIL441FJS/XxW62DJakp/NemkhAB83Z6lIb1/pt8vHA3AIhwErEcFfTJV7YGi5J1xet+TnqCvpnT8GHO/8yFN9IIZfs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b=KfDwCRDl; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b="KfDwCRDl" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-Type; bh=lMrn2OuSs8+Po/Mt1LAP2KnbJwlgAoydGZL4dwq11Zk=; b=KfDwCRDlrRzxU6L5DGjSY2u5lt H8NYV5CpQJ7QOH5kxXhjhhzcJFUIZK4kMmZOoZJD6dDKPC8/eqvydDnxw26gmkPlt2fnlonI5oTlZ jHGebt/cS/Il+NCWVlHuV/436pBdDDs4ka3M/Z+8kVpP6fakt8OsVtJqyiyeH2voTbnNtij69k76U dMMpEBt5P8c0l/2ysfJMSWgIppHeg2g1Lw24mVs9ApRmnBmUVSVgpI1baoH5fdFUqZ+lF5YLHGK+I 4B/io/p4ju1BBJzPDAWrw/OcLeOAr9nsULdD7R8t6jO2XROdnM/kCkysBRoYRktTxcKVQgui3J2hQ iH4gPnmg==; Received: from i53875a81.versanet.de ([83.135.90.129] helo=phil..) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1vpiiA-007v2y-1K; Tue, 10 Feb 2026 09:03:06 +0100 From: Heiko Stuebner To: heiko@sntech.de Cc: quentin.schulz@cherry.de, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Heiko Stuebner Subject: [PATCH v2 4/4] arm64: dts: rockchip: Make Jaguar PCIe-refclk pin use pull-up config Date: Tue, 10 Feb 2026 09:03:02 +0100 Message-ID: <20260210080303.680403-5-heiko@sntech.de> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20260210080303.680403-1-heiko@sntech.de> References: <20260210080303.680403-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Heiko Stuebner Different to RK3588-Tiger, on RK3588-Jaguar the signal enabling the PCIe-refclk generator controls a transistor which in turn controls the output-enable input of the PI6C557 and there's no external Pull-Up or Pull-Down between the SoC and the transistor gate. On Tiger the pin is directly connected to the PDn input which has an internal pull up. So match that behaviour on Jaguar by changing the pin config to enable the SoC's pull-up config. Suggested-by: Quentin Schulz Fixes: 0ec7e1096332 ("arm64: dts: rockchip: add PCIe3 support on rk3588-jag= uar") Signed-off-by: Heiko Stuebner Reviewed-by: Quentin Schulz Reviewed-by: Shawn Lin --- arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts b/arch/arm64/bo= ot/dts/rockchip/rk3588-jaguar.dts index e21ad7575cb6..5f5d89a33a4a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts @@ -579,7 +579,7 @@ led1_pin: led1-pin { =20 pcie30x4 { pcie30x4_clkreqn_m0: pcie30x4-clkreqn-m0 { - rockchip,pins =3D <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins =3D <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; }; =20 pcie30x4_perstn_m0: pcie30x4-perstn-m0 { --=20 2.47.2