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charset="utf-8" From: Udit Tiwari The Qualcomm Crypto Engine (QCE) driver currently lacks support for runtime power management (PM) and interconnect bandwidth control. As a result, the hardware remains fully powered and clocks stay enabled even when the device is idle. Additionally, static interconnect bandwidth votes are held indefinitely, preventing the system from reclaiming unused bandwidth. Address this by enabling runtime PM and dynamic interconnect bandwidth scaling to allow the system to suspend the device when idle and scale interconnect usage based on actual demand. Improve overall system efficiency by reducing power usage and optimizing interconnect resource allocation. Make the following changes as part of this integration: - Add support for pm_runtime APIs to manage device power state transitions. - Implement runtime_suspend() and runtime_resume() callbacks to gate clocks and vote for interconnect bandwidth only when needed. - Replace devm_clk_get_optional_enabled() with devm_pm_clk_create() + pm_clk_add() and let the PM core manage device clocks during runtime PM and system sleep. - Register dev_pm_ops with the platform driver to hook into the PM framework. Tested: - Verify that ICC votes drop to zero after probe and upon request completion. - Confirm that runtime PM usage count increments during active requests and decrements afterward. - Observe that the device correctly enters the suspended state when idle. Signed-off-by: Udit Tiwari --- Changes in v6: - Adopt ACQUIRE(pm_runtime_active_try, ...) for scoped runtime PM management in qce_handle_queue(). This removes the need for manual put calls and goto labels in the error paths, as suggested by Konrad. Changes in v5: - Drop Reported-by and Closes tags for kernel test robot W=3D1 warnings, as the issue was fixed within the same patch series. - Fix a minor comment indentation/style issue. - Link to v5: https://lore.kernel.org/lkml/20251120062443.2016084-1-quic_ut= iwari@quicinc.com/ Changes in v4: - Annotate runtime PM callbacks with __maybe_unused to silence W=3D1 warnin= gs. - Add Reported-by and Closes tags for kernel test robot warning. - Link to v4: https://lore.kernel.org/lkml/20251117062737.3946074-1-quic_ut= iwari@quicinc.com/ Changes in v3: - Switch from manual clock management to PM clock helpers (devm_pm_clk_create() + pm_clk_add()); no direct clk_* enable/disable in runtime callbacks. - Replace pm_runtime_get_sync() with pm_runtime_resume_and_get(); remove pm_runtime_put_noidle() on error. - Define PM ops using helper macros and reuse runtime callbacks for system sleep via pm_runtime_force_suspend()/pm_runtime_force_resume(). - Link to v2: https://lore.kernel.org/lkml/20250826110917.3383061-1-quic_ut= iwari@quicinc.com/ Changes in v2: - Extend suspend/resume support to include runtime PM and ICC scaling. - Register dev_pm_ops and implement runtime_suspend/resume callbacks. - Link to v1: https://lore.kernel.org/lkml/20250606105808.2119280-1-quic_ut= iwari@quicinc.com/ --- drivers/crypto/qce/core.c | 98 +++++++++++++++++++++++++++++++++------ 1 file changed, 83 insertions(+), 15 deletions(-) diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c index b966f3365b7d..2e1e4db93682 100644 --- a/drivers/crypto/qce/core.c +++ b/drivers/crypto/qce/core.c @@ -12,6 +12,9 @@ #include #include #include +#include +#include +#include #include #include #include @@ -90,6 +93,11 @@ static int qce_handle_queue(struct qce_device *qce, struct crypto_async_request *async_req, *backlog; int ret =3D 0, err; =20 + ACQUIRE(pm_runtime_active_try, pm)(qce->dev); + ret =3D ACQUIRE_ERR(pm_runtime_active_auto_try, &pm); + if (ret) + return ret; + scoped_guard(mutex, &qce->lock) { if (req) ret =3D crypto_enqueue_request(&qce->queue, req); @@ -207,37 +215,47 @@ static int qce_crypto_probe(struct platform_device *p= dev) if (ret < 0) return ret; =20 - qce->core =3D devm_clk_get_optional_enabled(qce->dev, "core"); - if (IS_ERR(qce->core)) - return PTR_ERR(qce->core); + /* PM clock helpers: register device clocks */ + ret =3D devm_pm_clk_create(dev); + if (ret) + return ret; + + ret =3D pm_clk_add(dev, "core"); + if (ret) + return ret; =20 - qce->iface =3D devm_clk_get_optional_enabled(qce->dev, "iface"); - if (IS_ERR(qce->iface)) - return PTR_ERR(qce->iface); + ret =3D pm_clk_add(dev, "iface"); + if (ret) + return ret; =20 - qce->bus =3D devm_clk_get_optional_enabled(qce->dev, "bus"); - if (IS_ERR(qce->bus)) - return PTR_ERR(qce->bus); + ret =3D pm_clk_add(dev, "bus"); + if (ret) + return ret; =20 - qce->mem_path =3D devm_of_icc_get(qce->dev, "memory"); + qce->mem_path =3D devm_of_icc_get(dev, "memory"); if (IS_ERR(qce->mem_path)) return PTR_ERR(qce->mem_path); =20 - ret =3D icc_set_bw(qce->mem_path, QCE_DEFAULT_MEM_BANDWIDTH, QCE_DEFAULT_= MEM_BANDWIDTH); + /* Enable runtime PM after clocks and ICC are acquired */ + ret =3D devm_pm_runtime_enable(dev); if (ret) return ret; =20 - ret =3D devm_qce_dma_request(qce->dev, &qce->dma); + ret =3D pm_runtime_resume_and_get(dev); if (ret) return ret; =20 + ret =3D devm_qce_dma_request(qce->dev, &qce->dma); + if (ret) + goto err_pm; + ret =3D qce_check_version(qce); if (ret) - return ret; + goto err_pm; =20 ret =3D devm_mutex_init(qce->dev, &qce->lock); if (ret) - return ret; + goto err_pm; =20 INIT_WORK(&qce->done_work, qce_req_done_work); crypto_init_queue(&qce->queue, QCE_QUEUE_LENGTH); @@ -245,9 +263,58 @@ static int qce_crypto_probe(struct platform_device *pd= ev) qce->async_req_enqueue =3D qce_async_request_enqueue; qce->async_req_done =3D qce_async_request_done; =20 - return devm_qce_register_algs(qce); + ret =3D devm_qce_register_algs(qce); + if (ret) + goto err_pm; + + /* Configure autosuspend after successful init */ + pm_runtime_set_autosuspend_delay(dev, 100); + pm_runtime_use_autosuspend(dev); + pm_runtime_mark_last_busy(dev); + pm_runtime_put_autosuspend(dev); + + return 0; + +err_pm: + pm_runtime_put(dev); + + return ret; +} + +static int __maybe_unused qce_runtime_suspend(struct device *dev) +{ + struct qce_device *qce =3D dev_get_drvdata(dev); + + icc_disable(qce->mem_path); + + return 0; } =20 +static int __maybe_unused qce_runtime_resume(struct device *dev) +{ + struct qce_device *qce =3D dev_get_drvdata(dev); + int ret =3D 0; + + ret =3D icc_enable(qce->mem_path); + if (ret) + return ret; + + ret =3D icc_set_bw(qce->mem_path, QCE_DEFAULT_MEM_BANDWIDTH, QCE_DEFAULT_= MEM_BANDWIDTH); + if (ret) + goto err_icc; + + return 0; + +err_icc: + icc_disable(qce->mem_path); + return ret; +} + +static const struct dev_pm_ops qce_crypto_pm_ops =3D { + SET_RUNTIME_PM_OPS(qce_runtime_suspend, qce_runtime_resume, NULL) + SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) +}; + static const struct of_device_id qce_crypto_of_match[] =3D { { .compatible =3D "qcom,crypto-v5.1", }, { .compatible =3D "qcom,crypto-v5.4", }, @@ -261,6 +328,7 @@ static struct platform_driver qce_crypto_driver =3D { .driver =3D { .name =3D KBUILD_MODNAME, .of_match_table =3D qce_crypto_of_match, + .pm =3D &qce_crypto_pm_ops, }, }; module_platform_driver(qce_crypto_driver); --=20 2.34.1