From nobody Tue Feb 10 06:07:33 2026 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F0D11368272 for ; Mon, 9 Feb 2026 10:42:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770633729; cv=none; b=dlrry35DeFkDVWWsG4W97l6HdDYjUd5wXxxstxFA9AMSMNz7ZTXzjjb6fmznD1KGf66iDJSqItFVoYyrzHePisQadt0z5CoevjURKv5qEq494ion+xGncZQIjKCJYqf7EJ8E3AcZFs5iUTgnvm5Hab7VLmk9kKwY1TEA+N0GYJY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770633729; c=relaxed/simple; bh=YYEYs0OVa9JHUJNAgRxGuS/RThNKiarmRH+qNjJAqGw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=BJNha1TAXyqYX8PGqqWPg3dviTtjPuTi7qZp8fJTLfG8617i/xcTPcLzWp0xMRhBGAsNbanQ+gC/lwe+zREzVC4rGIZdCk4hxDYgGLI9jO7pnmTtXUpzLd1Mf0ymm7zjAdNZQgMEbKsbPvkXyVFvl/zq6LNa7IaHtOsBgk+kOPk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=gTYN87vk; arc=none smtp.client-ip=209.85.128.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="gTYN87vk" Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-4832701b9b7so13886285e9.2 for ; Mon, 09 Feb 2026 02:42:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1770633727; x=1771238527; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7lS5nOyECwdNHUk0qKYzMpv/hk9cm/TFVPk/DA1BNXw=; b=gTYN87vkfEv0I9VVpsd43TNFUQvVxGwA/FRLO1s5y/cGks2sg+u0nDA5LIvJWMeK4n SvMZzBoiqeP7ehwJJFQfEexbke2fCzsiBvVM357srQa2ADbCR4QIAg3Hd7Ls5SPqjv4H M+HNs5JofVAID1cBOwZ9FMtCSWTUbHByDTa6IHEaP83SQMvBQv2sKR61B0A3yeLBpnZJ nVruS+swv5G2tGLfYpkLyIPHjtYPG2b4WZcTxyB32o+Tph86Mu5mFc0aijraQof4f94a ZJFln5h1u4uAbpavz9SZgbsZk/hf4x1g71YBYXu92dH0xzKQfcwK+fombcAZJAkedzmD rKxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770633727; x=1771238527; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=7lS5nOyECwdNHUk0qKYzMpv/hk9cm/TFVPk/DA1BNXw=; b=TC9s0KFCVdqPkBJpNXPgjMKVd8A4c0sEFljDj6p528ziSmraAaw60iIP9I8L06dQRZ Ba+Oz+3gEGdZSyghdzpMdtihM5EwoGbbKPkhZJmmAYxY/GbxozQdB6K68iryFjkvHzQu 0YCel7vZiRRPPpiVEA+r+c+RLcSyYnT/wzCCFa1mSmALmSWHVWIvqWQSCd2/KUrK6cpI UXtQwEkcmin3anhEmBCQtIQquhBAIk3wMZtemDN2UQhtLAmohC2L4auKvlbJ46flpOkn lTZpt+jDJISznhkSIyjqQz5Md0HvkJcO0Fbt34ZZtVuqM7brxzmMQDVQ3IiB+M+SsIN5 go4A== X-Gm-Message-State: AOJu0Yw8G3rIDbk0+VJojj/kTVtozmeezLDvTvLy3JyWdgQEwNuDm/O1 edQ03Frzdb7OrdcY0i1pebC5sfFBBGYAK3TQGcfSQfo68ZTujzoVHLGx X-Gm-Gg: AZuq6aIj9wdpQKrx86gioIHgjjW0XR7B5W7bejHFLoNWovsmIPf3bHrVC80+ADzFWdj tSyaEG+VmUfkN6eRVERj+LFkfSLaIGNhh0gtyRnYErHbXM0pClCXw6uc4wQFDxwQ/qJQxxYOm// bHR1+v5dOPDJo5YBHjug/Ez1qZgQW3WHgu2ZWtguhQyvoT24soGLQHV3W0thbnf0tvk1FLd19dy zLw7IieWrD7lrOsqkb+j5js8Vu6P48f19mh2qmlx56KMz13S9SevMj54mDCfEG3HwA+chubwf8n awaapVRgZoxvhrULRG/i4brGukI+F/8dNa7txXEFPDb85OI5QlKu2dnwqInZsM42qHpzUEpA0i4 J+s11CDwfH/KKiFmbzI5Nze9dslH72PV/VpQxdNTpimImeoDWEqMHz1WSfg9eUI1nsYOkNMNYLW a8z5oVoAPZT6mV0Z0UeADmB/f50SkCtQ6K3hma/mRXPtXGdzOEUALyQYLzoVLdJR43JhvK+NcWL VmyVQxtC6GR5tRRJfpi6IlZSHzHILC/vvHi X-Received: by 2002:a05:600c:1d01:b0:480:1a9a:e571 with SMTP id 5b1f17b1804b1-48320213a37mr162115645e9.22.1770633727018; Mon, 09 Feb 2026 02:42:07 -0800 (PST) Received: from iku.Home ([2a06:5906:61b:2d00:436e:8b6:a7da:63b7]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-436296b20fasm25962211f8f.6.2026.02.09.02.42.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Feb 2026 02:42:06 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Thomas Gleixner , Philipp Zabel , Geert Uytterhoeven , Magnus Damm Cc: linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v3 1/6] irqchip/renesas-rzv2h: Use local node pointer Date: Mon, 9 Feb 2026 10:41:15 +0000 Message-ID: <20260209104121.26172-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260209104121.26172-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260209104121.26172-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Avoid dereferencing pdev->dev.of_node again in rzv2h_icu_probe_common(). Reuse the already available local node pointer when mapping the ICU register space. Signed-off-by: Lad Prabhakar --- v2->v3: - No change. v1->v2: - No change. --- drivers/irqchip/irq-renesas-rzv2h.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-rene= sas-rzv2h.c index da2bc43a0e12..20c0cd11ef25 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -570,7 +570,7 @@ static int rzv2h_icu_probe_common(struct platform_devic= e *pdev, struct device_no =20 platform_set_drvdata(pdev, rzv2h_icu_data); =20 - rzv2h_icu_data->base =3D devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, = NULL); + rzv2h_icu_data->base =3D devm_of_iomap(&pdev->dev, node, 0, NULL); if (IS_ERR(rzv2h_icu_data->base)) return PTR_ERR(rzv2h_icu_data->base); =20 --=20 2.52.0 From nobody Tue Feb 10 06:07:33 2026 Received: from mail-wr1-f47.google.com (mail-wr1-f47.google.com [209.85.221.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 80451368283 for ; Mon, 9 Feb 2026 10:42:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770633729; cv=none; b=bT2DMz2nikqitO+t14Ut4KQZVr92SdpZDm3RM4OTSSjCJfEgB7mNOIRKK+ZD86lz3GfykP6JaAEWtyRHYJJmBa454fjHy8UHsYAJOK6sVjZEBMPxv5TYqeJPw9xbkgDR+F99kjbABNUKltMgx2aNShMPcGSQA1XdGHTKqx+qLXE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770633729; c=relaxed/simple; bh=X8VRsDJSUKbzQeLVYD69jLukOlhuzFACaxjGzj9VlIo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=LecAHYUDf6Kcogq2he25HAIw/WB34F3PD6/Fam3j13C9fXheWAHl3PgLEWWD8TEwH5Tu28Cl7O8MFUpqMXXgbEcgUa1TX4pmtJMxNwtKfNCjUhdjEaHRvBxBhuKOTD6eDM84qvDG5MnO7Fsm7ZPq54c8LnWtdUJaIKYLJxi3N/4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=LC62rWA1; arc=none smtp.client-ip=209.85.221.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="LC62rWA1" Received: by mail-wr1-f47.google.com with SMTP id ffacd0b85a97d-436317c80f7so1103856f8f.1 for ; Mon, 09 Feb 2026 02:42:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1770633728; x=1771238528; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rjZGwoGLvpD/x60R9yhO9bbOT/PRB//ibosQk+nz2+I=; b=LC62rWA1K7KciWYqJnfuHL7CJZCN+gg4p5StCucztjfd67sJmod+wEn6Nain+aRNjI dRPG0kBaOeKu9Y59+PMsJvF1GVMTbweCCc9ty5ZaRUoKlnDsbocZpR3zXcbQDLdz7PaX Rg5UJO07EneZdV3LwEHuhjYfc0yqyqQuACqHOxo9AFQdCbr0fvu4gtYC0FlAVgyVRbIG IMl3Cdzf87rsbMUZdRSg96VQEBDuTWNyp1kdIqP0VF+l2BW8m0mtude2UyWL/AqR/JP8 iHXqeIBTQBZciEDzfb7RnKBxwJCcVi0T5ivFX611F2Inh1Es7FzPH6ilB/U5CleB7LeJ n9GA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770633728; x=1771238528; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=rjZGwoGLvpD/x60R9yhO9bbOT/PRB//ibosQk+nz2+I=; b=DCZ4SCNj516WHA2r726tzVFALqA4o5RcYng6YCqzq1gLfspuIXtvsWriEdkVFstTkE o4Sx8BILsDWNg5VM2oXdAlH+xb9Hb5l3UT8JjIMlXrKeoBHg+DAqxEWpqjP/JBevtkcN 1jQSSnlN9PkvTV+BqMPYQp/Jq6ik89Wf/Ss0RUv1jNY/9ZEvSWKvbeb7Baio64/omARO 54KZKNQp/GoB256Dhxb9ouNM6AQWo2aGaXz9W6WkpWft9cqI37vuAAIOkUF0F031ZITa QO9m7TrUA7gkoCL0oN8eBWW1JDft8vToXP5rByRBpBPi37psQEyWaUfSCRscsGyfs4CW Z63w== X-Gm-Message-State: AOJu0YzIgL9bMgAHScY2iRATwwsOQAz+1H8+1dN0PF6TFxdwVyN3PZpM gi/P4hv2zS+GJJ/9dFFeG2JBkvImA9iqJ7oo9hO3Uw/MLiQkSqbvQUyo X-Gm-Gg: AZuq6aKdZ2QhUwOXxxaxud0dsldAZ3ezf//Sj1EsjLr/EoeB/XoAkfu4gxSzXF2VhT1 kw9/tzVmYpprUqIgn+P0VhCFaoZBBfZlXwwyAMYaOERuqmktKuAg/LQ7mfeUW1pPvCeh+1iWG41 U2IoWG4ySEW0ejWzlS+txCyVGikrnN3Lvp8g2Ukpls4tUAzpnYZNuT9GfsnUNyjNuPPKPOQjd9z 9LYH+ynjODLpVUqOOnvaP2GGuopW9pg1kupEGSB4xy7px6H30DQYpeiDY1VBSvFDzHmK0RA2w0m uIfvDZTB5lPkLnj6VTS2D6tiq0iIRmQyB9oNViaxnU162G+1U6u8/+U36/JoaruHdXMvlarN2Mw 3+B5FRZktmWDG+i642sBvUupqLwrlEVEhhfdyRJTrPlq1mMgOsmg1zmTMuKDlLDd76OaeN/aVGy Q1AHJlJtXWUK77DIjdV2iHeMONKtucEirEk4vW2zhHHbPUhs80WTs5KrhP7YYLhZmtzkU6Di0Ad mgalyuKR7PlZ6Qg/Hf6GYk2Vb0c55ioNzs= X-Received: by 2002:a05:6000:2210:b0:435:92c6:d556 with SMTP id ffacd0b85a97d-4362933ec62mr18293299f8f.16.1770633727746; Mon, 09 Feb 2026 02:42:07 -0800 (PST) Received: from iku.Home ([2a06:5906:61b:2d00:436e:8b6:a7da:63b7]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-436296b20fasm25962211f8f.6.2026.02.09.02.42.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Feb 2026 02:42:07 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Thomas Gleixner , Philipp Zabel , Geert Uytterhoeven , Magnus Damm Cc: linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v3 2/6] irqchip/renesas-rzv2h: Use local device pointer in ICU probe Date: Mon, 9 Feb 2026 10:41:16 +0000 Message-ID: <20260209104121.26172-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260209104121.26172-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260209104121.26172-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Use a local struct device pointer in rzv2h_icu_probe_common() to avoid repeated dereferencing of pdev->dev. Signed-off-by: Lad Prabhakar --- v2->v3: - No change. v1->v2: - No change. --- drivers/irqchip/irq-renesas-rzv2h.c | 29 +++++++++++++++-------------- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-rene= sas-rzv2h.c index 20c0cd11ef25..766b981cf3d8 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -555,57 +555,58 @@ static int rzv2h_icu_probe_common(struct platform_dev= ice *pdev, struct device_no { struct irq_domain *irq_domain, *parent_domain; struct device_node *node =3D pdev->dev.of_node; + struct device *dev =3D &pdev->dev; struct reset_control *resetn; int ret; =20 parent_domain =3D irq_find_host(parent); if (!parent_domain) { - dev_err(&pdev->dev, "cannot find parent domain\n"); + dev_err(dev, "cannot find parent domain\n"); return -ENODEV; } =20 - rzv2h_icu_data =3D devm_kzalloc(&pdev->dev, sizeof(*rzv2h_icu_data), GFP_= KERNEL); + rzv2h_icu_data =3D devm_kzalloc(dev, sizeof(*rzv2h_icu_data), GFP_KERNEL); if (!rzv2h_icu_data) return -ENOMEM; =20 platform_set_drvdata(pdev, rzv2h_icu_data); =20 - rzv2h_icu_data->base =3D devm_of_iomap(&pdev->dev, node, 0, NULL); + rzv2h_icu_data->base =3D devm_of_iomap(dev, node, 0, NULL); if (IS_ERR(rzv2h_icu_data->base)) return PTR_ERR(rzv2h_icu_data->base); =20 ret =3D rzv2h_icu_parse_interrupts(rzv2h_icu_data, node); if (ret) { - dev_err(&pdev->dev, "cannot parse interrupts: %d\n", ret); + dev_err(dev, "cannot parse interrupts: %d\n", ret); return ret; } =20 - resetn =3D devm_reset_control_get_exclusive_deasserted(&pdev->dev, NULL); + resetn =3D devm_reset_control_get_exclusive_deasserted(dev, NULL); if (IS_ERR(resetn)) { ret =3D PTR_ERR(resetn); - dev_err(&pdev->dev, "failed to acquire deasserted reset: %d\n", ret); + dev_err(dev, "failed to acquire deasserted reset: %d\n", ret); return ret; } =20 - ret =3D devm_pm_runtime_enable(&pdev->dev); + ret =3D devm_pm_runtime_enable(dev); if (ret < 0) { - dev_err(&pdev->dev, "devm_pm_runtime_enable failed, %d\n", ret); + dev_err(dev, "devm_pm_runtime_enable failed, %d\n", ret); return ret; } =20 - ret =3D pm_runtime_resume_and_get(&pdev->dev); + ret =3D pm_runtime_resume_and_get(dev); if (ret < 0) { - dev_err(&pdev->dev, "pm_runtime_resume_and_get failed: %d\n", ret); + dev_err(dev, "pm_runtime_resume_and_get failed: %d\n", ret); return ret; } =20 raw_spin_lock_init(&rzv2h_icu_data->lock); =20 irq_domain =3D irq_domain_create_hierarchy(parent_domain, 0, ICU_NUM_IRQ, - dev_fwnode(&pdev->dev), &rzv2h_icu_domain_ops, + dev_fwnode(dev), &rzv2h_icu_domain_ops, rzv2h_icu_data); if (!irq_domain) { - dev_err(&pdev->dev, "failed to add irq domain\n"); + dev_err(dev, "failed to add irq domain\n"); ret =3D -ENOMEM; goto pm_put; } @@ -616,12 +617,12 @@ static int rzv2h_icu_probe_common(struct platform_dev= ice *pdev, struct device_no =20 /* * coccicheck complains about a missing put_device call before returning,= but it's a false - * positive. We still need &pdev->dev after successfully returning from t= his function. + * positive. We still need dev after successfully returning from this fun= ction. */ return 0; =20 pm_put: - pm_runtime_put(&pdev->dev); + pm_runtime_put(dev); =20 return ret; } --=20 2.52.0 From nobody Tue Feb 10 06:07:33 2026 Received: from mail-wr1-f46.google.com (mail-wr1-f46.google.com [209.85.221.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A13C369202 for ; Mon, 9 Feb 2026 10:42:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770633730; cv=none; b=GOux6zlu2PpczMVNHgoW0ooRjSiFSnomcmeLV+gckEArjYTIwI/auYsv093sCwVAR6RMz8QqJ6+eMZLJ8hrLVftnViiI59Y37FpTeGxclAQkxlitkxIKi8VsFluvYMnpZQn2J3RhU9pkYhlomYqWceScfatBGIYhsSoDnIOJWlM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770633730; c=relaxed/simple; bh=fxt3A+tirf3Wg8wHczFX4y/PTivJ+DfuE55aboPK3Vc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=mXZBiRa/4KN0jbRktHBo2Ga3a8TDHvBedgzC67xL69cLSVqHvxw2vQxhIwlGOiryaLQkG+10T13F++0+46qtpclA85NqO+MHpj3sI2GuepKximnrJY6vou8Cexk9XbctDeTsScb6X8c1UjsgXxqNtNmhwx9n2Z6j6xaYJcSY04U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=OEi6Lsw0; arc=none smtp.client-ip=209.85.221.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="OEi6Lsw0" Received: by mail-wr1-f46.google.com with SMTP id ffacd0b85a97d-43590777e22so1693281f8f.3 for ; Mon, 09 Feb 2026 02:42:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1770633729; x=1771238529; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DQGNT8v1FwtWiEhdds68iZnn1sJN93rwtii+mIzcGis=; b=OEi6Lsw0GpGG0HGErnAvWtF0HOOvvAAmnCra9UCOGc40XFv88deSRxEwiGJPD/H581 YrpfqTNwUz/5f0Z2CJ57QuimBQUi3ZFnhJOUoe5eIa6pAzuV8A3+aqAXMkLH6nF6gjK+ mJ7KZDx8i1p/2Uw4b1J78zG5C0mdxjRWpzp1G3TfuTv/p9rQVOlmfBVT2f2cO3mOOvtg dyvZN/s1HctFX9OuVRlm/ExlGaMH7yri+Ev08torsjhb+HhGO7+CJvxAl5JKZhIGib7K FEqAYM3pv8CAEQN6I5i8lgqIKyZMjauVD9VHG75y8QAXXKXD6xvfhN2jvv/YED8tHrFN nYOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770633729; x=1771238529; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=DQGNT8v1FwtWiEhdds68iZnn1sJN93rwtii+mIzcGis=; b=JlO31gH83XlgFRsAD+xAtvmctdEd0yYhj4vhoGBE6pcMxreWm2hzRQ6DRC3YSKZ74z ccW5Nz5F7zLZjQCO6w0urz99hL39T//LUAF/Skm5sqcEbWH3QtXeUx0i0hrBiSFP8mux NqhajZLBPDuQ8xji5hWkgsmuuUXYFgz2VYoASXGem83hB9xouUtuQTGkjXy7yuOYbUED n8qzxjNEPA2zPjIlwENT1MTIiUHnVx2mw+fHGJLwzpMmaaRPOC3VKOl2znpbMb0onu33 1E+9sAKsoxuYpsXNw6gG7hOKOoQv5JNRYnpTTCvpcMnVDYVNbQJb2z2iX0d3MINEzTOk PaFA== X-Gm-Message-State: AOJu0YxLaxDUMDA78P6/ceWNGHDzepICszniR+q0r2EhSZ4s8ZDo445c 88PMRTkleog3yGIehOQwfc6aVxF5p3tOvJF0OJy+DUSg9JuIQQVTogdY X-Gm-Gg: AZuq6aLHHGGb2SFwsdCDB2756klfFXDAGudDJhTzY24Ov4M8ZMQTE2xinmiyc92XUyR rqYXgBivSOXM+JjlpMx/xgR5ujfj4biWGEDu1qcNPECNlpFSMpipgLNiyBmNkRsa/2jjr6uYxoI Ri1PgcU/I+tu2JQqeHVWG/BEMBAEyDER0Bd8KiWsCmheOGm/YIywzrkfQ0Ij2rF+G6MyiVZpFAz 4CprX5zJLnhlhl3rfAidVDFNI2ntUE6PtwkDPyqyOjfrrVDKKZ89fWO3/khzA3VAW0qdDaaHF/4 FQUdkBieUMTVSJyfpAFwW1XaU2FAZqUs3oLrJ5YEGqVLPgtm2Ry5htvE9tIQuQ1LJL4EJpHbZQY OTIqEo/2Gg0riPJb06JxspE0AEzepmBKecI4Obiy4WIHEwXZPino5FQ8a9R/iwok/XokMvQzZbs SChKM3uCq8idOoKZkZ11pYNlqVg0uAqKmjI9UzYg7VGtpWQTrqXTSi+klK5wlmnle/sFBPsr6xu tV2Qxtl7ZSv3bxMVnVVq4qR X-Received: by 2002:a05:6000:1843:b0:437:711c:8750 with SMTP id ffacd0b85a97d-437711c8a40mr2918530f8f.46.1770633728802; Mon, 09 Feb 2026 02:42:08 -0800 (PST) Received: from iku.Home ([2a06:5906:61b:2d00:436e:8b6:a7da:63b7]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-436296b20fasm25962211f8f.6.2026.02.09.02.42.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Feb 2026 02:42:08 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Thomas Gleixner , Philipp Zabel , Geert Uytterhoeven , Magnus Damm Cc: linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v3 3/6] irqchip/renesas-rzv2h: Switch to using dev_err_probe() Date: Mon, 9 Feb 2026 10:41:17 +0000 Message-ID: <20260209104121.26172-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260209104121.26172-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260209104121.26172-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Make use of dev_err_probe() to simplify rzv2h_icu_probe_common(). Keep dev_err() for -ENOMEM paths, as dev_err_probe() does not print for allocation failures, ensuring they remain visible in logs. Signed-off-by: Lad Prabhakar --- v2->v3: - No change. v1->v2: - No change. --- drivers/irqchip/irq-renesas-rzv2h.c | 32 ++++++++++------------------- 1 file changed, 11 insertions(+), 21 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-rene= sas-rzv2h.c index 766b981cf3d8..4aa772ba1a1f 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -560,10 +560,8 @@ static int rzv2h_icu_probe_common(struct platform_devi= ce *pdev, struct device_no int ret; =20 parent_domain =3D irq_find_host(parent); - if (!parent_domain) { - dev_err(dev, "cannot find parent domain\n"); - return -ENODEV; - } + if (!parent_domain) + return dev_err_probe(dev, -ENODEV, "cannot find parent domain\n"); =20 rzv2h_icu_data =3D devm_kzalloc(dev, sizeof(*rzv2h_icu_data), GFP_KERNEL); if (!rzv2h_icu_data) @@ -576,29 +574,21 @@ static int rzv2h_icu_probe_common(struct platform_dev= ice *pdev, struct device_no return PTR_ERR(rzv2h_icu_data->base); =20 ret =3D rzv2h_icu_parse_interrupts(rzv2h_icu_data, node); - if (ret) { - dev_err(dev, "cannot parse interrupts: %d\n", ret); - return ret; - } + if (ret) + return dev_err_probe(dev, ret, "cannot parse interrupts\n"); =20 resetn =3D devm_reset_control_get_exclusive_deasserted(dev, NULL); - if (IS_ERR(resetn)) { - ret =3D PTR_ERR(resetn); - dev_err(dev, "failed to acquire deasserted reset: %d\n", ret); - return ret; - } + if (IS_ERR(resetn)) + return dev_err_probe(dev, PTR_ERR(resetn), + "failed to acquire deasserted reset\n"); =20 ret =3D devm_pm_runtime_enable(dev); - if (ret < 0) { - dev_err(dev, "devm_pm_runtime_enable failed, %d\n", ret); - return ret; - } + if (ret < 0) + return dev_err_probe(dev, ret, "devm_pm_runtime_enable failed\n"); =20 ret =3D pm_runtime_resume_and_get(dev); - if (ret < 0) { - dev_err(dev, "pm_runtime_resume_and_get failed: %d\n", ret); - return ret; - } + if (ret < 0) + return dev_err_probe(dev, ret, "pm_runtime_resume_and_get failed\n"); =20 raw_spin_lock_init(&rzv2h_icu_data->lock); =20 --=20 2.52.0 From nobody Tue Feb 10 06:07:33 2026 Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D34B636922B for ; Mon, 9 Feb 2026 10:42:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770633732; cv=none; b=RfroBx05O/G1v4EeeePC7f6naEDPStdLos+eTjvW4rkGNeWb/HKEEMsNsH/JiS/Rggy1UAVVHF8QPGwKEiyHoC6GfflFcAoNl1JWsc4u3njz8CXKshnWxc8dtgCThlazLKkRNVvuoVlU7CeIhmj0moUtQSo59F9jGaesLLYq0v8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770633732; c=relaxed/simple; bh=TqaRlfcksReFLFPjLOJqka0OjTG44POzeHc64dTRc60=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=nrZC46DehlnP1RBDtaiX2nSispYhWYeI5OoOVD4RHm2MI+9hZRIASjSEaUd+GQBvuKie3nwkWK3sL5XaeuyxWKQhIBOigvJza/T2WeS4zfBp4veuIM8WOkGlW35zo3d2Yj+d18HXTBUrvNKgEtG4TRtvWEpTggi0M9VC8GebSJc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=YMnA1nJy; arc=none smtp.client-ip=209.85.221.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="YMnA1nJy" Received: by mail-wr1-f43.google.com with SMTP id ffacd0b85a97d-4376c0bffc1so756931f8f.0 for ; Mon, 09 Feb 2026 02:42:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1770633730; x=1771238530; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LinQMk8vpLuA2yrBKVt1Nrvfv80xEiK4QCTzQwij+FQ=; b=YMnA1nJybXmepnBxZsfRtCRu6sevIA+B30zk34LPUAoX8+YmIdeDg2ZHVxJnwnM92A Sl6tr3gcvh3bjbt3q0sJXnnlV5i7R9bmh6o2SzdvmvjFm3Lof6fVsfl64UVYpXOTaGLf IZu+9kU0HeD7jGQMAsYVmTW2hOop0rSmePhl2frQG7XI32qqvLhpjaBpV2Ta8Q4bdCGc WIrCyXIQfcQN/FRgpPzvtKxz7l1WE6xlSyLjj0+XJ9shZpTZeUzygK5DFhmnzSZG3/4U zd32SBYLWSP1OeXV36kxtYNQip/KD5B5VNyVWAxtmlzxUvpnKBxEAeNHETohxW1NcC0w y/Wg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770633730; x=1771238530; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=LinQMk8vpLuA2yrBKVt1Nrvfv80xEiK4QCTzQwij+FQ=; b=pz3v6FUIqvCA4Cq5QZIYyT++XfgDTq8Ro4o2hza3rIwX3n9nYzEYfetc/HXH8cIfBT nh01xqDpULE39F2nNc53Pi1ev63kyVEXM8X7kTY7+DkJi0egZLUshdIsG22rGgNOUIJx lliGe/VdIy6YuGw9fcdIjI7f2B9OtTFaVZSk8PHGOSI/JiZJn0spMbi3FNEe5bmmycyg BMJyznrUqYpIH8zdFkL7YysDRg1RSu7aLxvhJJnj3kl45ximXvntXQDP18O4ja4M9JS8 rGEuJrHVrLHw1KvAQPA/G0ZeJ/siwswrDXK6tPfOlDswXpsi8dlAMg1TUs8TSZNu/koA H15g== X-Gm-Message-State: AOJu0YwxCybnfHHrJCh5P7j8haUnvLa+rjdcDjLpksb9ooKs7bpLV2BR jKNmf2IXSjYE3FpMAchxQsqEwsecCuZbNmXgFTRTml6iC1ZIbbjBMk63 X-Gm-Gg: AZuq6aJW1AHWKzwVP5juKTO7SvQu3+kLUBfbZpaEa+WIpCGqHs3hKjM/oHhTMqWYeCv VtwAdYZpNUhJBXJwPxcXtH5IIeeE+6ycocVUkNkZ91KNvW5MoYwnlC14HCu8y5D1Q5OsnE6T0us JwWBK9d6bnytjhU23JyaBnQyP8kryhM3qtfgSzbmgQFxlaKt3dWNnjHiau47O4xBmthx7+Z4h54 iiKGAxPExxXeChbbddbQSEQvMiSR3oxCj10GrIuybPfdTFqFmG7wQr+oGHvJnyyPR6XxBq0uyP1 AQzqLHfiCTduDiayxdmGrgHQUQsRJcrRYIQlhbQZ75+ZE6n1T4wqdP8pD3zc/9KDwnBNXRceRpP UNCuN2dFK9vHP6WyDV7fuHPcVkRuWFey9B7gWpeJlR6reAxaDgvE6FeWIyRusLdHX2DYtPxCPZl q0uQrmlG2+kowoNTu3NOtkhPg+uFoBFyRhwsnIgXJla+pbhPpRAFdlX3vFRDmQ8Txn+JryP6P6M 45lkCy/ivaYFsuTZgeY114A61S2zBL2LjY= X-Received: by 2002:a05:600c:3e0b:b0:47a:810f:1d06 with SMTP id 5b1f17b1804b1-483209291eamr154277925e9.4.1770633729738; Mon, 09 Feb 2026 02:42:09 -0800 (PST) Received: from iku.Home ([2a06:5906:61b:2d00:436e:8b6:a7da:63b7]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-436296b20fasm25962211f8f.6.2026.02.09.02.42.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Feb 2026 02:42:09 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Thomas Gleixner , Philipp Zabel , Geert Uytterhoeven , Magnus Damm Cc: linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v3 4/6] irqchip/renesas-rzv2h: Make IRQ type handling range-aware Date: Mon, 9 Feb 2026 10:41:18 +0000 Message-ID: <20260209104121.26172-5-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260209104121.26172-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260209104121.26172-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Refine IRQ type handling to explicitly bound IRQ and TINT ranges and dispatch based on the hardware IRQ number. This restructures the logic to clearly separate NMI, IRQ, and TINT handling and ensures out-of-range interrupts are ignored safely. The change prepares the driver for adding CA55 interrupts into the IRQ hierarchy domain by making the interrupt classification explicit and extensible. Signed-off-by: Lad Prabhakar --- v2->v3: - Updated the check in rzv2h_icu_alloc() to ensure hwirq is within the TINT range when extracting TINT information. v1->v2: - New patch. --- drivers/irqchip/irq-renesas-rzv2h.c | 60 +++++++++++++++++++---------- 1 file changed, 40 insertions(+), 20 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-rene= sas-rzv2h.c index 4aa772ba1a1f..d4a47df0e26e 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -25,9 +25,11 @@ /* DT "interrupts" indexes */ #define ICU_IRQ_START 1 #define ICU_IRQ_COUNT 16 -#define ICU_TINT_START (ICU_IRQ_START + ICU_IRQ_COUNT) +#define ICU_IRQ_LAST (ICU_IRQ_START + ICU_IRQ_COUNT - 1) +#define ICU_TINT_START (ICU_IRQ_LAST + 1) #define ICU_TINT_COUNT 32 -#define ICU_NUM_IRQ (ICU_TINT_START + ICU_TINT_COUNT) +#define ICU_TINT_LAST (ICU_TINT_START + ICU_TINT_COUNT - 1) +#define ICU_NUM_IRQ (ICU_TINT_LAST + 1) =20 /* Registers */ #define ICU_NSCNT 0x00 @@ -175,18 +177,27 @@ static void rzv2h_icu_eoi(struct irq_data *d) u32 bit; =20 scoped_guard(raw_spinlock, &priv->lock) { - if (hw_irq >=3D ICU_TINT_START) { - tintirq_nr =3D hw_irq - ICU_TINT_START; - bit =3D BIT(tintirq_nr); - if (!irqd_is_level_type(d)) - writel_relaxed(bit, priv->base + priv->info->t_offs + ICU_TSCLR); - } else if (hw_irq >=3D ICU_IRQ_START) { + switch (hw_irq) { + case 0: + /* Clear NMI */ + writel_relaxed(ICU_NSCLR_NCLR, priv->base + ICU_NSCLR); + break; + case ICU_IRQ_START ... ICU_IRQ_LAST: + /* Clear IRQ */ tintirq_nr =3D hw_irq - ICU_IRQ_START; bit =3D BIT(tintirq_nr); if (!irqd_is_level_type(d)) writel_relaxed(bit, priv->base + ICU_ISCLR); - } else { - writel_relaxed(ICU_NSCLR_NCLR, priv->base + ICU_NSCLR); + break; + case ICU_TINT_START ... ICU_TINT_LAST: + /* Clear TINT */ + tintirq_nr =3D hw_irq - ICU_TINT_START; + bit =3D BIT(tintirq_nr); + if (!irqd_is_level_type(d)) + writel_relaxed(bit, priv->base + priv->info->t_offs + ICU_TSCLR); + break; + default: + break; } } =20 @@ -200,7 +211,7 @@ static void rzv2h_tint_irq_endisable(struct irq_data *d= , bool enable) u32 tint_nr, tssel_n, k, tssr; u8 nr_tint; =20 - if (hw_irq < ICU_TINT_START) + if (hw_irq < ICU_TINT_START || hw_irq > ICU_TINT_LAST) return; =20 tint_nr =3D hw_irq - ICU_TINT_START; @@ -421,12 +432,22 @@ static int rzv2h_icu_set_type(struct irq_data *d, uns= igned int type) unsigned int hw_irq =3D irqd_to_hwirq(d); int ret; =20 - if (hw_irq >=3D ICU_TINT_START) - ret =3D rzv2h_tint_set_type(d, type); - else if (hw_irq >=3D ICU_IRQ_START) - ret =3D rzv2h_irq_set_type(d, type); - else + switch (hw_irq) { + case 0: + /* NMI */ ret =3D rzv2h_nmi_set_type(d, type); + break; + case ICU_IRQ_START ... ICU_IRQ_LAST: + /* IRQ */ + ret =3D rzv2h_irq_set_type(d, type); + break; + case ICU_TINT_START ... ICU_TINT_LAST: + /* TINT */ + ret =3D rzv2h_tint_set_type(d, type); + break; + default: + ret =3D -EINVAL; + } =20 if (ret) return ret; @@ -508,11 +529,10 @@ static int rzv2h_icu_alloc(struct irq_domain *domain,= unsigned int virq, unsigne * hwirq is embedded in bits 0-15. * TINT is embedded in bits 16-31. */ - if (hwirq >=3D ICU_TINT_START) { - tint =3D ICU_TINT_EXTRACT_GPIOINT(hwirq); + tint =3D ICU_TINT_EXTRACT_GPIOINT(hwirq); + if (tint || (hwirq >=3D ICU_TINT_START && hwirq <=3D ICU_TINT_LAST)) { hwirq =3D ICU_TINT_EXTRACT_HWIRQ(hwirq); - - if (hwirq < ICU_TINT_START) + if (hwirq < ICU_TINT_START || hwirq > ICU_TINT_LAST) return -EINVAL; } =20 --=20 2.52.0 From nobody Tue Feb 10 06:07:33 2026 Received: from mail-wr1-f44.google.com (mail-wr1-f44.google.com [209.85.221.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 808E036827F for ; Mon, 9 Feb 2026 10:42:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770633732; cv=none; b=QtznxH+3Kt/P6N22oIjp/Jn8xSdyxmVhVxODkH7mcZhWi7/G7jZ++ZprznNUcsUTsRzXW8wJBkBLTKNudCMxg7cbraiEH4zvOSbeIxADJ804wkB7EotTHwUlZfYKW1yygMdiQ6UacfTqIorJc1akDMBzgOV9cHxJS9exbX9Cidg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770633732; c=relaxed/simple; bh=T/xGIUcNLulLdJL79PlV2KcyCy8itN3/jJLU1J2lZtw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=IqONoaP1DFkfDvFNBVenFTDdCSqKcCYv8MjymApQvXw9pBoqXo/sZO/tVqz0Dq7bsqEV9SjOLs3PNkeYecA+WUIEinLgLeSRUBM2uKFRdSpAKS0Ml7gQvbOS6g58exKa2x7E9FDjNlj7+7pgVqaSnEk8nR6PR1PQcFu4lu6achI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=NvsM9yHq; arc=none smtp.client-ip=209.85.221.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="NvsM9yHq" Received: by mail-wr1-f44.google.com with SMTP id ffacd0b85a97d-43767807cf3so826654f8f.1 for ; Mon, 09 Feb 2026 02:42:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1770633731; x=1771238531; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YIuS6VE4RcagWoTJa6lurwoAPv6InRM+7MTVEIanWYY=; b=NvsM9yHqymyES+y36owmHS49umqtmsGirhG/zm66vCXdwNlJUdJEsZJI74LFiexJSK OL4EK6dMuoVSHOiwiKTs2zjLEK3V/dzCM+/qsnHgQYjX1U9rcEh3sJYaG1DYWOhp1m1Z qFudtAv52aOTS2BYWkrz5Gf1mxrDn0I0NJLC6vSsct6t1dmZ75iF78zBTwxNq318hE3F ozVO5Bh3wJlOsA6El/L7UjR3UCAitgD1A3nNBSt22eDdzksMLu5/M5jUbHYoDPi3ZtZn J+zks06BS8kI/ipqOXAtgC5XKPkOg33a5YdbewBlmFYZNJfD9PXhrqnGw06CsydgBQd5 46OA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770633731; x=1771238531; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=YIuS6VE4RcagWoTJa6lurwoAPv6InRM+7MTVEIanWYY=; b=jThEgdyGaTqbJRoZdvhI/+Ipj9vyEcAogmDnuVf5yfQF9cTWO3OxvN2P+s/WxfMeGA 8xI805oSGqtrRHQ6Gkpuy6Q5iKkLjtL2E8f5fN0/bVgc3jYByPaXw5PeZhr5JCk8qDrR +g+BUBL7NzYVl0+RKgMKOyujpLfwqtPBrJImTeNdvyNrSEOchUjlvBiRV6bC86albIed pWtaF9GtTlOa/NjOMVzIPieuV7ApFyZHJlf78ldIL/wm/xDPApvhU5PjDuMuxeEoagFY XhJaZVdxYOpIfrr+MTVPckHy/C7Albgvmfdu3wl/Mj/BEzcC7bmM4PRCtpUHJoYnnQrX wDQw== X-Gm-Message-State: AOJu0Yz6PMWgc2/BWrtrFbsyuPSNpvG1hmL1lDpa4xsG4WEarR4960oR vZkZINlJ3c/D/hd7UaamE5rKvLDzGl6MVno31AaNtqaxOGSbnKxapTAp X-Gm-Gg: AZuq6aJrIXRZu4rFaE1vXBlEGNPc25MN7xtNWtD7VeeFqrlSkOcg+HH7I2bprAegEVb VAmxX3E2klM+3+9KtZvty0A4YQEVOQ1MgGveVWQCcQFyAsQyPUzOfSunM3UzlX2s7CdrDOEib2z weAk9QlziGPxubgAXiRMrhtSgL16m1uTqfw6ZZF2Nwx+QiA5+/azCF47RzA5SUfB5xrBUWlEkhI 3LjFEDgV+Iw9xs7PSu7YEGyhBYvgfAMZou5ju04dBJF+ibkfoqbpEEQsqGjGy44myQrOWUtDmcT s24lpmhuMjZNUPm9DvfvzK9rWDlLn9VxVTEhDvTBNIySYlwzfrXdyK/L3FSu2gdVco9R4BnEnqD LGVI/wQ1T/asXa8kg2oLjdWkXrn3TRl45uMdr0G9IkJNCwaJIkivao+pOp2iqZOWwYoKtQ/jA+1 FIflHW9T1d+wXBMfsnPaApTUFdQZ5lYO/pgcHLkYzO5haoektz7+2dWImvRtlrh0W4TDFgwrJfO YGCeMJsY7YetHX2TnTuMcIy X-Received: by 2002:a05:6000:26cd:b0:425:769e:515a with SMTP id ffacd0b85a97d-436293ba69fmr17797762f8f.42.1770633730588; Mon, 09 Feb 2026 02:42:10 -0800 (PST) Received: from iku.Home ([2a06:5906:61b:2d00:436e:8b6:a7da:63b7]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-436296b20fasm25962211f8f.6.2026.02.09.02.42.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Feb 2026 02:42:10 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Thomas Gleixner , Philipp Zabel , Geert Uytterhoeven , Magnus Damm Cc: linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v3 5/6] irqchip/renesas-rzv2h: Add CA55 software interrupt support Date: Mon, 9 Feb 2026 10:41:19 +0000 Message-ID: <20260209104121.26172-6-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260209104121.26172-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260209104121.26172-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar The Renesas RZ/V2H ICU provides a software interrupt register (ICU_SWINT) that allows software to explicitly assert interrupts toward individual CA55 cores. Writing BIT(n) to ICU_SWINT triggers the corresponding interrupt. Extend the RZ/V2H ICU IRQ domain to include CA55 software interrupts as part of the hierarchical IRQ numbering, backed by the ICU_SWINT register. SW interrupts can now be triggered when GENERIC_IRQ_INJECTION is enabled. Signed-off-by: Lad Prabhakar --- v2->v3: - Replaced pr_debug with pr_info in the SWINT handler to ensure visibility of the message. v1->v2: - Made CA55 SW interrupt as part of ICU IRQ domain. - Implemented rzv2h_icu_irq_set_irqchip_state() to trigger SWINT. - Updated commit message accordingly. --- drivers/irqchip/irq-renesas-rzv2h.c | 89 ++++++++++++++++++++++++++++- 1 file changed, 86 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-rene= sas-rzv2h.c index d4a47df0e26e..bfb975f7e370 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -29,7 +30,10 @@ #define ICU_TINT_START (ICU_IRQ_LAST + 1) #define ICU_TINT_COUNT 32 #define ICU_TINT_LAST (ICU_TINT_START + ICU_TINT_COUNT - 1) -#define ICU_NUM_IRQ (ICU_TINT_LAST + 1) +#define ICU_CA55_INT_START (ICU_TINT_LAST + 1) +#define ICU_CA55_INT_COUNT 4 +#define ICU_CA55_INT_LAST (ICU_CA55_INT_START + ICU_= CA55_INT_COUNT - 1) +#define ICU_NUM_IRQ (ICU_CA55_INT_LAST + 1) =20 /* Registers */ #define ICU_NSCNT 0x00 @@ -42,6 +46,7 @@ #define ICU_TSCLR 0x24 #define ICU_TITSR(k) (0x28 + (k) * 4) #define ICU_TSSR(k) (0x30 + (k) * 4) +#define ICU_SWINT 0x130 #define ICU_DMkSELy(k, y) (0x420 + (k) * 0x20 + (y) * 4) #define ICU_DMACKSELk(k) (0x500 + (k) * 4) =20 @@ -248,6 +253,30 @@ static void rzv2h_icu_irq_enable(struct irq_data *d) irq_chip_enable_parent(d); } =20 +static int rzv2h_icu_irq_set_irqchip_state(struct irq_data *d, + enum irqchip_irq_state which, + bool state) +{ + unsigned int hwirq =3D irqd_to_hwirq(d); + struct rzv2h_icu_priv *priv; + unsigned int bit; + + if (hwirq < ICU_CA55_INT_START || hwirq > ICU_CA55_INT_LAST || + which !=3D IRQCHIP_STATE_PENDING) + return irq_chip_set_parent_state(d, which, state); + + if (!state) + return 0; + + priv =3D irq_data_to_priv(d); + bit =3D BIT(hwirq - ICU_CA55_INT_START); + + guard(raw_spinlock)(&priv->lock); + /* Trigger the software interrupt */ + writel_relaxed(bit, priv->base + ICU_SWINT); + return 0; +} + static int rzv2h_nmi_set_type(struct irq_data *d, unsigned int type) { struct rzv2h_icu_priv *priv =3D irq_data_to_priv(d); @@ -429,6 +458,7 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsi= gned int type) =20 static int rzv2h_icu_set_type(struct irq_data *d, unsigned int type) { + unsigned int gic_type =3D IRQ_TYPE_LEVEL_HIGH; unsigned int hw_irq =3D irqd_to_hwirq(d); int ret; =20 @@ -445,6 +475,11 @@ static int rzv2h_icu_set_type(struct irq_data *d, unsi= gned int type) /* TINT */ ret =3D rzv2h_tint_set_type(d, type); break; + case ICU_CA55_INT_START ... ICU_CA55_INT_LAST: + /* CA55 Software Interrupts have EDGE_RISING type */ + gic_type =3D IRQ_TYPE_EDGE_RISING; + ret =3D 0; + break; default: ret =3D -EINVAL; } @@ -452,7 +487,7 @@ static int rzv2h_icu_set_type(struct irq_data *d, unsig= ned int type) if (ret) return ret; =20 - return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH); + return irq_chip_set_type_parent(d, gic_type); } =20 static int rzv2h_irqc_irq_suspend(void *data) @@ -501,7 +536,7 @@ static const struct irq_chip rzv2h_icu_chip =3D { .irq_disable =3D rzv2h_icu_irq_disable, .irq_enable =3D rzv2h_icu_irq_enable, .irq_get_irqchip_state =3D irq_chip_get_parent_state, - .irq_set_irqchip_state =3D irq_chip_set_parent_state, + .irq_set_irqchip_state =3D rzv2h_icu_irq_set_irqchip_state, .irq_retrigger =3D irq_chip_retrigger_hierarchy, .irq_set_type =3D rzv2h_icu_set_type, .irq_set_affinity =3D irq_chip_set_affinity_parent, @@ -570,6 +605,50 @@ static int rzv2h_icu_parse_interrupts(struct rzv2h_icu= _priv *priv, struct device return 0; } =20 +static irqreturn_t rzv2h_icu_swint_irq(int irq, void *data) +{ + u8 cpu =3D *(u8 *)data; + + pr_info("SWINT interrupt for CA55 core %u\n", cpu); + return IRQ_HANDLED; +} + +static int rzv2h_icu_setup_irqs(struct platform_device *pdev, + struct irq_domain *irq_domain) +{ + bool irq_inject =3D IS_ENABLED(CONFIG_GENERIC_IRQ_INJECTION); + static const char * const rzv2h_swint_names[] =3D { + "int-ca55-0", "int-ca55-1", + "int-ca55-2", "int-ca55-3", + }; + static const u8 swint_idx[] =3D { 0, 1, 2, 3 }; + struct device *dev =3D &pdev->dev; + struct irq_fwspec fwspec; + unsigned int virq; + unsigned int i; + int ret; + + for (i =3D 0; i < ICU_CA55_INT_COUNT && irq_inject; i++) { + fwspec.fwnode =3D irq_domain->fwnode; + fwspec.param_count =3D 2; + fwspec.param[0] =3D ICU_CA55_INT_START + i; + fwspec.param[1] =3D IRQ_TYPE_EDGE_RISING; + + virq =3D irq_create_fwspec_mapping(&fwspec); + if (!virq) + return dev_err_probe(dev, -EINVAL, "failed to create IRQ mapping for %s= \n", + rzv2h_swint_names[i]); + + ret =3D devm_request_irq(dev, virq, rzv2h_icu_swint_irq, 0, dev_name(dev= ), + (void *)&swint_idx[i]); + if (ret) + return dev_err_probe(dev, ret, "Failed to request %s IRQ\n", + rzv2h_swint_names[i]); + } + + return 0; +} + static int rzv2h_icu_probe_common(struct platform_device *pdev, struct dev= ice_node *parent, const struct rzv2h_hw_info *hw_info) { @@ -625,6 +704,10 @@ static int rzv2h_icu_probe_common(struct platform_devi= ce *pdev, struct device_no =20 register_syscore(&rzv2h_irqc_syscore); =20 + ret =3D rzv2h_icu_setup_irqs(pdev, irq_domain); + if (ret) + goto pm_put; + /* * coccicheck complains about a missing put_device call before returning,= but it's a false * positive. We still need dev after successfully returning from this fun= ction. --=20 2.52.0 From nobody Tue Feb 10 06:07:33 2026 Received: from mail-wr1-f42.google.com (mail-wr1-f42.google.com [209.85.221.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 66A4C369209 for ; Mon, 9 Feb 2026 10:42:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770633733; cv=none; b=mkCn6IwKdO0a4FO9ILUY6sX8ugAnEkB5U3BmS1ovctGBvWTnVyx3A1z02NaqeUntjvgQvpQxXjAkgobRf3wZjpgGJzckWOoVGpMMMH8/tEnbPlOsijhGz0+bfj/wLWSu2mz4Wmvnk7EOXpB3vtVw/qbgUkP5dEOBxL4n6pNqShw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770633733; c=relaxed/simple; bh=gYzkVWgdBems/TFDSNMRlj8gcRtjG5dnWHKOVV8uAWg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=P64iozfONLjJst2C3nvyC8I2pvdJ51GVORtMzmAh6JCMcDROKAt6mG+GjmjOeD5XtnI8n5I3GbY5E8GG0+OO6CweqrDktZYCrNLwG71pPfUoLmzepgZa9Z2JcGP+cMH6pwJOpqaYrGSgVrcGo2uyN9T8aa9aJE1GjiCG+p79wU4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=ggzqgPgd; arc=none smtp.client-ip=209.85.221.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ggzqgPgd" Received: by mail-wr1-f42.google.com with SMTP id ffacd0b85a97d-436263e31abso2930789f8f.1 for ; Mon, 09 Feb 2026 02:42:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1770633732; x=1771238532; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=o11486/1RRk9UzWQIeXwojFYzCpvodTNfzzuPu0RgGQ=; b=ggzqgPgdsPuY3POTo2jaS/0fZsbi4kIXaBPnog5GiuGZ68z9PWYXzraBj1jICogacK Q4eYCNqJqdCU2NgYW0MXzmcm1wUTNF8lbIgPlRsPuWuZ6ojUODDFsaIsXLFNuvNMhXNq RLKaYNwugakV0nhaoBL2z1BTq4Csq0o6FWVF1i+2ffHzWWqvLWDLN7pazQuudmucPGXf QwLQo8uIHrYLF5EULfElcOIdhRXA9Q+UhPlIGAJ0xYuLdwzRpdM4SHQSMo07Oit7S53h L6NyHc2xw3n6l8WloZMqRJuI+FLzA9JSfEAm6Ia9afdvxrmaiACqOeOqQlDrNUAG8YVL TL5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770633732; x=1771238532; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=o11486/1RRk9UzWQIeXwojFYzCpvodTNfzzuPu0RgGQ=; b=ESG57jWwyrGC1Uodd2QYVff4R+e8n0ghqlRcEfG9oo9qduq9v7ukjEQfF2tLi1g7CB FMiMicN3cyUlij/B6D01wz0xzttsFJzUxK5OK6Vhf+dyLHt7uj5Jm1bhmPF7NfEgdZfC nddsuAl1WUDx60JQ0w6jEUs0WjVX4BnWRYmMCO61BiFT2LHgDR0pzjjjViibs7hKnFI9 2897CBaBwfsC4/E1gXHYD2S3PvYlN/C4zLCUjg/HFPueRystUBaQi9vwsQM4ESMkdzOT 9znpNiEOiy0RpkJvE2NHezUobtyQyjSCOZHDF21pMUiX5JPml2yqJPD8uT9XgtjgRjTZ 3ToQ== X-Gm-Message-State: AOJu0YwfIxAsbiIle3ZB5Roa5ChfnA4zyaEJKK8cSaI01JQqaB/xFR9v oRzq7E3qqwJb4/KX+RWshzQGaSyFiDPcFMZ8VOi2ztIQvglqxu7jav/K X-Gm-Gg: AZuq6aLi36kITKV9KRdKOzk/k8xK2OMW3sOM1vDJX8yGTzkMdHOlHtaj1jknkeE92PL nA4wS98Ngvg+tMxZfVHa+giRVv0xCiOA2hiTX+m1O0dA8NaSLacOWBHFyzEAjB8aKRwOw2TTdPb RdPOe5kbRoC48mtk0KOiNUUqng1l9dU2OSAQgzj1emD71WXxPjbprU0dRS3yfnx/dpT+we+QG7S WmBp8sj+yXy2UGLJdVIFnX3m+wlO20hmLRFd5t4yvw7IKtchtSH6B3UufXkGaXYNGAphD0C3DMM 53h/hHVUeo7un5NfIG6QHagD8AAFuIsgBmjthxGEFObzT0psY/auefECe9fr0q7+z8s6AmK+nnE vMhE6d5ijk5bBIle49x/iuq4xiWgSd27/5p5okUgTAhFWZL0zQQh3i7i0Xiu5W+riFIO/6GoFrB 61c+jmDo0zxErNqU9gHawxLmX+Dif1f1YuDSVl+zzf328ZHagkQ4gJBq2D8wqO/bjGy1vXBjyNe OpBObYmzy1lrfZC5qFRWYoE X-Received: by 2002:a05:6000:2c08:b0:437:6dac:4578 with SMTP id ffacd0b85a97d-4376dac47c2mr4858253f8f.42.1770633731363; Mon, 09 Feb 2026 02:42:11 -0800 (PST) Received: from iku.Home ([2a06:5906:61b:2d00:436e:8b6:a7da:63b7]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-436296b20fasm25962211f8f.6.2026.02.09.02.42.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Feb 2026 02:42:10 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Thomas Gleixner , Philipp Zabel , Geert Uytterhoeven , Magnus Damm Cc: linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v3 6/6] irqchip/renesas-rzv2h: Handle ICU error IRQ and add SWPE trigger Date: Mon, 9 Feb 2026 10:41:20 +0000 Message-ID: <20260209104121.26172-7-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260209104121.26172-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260209104121.26172-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Handle the RZ/V2H ICU error interrupt to help diagnose latched bus, ECC RAM, and CA55/IP error conditions. Extend the hardware IRQ numbering to include a single error interrupt line and route IRQCHIP_STATE_PENDING requests to hardware-triggered error injection via ICU_SWPE. Account for SoC differences in ECC RAM error register coverage so the handler only iterates over valid ECC status/clear banks, and route the RZ/V2N compatible to a probe path with the correct ECC range while keeping the existing RZ/V2H and RZ/G3E handling. Signed-off-by: Lad Prabhakar --- v2->v3: - Updated pr_debug to pr_info in the error IRQ handler to ensure visibility of the messages. v1->v2: - Made Error interrupt as part of ICU IRQ domain. - Updated rzv2h_icu_irq_set_irqchip_state() to trigger pseudo interrupt. - Updated commit message accordingly. --- drivers/irqchip/irq-renesas-rzv2h.c | 149 ++++++++++++++++++++++++++-- 1 file changed, 143 insertions(+), 6 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-rene= sas-rzv2h.c index bfb975f7e370..d4e8aab46412 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -33,7 +33,10 @@ #define ICU_CA55_INT_START (ICU_TINT_LAST + 1) #define ICU_CA55_INT_COUNT 4 #define ICU_CA55_INT_LAST (ICU_CA55_INT_START + ICU_= CA55_INT_COUNT - 1) -#define ICU_NUM_IRQ (ICU_CA55_INT_LAST + 1) +#define ICU_ERR_INT_START (ICU_CA55_INT_LAST + 1) +#define ICU_ERR_INT_COUNT 1 +#define ICU_ERR_INT_LAST (ICU_ERR_INT_START + ICU_ER= R_INT_COUNT - 1) +#define ICU_NUM_IRQ (ICU_ERR_INT_LAST + 1) =20 /* Registers */ #define ICU_NSCNT 0x00 @@ -46,7 +49,15 @@ #define ICU_TSCLR 0x24 #define ICU_TITSR(k) (0x28 + (k) * 4) #define ICU_TSSR(k) (0x30 + (k) * 4) +#define ICU_BEISR(k) (0x70 + (k) * 4) +#define ICU_BECLR(k) (0x80 + (k) * 4) +#define ICU_EREISR(k) (0x90 + (k) * 4) +#define ICU_ERCLR(k) (0xE0 + (k) * 4) #define ICU_SWINT 0x130 +#define ICU_ERINTA55CTL(k) (0x338 + (k) * 4) +#define ICU_ERINTA55CRL(k) (0x348 + (k) * 4) +#define ICU_ERINTA55MSK(k) (0x358 + (k) * 4) +#define ICU_SWPE 0x370 #define ICU_DMkSELy(k, y) (0x420 + (k) * 0x20 + (y) * 4) #define ICU_DMACKSELk(k) (0x500 + (k) * 4) =20 @@ -97,6 +108,10 @@ #define ICU_RZG3E_TSSEL_MAX_VAL 0x8c #define ICU_RZV2H_TSSEL_MAX_VAL 0x55 =20 +#define ICU_SWPE_NUM 16 +#define ICU_NUM_BE 4 +#define ICU_NUM_A55ERR 4 + /** * struct rzv2h_irqc_reg_cache - registers cache (necessary for suspend/re= sume) * @nitsr: ICU_NITSR register @@ -115,12 +130,16 @@ struct rzv2h_irqc_reg_cache { * @t_offs: TINT offset * @max_tssel: TSSEL max value * @field_width: TSSR field width + * @ecc_start: Start index of ECC RAM interrupts + * @ecc_end: End index of ECC RAM interrupts */ struct rzv2h_hw_info { const u8 *tssel_lut; u16 t_offs; u8 max_tssel; u8 field_width; + u8 ecc_start; + u8 ecc_end; }; =20 /* DMAC */ @@ -259,10 +278,10 @@ static int rzv2h_icu_irq_set_irqchip_state(struct irq= _data *d, { unsigned int hwirq =3D irqd_to_hwirq(d); struct rzv2h_icu_priv *priv; + void __iomem *offset; unsigned int bit; =20 - if (hwirq < ICU_CA55_INT_START || hwirq > ICU_CA55_INT_LAST || - which !=3D IRQCHIP_STATE_PENDING) + if (which !=3D IRQCHIP_STATE_PENDING) return irq_chip_set_parent_state(d, which, state); =20 if (!state) @@ -271,9 +290,33 @@ static int rzv2h_icu_irq_set_irqchip_state(struct irq_= data *d, priv =3D irq_data_to_priv(d); bit =3D BIT(hwirq - ICU_CA55_INT_START); =20 + switch (hwirq) { + case ICU_CA55_INT_START ... ICU_CA55_INT_LAST: + bit =3D BIT(hwirq - ICU_CA55_INT_START); + offset =3D priv->base + ICU_SWINT; + break; + case ICU_ERR_INT_START ... ICU_ERR_INT_LAST: { + static u8 swpe; + + bit =3D BIT(swpe); + /* + * SWPE has 16 bits; the bit position is rotated on each trigger + * and wraps around once all bits have been used. + */ + if (++swpe >=3D ICU_SWPE_NUM) + swpe =3D 0; + + offset =3D priv->base + ICU_SWPE; + break; + } + default: + return irq_chip_set_parent_state(d, which, state); + } + guard(raw_spinlock)(&priv->lock); - /* Trigger the software interrupt */ - writel_relaxed(bit, priv->base + ICU_SWINT); + /* Trigger the error/software interrupt */ + writel_relaxed(bit, offset); + return 0; } =20 @@ -480,6 +523,10 @@ static int rzv2h_icu_set_type(struct irq_data *d, unsi= gned int type) gic_type =3D IRQ_TYPE_EDGE_RISING; ret =3D 0; break; + case ICU_ERR_INT_START ... ICU_ERR_INT_LAST: + /* Error Interrupts */ + ret =3D 0; + break; default: ret =3D -EINVAL; } @@ -605,6 +652,48 @@ static int rzv2h_icu_parse_interrupts(struct rzv2h_icu= _priv *priv, struct device return 0; } =20 +static irqreturn_t rzv2h_icu_error_irq(int irq, void *data) +{ + struct rzv2h_icu_priv *priv =3D data; + const struct rzv2h_hw_info *hw_info =3D priv->info; + void __iomem *base =3D priv->base; + unsigned int k; + u32 st; + + /* 1) Bus errors (BEISR0..3) */ + for (k =3D 0; k < ICU_NUM_BE; k++) { + st =3D readl(base + ICU_BEISR(k)); + if (!st) + continue; + + writel_relaxed(st, base + ICU_BECLR(k)); + pr_info("rzv2h-icu: BUS error k=3D%u status=3D0x%08x\n", k, st); + } + + /* 2) ECC RAM errors (EREISR0..X) */ + for (k =3D hw_info->ecc_start; k <=3D hw_info->ecc_end; k++) { + st =3D readl(base + ICU_EREISR(k)); + if (!st) + continue; + + writel_relaxed(st, base + ICU_ERCLR(k)); + pr_info("rzv2h-icu: ECC error k=3D%u status=3D0x%08x\n", k, st); + } + + /* 3) IP/CA55 error interrupt status (ERINTA55CTL0..3) */ + for (k =3D 0; k < ICU_NUM_A55ERR; k++) { + st =3D readl(base + ICU_ERINTA55CTL(k)); + if (!st) + continue; + + /* there is no relation with status bits so clear all the interrupts */ + writel_relaxed(0xffffffff, base + ICU_ERINTA55CRL(k)); + pr_info("rzv2h-icu: IP/CA55 error k=3D%u status=3D0x%08x\n", k, st); + } + + return IRQ_HANDLED; +} + static irqreturn_t rzv2h_icu_swint_irq(int irq, void *data) { u8 cpu =3D *(u8 *)data; @@ -616,12 +705,15 @@ static irqreturn_t rzv2h_icu_swint_irq(int irq, void = *data) static int rzv2h_icu_setup_irqs(struct platform_device *pdev, struct irq_domain *irq_domain) { + const struct rzv2h_hw_info *hw_info =3D rzv2h_icu_data->info; bool irq_inject =3D IS_ENABLED(CONFIG_GENERIC_IRQ_INJECTION); static const char * const rzv2h_swint_names[] =3D { "int-ca55-0", "int-ca55-1", "int-ca55-2", "int-ca55-3", }; + static const char *icu_err =3D "icu-error-ca55"; static const u8 swint_idx[] =3D { 0, 1, 2, 3 }; + void __iomem *base =3D rzv2h_icu_data->base; struct device *dev =3D &pdev->dev; struct irq_fwspec fwspec; unsigned int virq; @@ -646,6 +738,34 @@ static int rzv2h_icu_setup_irqs(struct platform_device= *pdev, rzv2h_swint_names[i]); } =20 + /* Unmask and clear all IP/CA55 error interrupts */ + for (i =3D 0; i < ICU_NUM_A55ERR; i++) { + writel_relaxed(0xffffff, base + ICU_ERINTA55CRL(i)); + writel_relaxed(0x0, base + ICU_ERINTA55MSK(i)); + } + + /* Clear all Bus errors */ + for (i =3D 0; i < ICU_NUM_BE; i++) + writel_relaxed(0xffffffff, base + ICU_BECLR(i)); + + /* Clear all ECCRAM errors */ + for (i =3D hw_info->ecc_start; i <=3D hw_info->ecc_end; i++) + writel_relaxed(0xffffffff, base + ICU_ERCLR(i)); + + fwspec.fwnode =3D irq_domain->fwnode; + fwspec.param_count =3D 2; + fwspec.param[0] =3D ICU_ERR_INT_START; + fwspec.param[1] =3D IRQ_TYPE_LEVEL_HIGH; + + virq =3D irq_create_fwspec_mapping(&fwspec); + if (!virq) + return dev_err_probe(dev, -EINVAL, "failed to create IRQ mapping for %s\= n", + icu_err); + + ret =3D devm_request_irq(dev, virq, rzv2h_icu_error_irq, 0, dev_name(dev)= , rzv2h_icu_data); + if (ret) + return dev_err_probe(dev, ret, "Failed to request %s IRQ\n", icu_err); + return 0; } =20 @@ -751,12 +871,24 @@ static const struct rzv2h_hw_info rzg3e_hw_params =3D= { .t_offs =3D ICU_RZG3E_TINT_OFFSET, .max_tssel =3D ICU_RZG3E_TSSEL_MAX_VAL, .field_width =3D 16, + .ecc_start =3D 1, + .ecc_end =3D 4, +}; + +static const struct rzv2h_hw_info rzv2n_hw_params =3D { + .t_offs =3D 0, + .max_tssel =3D ICU_RZV2H_TSSEL_MAX_VAL, + .field_width =3D 8, + .ecc_start =3D 0, + .ecc_end =3D 2, }; =20 static const struct rzv2h_hw_info rzv2h_hw_params =3D { .t_offs =3D 0, .max_tssel =3D ICU_RZV2H_TSSEL_MAX_VAL, .field_width =3D 8, + .ecc_start =3D 0, + .ecc_end =3D 11, }; =20 static int rzg3e_icu_probe(struct platform_device *pdev, struct device_nod= e *parent) @@ -764,6 +896,11 @@ static int rzg3e_icu_probe(struct platform_device *pde= v, struct device_node *par return rzv2h_icu_probe_common(pdev, parent, &rzg3e_hw_params); } =20 +static int rzv2n_icu_probe(struct platform_device *pdev, struct device_nod= e *parent) +{ + return rzv2h_icu_probe_common(pdev, parent, &rzv2n_hw_params); +} + static int rzv2h_icu_probe(struct platform_device *pdev, struct device_nod= e *parent) { return rzv2h_icu_probe_common(pdev, parent, &rzv2h_hw_params); @@ -771,7 +908,7 @@ static int rzv2h_icu_probe(struct platform_device *pdev= , struct device_node *par =20 IRQCHIP_PLATFORM_DRIVER_BEGIN(rzv2h_icu) IRQCHIP_MATCH("renesas,r9a09g047-icu", rzg3e_icu_probe) -IRQCHIP_MATCH("renesas,r9a09g056-icu", rzv2h_icu_probe) +IRQCHIP_MATCH("renesas,r9a09g056-icu", rzv2n_icu_probe) IRQCHIP_MATCH("renesas,r9a09g057-icu", rzv2h_icu_probe) IRQCHIP_PLATFORM_DRIVER_END(rzv2h_icu) MODULE_AUTHOR("Fabrizio Castro "); --=20 2.52.0