From nobody Tue Feb 10 14:25:58 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 598F132548D; Mon, 9 Feb 2026 07:26:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770621999; cv=none; b=MNCGC4VXgGjJF0WUMLL+EDz0CtwIBFRJFD5ElwF8iAIc4/Jm/KztrSYj/DgvbDOhGMDjVYsSuqPJWCOV3Ib1STS6IbwJB3z1DPkOyEHr0lHCtIqpOpUhcm0rHArOng9P1w5s8XjsenRuciwz8Lu5BLV2bDz1OdrUOJsN5MQEEvI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770621999; c=relaxed/simple; bh=1EMx7jB3je0G2luX3xOuQcangUI11/tq1DJdXAx7rMs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=oiyoKN9N2fL32TkFq9e33gLZoxTJUjtgM/Ir8qMeeZ/5hrYiI/zPJzni5JYjUGNB7KBN0REbhXPtA9XvAEpefMRvl8H2Oi08vOr5Tf+sAHL3sWsDZPcx8l7Ms0IoMX2QMMramXPoAvYzfLsxAh4H/5f95/RKjhzOPEtLKT385mc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Zi33P8E+; arc=none smtp.client-ip=192.198.163.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Zi33P8E+" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1770622000; x=1802158000; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1EMx7jB3je0G2luX3xOuQcangUI11/tq1DJdXAx7rMs=; b=Zi33P8E+Xt/g2l/ch8J0ui7GBga4PpgNVMIlYVnAAAwSrqBUeB5RGZdR AUH/PBVkUpzPmyt6OylvuL19pASsAWst6JWUa5g6twcFDAW2/qzUggMtL R5dqrwASXu7nsQWyUDxqVtUyqSXqPxwNdCAIIOzufHclDQbQ0CCwUe9U6 IN+tANbQHwaYgKsfLHv1XGokl+qjHL5C4VT0SS/Yf8yV1+ifS4xbmRy4T sszfG+XkoDkwOq3j42AMvEpr41u1TLEtg4OrPKMAaUlgH6WtYdLAFDxsp llfT6ZmJMXLrOjt6aDn6Tg7cARkVXCjtp44n+BtlRKwpnGJfRo6lSE2tg Q==; X-CSE-ConnectionGUID: vyd85wgkS8m+hDBc2tZrkA== X-CSE-MsgGUID: e8u89hcpSTausZGCcjCe9g== X-IronPort-AV: E=McAfee;i="6800,10657,11695"; a="83098582" X-IronPort-AV: E=Sophos;i="6.21,281,1763452800"; d="scan'208";a="83098582" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Feb 2026 23:26:39 -0800 X-CSE-ConnectionGUID: CBFdeYpYRRqAYvHMcZsqkA== X-CSE-MsgGUID: uDN6NfYISdulv1eDD6Apeg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,281,1763452800"; d="scan'208";a="241694829" Received: from spr.sh.intel.com ([10.112.229.196]) by fmviesa001.fm.intel.com with ESMTP; 08 Feb 2026 23:26:34 -0800 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Thomas Gleixner , Dave Hansen , Ian Rogers , Adrian Hunter , Jiri Olsa , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: Mark Rutland , broonie@kernel.org, Ravi Bangoria , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Zide Chen , Falcon Thomas , Dapeng Mi , Xudong Hao , Dapeng Mi Subject: [Patch v6 22/22] perf/x86: Activate back-to-back NMI detection for arch-PEBS induced NMIs Date: Mon, 9 Feb 2026 15:20:47 +0800 Message-Id: <20260209072047.2180332-23-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260209072047.2180332-1-dapeng1.mi@linux.intel.com> References: <20260209072047.2180332-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When two or more identical PEBS events with the same sampling period are programmed on a mix of PDIST and non-PDIST counters, multiple back-to-back NMIs can be triggered. The Linux PMI handler processes the first NMI and clears the GLOBAL_STATUS MSR. If a second NMI is triggered immediately after the first, it is recognized as a "suspicious NMI" because no bits are set in the GLOBAL_STATUS MSR (cleared by the first NMI). This issue does not lead to PEBS data corruption or data loss, but it does result in an annoying warning message. The current NMI handler supports back-to-back NMI detection, but it requires the PMI handler to return the count of actually processed events, which the PEBS handler does not currently do. This patch modifies the PEBS handlers to return the count of actually processed events, thereby activating back-to-back NMI detection and avoiding the "suspicious NMI" warning. Suggested-by: Andi Kleen Signed-off-by: Dapeng Mi --- V6: Enhance b2b NMI detection for all PEBS handlers to ensure identical behaviors of all PEBS handlers arch/x86/events/intel/core.c | 6 ++---- arch/x86/events/intel/ds.c | 40 ++++++++++++++++++++++++------------ arch/x86/events/perf_event.h | 2 +- 3 files changed, 30 insertions(+), 18 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index c57a70798364..387205c5d5b5 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -3558,9 +3558,8 @@ static int handle_pmi_common(struct pt_regs *regs, u6= 4 status) if (__test_and_clear_bit(GLOBAL_STATUS_BUFFER_OVF_BIT, (unsigned long *)&= status)) { u64 pebs_enabled =3D cpuc->pebs_enabled; =20 - handled++; x86_pmu_handle_guest_pebs(regs, &data); - static_call(x86_pmu_drain_pebs)(regs, &data); + handled +=3D static_call(x86_pmu_drain_pebs)(regs, &data); =20 /* * PMI throttle may be triggered, which stops the PEBS event. @@ -3589,8 +3588,7 @@ static int handle_pmi_common(struct pt_regs *regs, u6= 4 status) */ if (__test_and_clear_bit(GLOBAL_STATUS_ARCH_PEBS_THRESHOLD_BIT, (unsigned long *)&status)) { - handled++; - static_call(x86_pmu_drain_pebs)(regs, &data); + handled +=3D static_call(x86_pmu_drain_pebs)(regs, &data); =20 if (cpuc->events[INTEL_PMC_IDX_FIXED_SLOTS] && is_pebs_counter_event_group(cpuc->events[INTEL_PMC_IDX_FIXED_SLOTS])) diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c index 2851622fbf0f..94ada08360f1 100644 --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -3029,7 +3029,7 @@ __intel_pmu_pebs_events(struct perf_event *event, __intel_pmu_pebs_last_event(event, iregs, regs, data, at, count, setup_sa= mple); } =20 -static void intel_pmu_drain_pebs_core(struct pt_regs *iregs, struct perf_s= ample_data *data) +static int intel_pmu_drain_pebs_core(struct pt_regs *iregs, struct perf_sa= mple_data *data) { struct cpu_hw_events *cpuc =3D this_cpu_ptr(&cpu_hw_events); struct debug_store *ds =3D cpuc->ds; @@ -3038,7 +3038,7 @@ static void intel_pmu_drain_pebs_core(struct pt_regs = *iregs, struct perf_sample_ int n; =20 if (!x86_pmu.pebs_active) - return; + return 0; =20 at =3D (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base; top =3D (struct pebs_record_core *)(unsigned long)ds->pebs_index; @@ -3049,22 +3049,24 @@ static void intel_pmu_drain_pebs_core(struct pt_reg= s *iregs, struct perf_sample_ ds->pebs_index =3D ds->pebs_buffer_base; =20 if (!test_bit(0, cpuc->active_mask)) - return; + return 0; =20 WARN_ON_ONCE(!event); =20 if (!event->attr.precise_ip) - return; + return 0; =20 n =3D top - at; if (n <=3D 0) { if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD) intel_pmu_save_and_restart_reload(event, 0); - return; + return 0; } =20 __intel_pmu_pebs_events(event, iregs, data, at, top, 0, n, setup_pebs_fixed_sample_data); + + return 1; /* PMC0 only*/ } =20 static void intel_pmu_pebs_event_update_no_drain(struct cpu_hw_events *cpu= c, u64 mask) @@ -3087,7 +3089,7 @@ static void intel_pmu_pebs_event_update_no_drain(stru= ct cpu_hw_events *cpuc, u64 } } =20 -static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs, struct perf_sa= mple_data *data) +static int intel_pmu_drain_pebs_nhm(struct pt_regs *iregs, struct perf_sam= ple_data *data) { struct cpu_hw_events *cpuc =3D this_cpu_ptr(&cpu_hw_events); struct debug_store *ds =3D cpuc->ds; @@ -3096,11 +3098,12 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs= *iregs, struct perf_sample_d short counts[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] =3D {}; short error[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] =3D {}; int max_pebs_events =3D intel_pmu_max_num_pebs(NULL); + u64 events_bitmap =3D 0; int bit, i, size; u64 mask; =20 if (!x86_pmu.pebs_active) - return; + return 0; =20 base =3D (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base; top =3D (struct pebs_record_nhm *)(unsigned long)ds->pebs_index; @@ -3116,7 +3119,7 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs *= iregs, struct perf_sample_d =20 if (unlikely(base >=3D top)) { intel_pmu_pebs_event_update_no_drain(cpuc, mask); - return; + return 0; } =20 for (at =3D base; at < top; at +=3D x86_pmu.pebs_record_size) { @@ -3180,6 +3183,7 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs *= iregs, struct perf_sample_d if ((counts[bit] =3D=3D 0) && (error[bit] =3D=3D 0)) continue; =20 + events_bitmap |=3D bit; event =3D cpuc->events[bit]; if (WARN_ON_ONCE(!event)) continue; @@ -3201,6 +3205,8 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs *= iregs, struct perf_sample_d setup_pebs_fixed_sample_data); } } + + return hweight64(events_bitmap); } =20 static __always_inline void @@ -3256,7 +3262,7 @@ __intel_pmu_handle_last_pebs_record(struct pt_regs *i= regs, =20 DEFINE_PER_CPU(struct x86_perf_regs, pebs_perf_regs); =20 -static void intel_pmu_drain_pebs_icl(struct pt_regs *iregs, struct perf_sa= mple_data *data) +static int intel_pmu_drain_pebs_icl(struct pt_regs *iregs, struct perf_sam= ple_data *data) { short counts[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] =3D {}; void *last[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS]; @@ -3266,10 +3272,11 @@ static void intel_pmu_drain_pebs_icl(struct pt_regs= *iregs, struct perf_sample_d struct pt_regs *regs =3D &perf_regs->regs; struct pebs_basic *basic; void *base, *at, *top; + u64 events_bitmap =3D 0; u64 mask; =20 if (!x86_pmu.pebs_active) - return; + return 0; =20 base =3D (struct pebs_basic *)(unsigned long)ds->pebs_buffer_base; top =3D (struct pebs_basic *)(unsigned long)ds->pebs_index; @@ -3282,7 +3289,7 @@ static void intel_pmu_drain_pebs_icl(struct pt_regs *= iregs, struct perf_sample_d =20 if (unlikely(base >=3D top)) { intel_pmu_pebs_event_update_no_drain(cpuc, mask); - return; + return 0; } =20 if (!iregs) @@ -3297,6 +3304,7 @@ static void intel_pmu_drain_pebs_icl(struct pt_regs *= iregs, struct perf_sample_d continue; =20 pebs_status =3D mask & basic->applicable_counters; + events_bitmap |=3D pebs_status; __intel_pmu_handle_pebs_record(iregs, regs, data, at, pebs_status, counts, last, setup_pebs_adaptive_sample_data); @@ -3304,9 +3312,11 @@ static void intel_pmu_drain_pebs_icl(struct pt_regs = *iregs, struct perf_sample_d =20 __intel_pmu_handle_last_pebs_record(iregs, regs, data, mask, counts, last, setup_pebs_adaptive_sample_data); + + return hweight64(events_bitmap); } =20 -static void intel_pmu_drain_arch_pebs(struct pt_regs *iregs, +static int intel_pmu_drain_arch_pebs(struct pt_regs *iregs, struct perf_sample_data *data) { short counts[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] =3D {}; @@ -3316,13 +3326,14 @@ static void intel_pmu_drain_arch_pebs(struct pt_reg= s *iregs, struct x86_perf_regs *perf_regs =3D this_cpu_ptr(&pebs_perf_regs); struct pt_regs *regs =3D &perf_regs->regs; void *base, *at, *top; + u64 events_bitmap =3D 0; u64 mask; =20 rdmsrq(MSR_IA32_PEBS_INDEX, index.whole); =20 if (unlikely(!index.wr)) { intel_pmu_pebs_event_update_no_drain(cpuc, X86_PMC_IDX_MAX); - return; + return 0; } =20 base =3D cpuc->pebs_vaddr; @@ -3361,6 +3372,7 @@ static void intel_pmu_drain_arch_pebs(struct pt_regs = *iregs, =20 basic =3D at + sizeof(struct arch_pebs_header); pebs_status =3D mask & basic->applicable_counters; + events_bitmap |=3D pebs_status; __intel_pmu_handle_pebs_record(iregs, regs, data, at, pebs_status, counts, last, setup_arch_pebs_sample_data); @@ -3380,6 +3392,8 @@ static void intel_pmu_drain_arch_pebs(struct pt_regs = *iregs, __intel_pmu_handle_last_pebs_record(iregs, regs, data, mask, counts, last, setup_arch_pebs_sample_data); + + return hweight64(events_bitmap); } =20 static void __init intel_arch_pebs_init(void) diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index fdfb34d7b1d2..0083334f2d33 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -1014,7 +1014,7 @@ struct x86_pmu { int pebs_record_size; int pebs_buffer_size; u64 pebs_events_mask; - void (*drain_pebs)(struct pt_regs *regs, struct perf_sample_data *data); + int (*drain_pebs)(struct pt_regs *regs, struct perf_sample_data *data); struct event_constraint *pebs_constraints; void (*pebs_aliases)(struct perf_event *event); u64 (*pebs_latency_data)(struct perf_event *event, u64 status); --=20 2.34.1