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Signed-off-by: Gatien Chevallier --- .../bindings/soc/st/st,stm32mp25-risab.yaml | 74 ++++++++++++++++++= ++++ MAINTAINERS | 5 ++ 2 files changed, 79 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/st/st,stm32mp25-risab.ya= ml b/Documentation/devicetree/bindings/soc/st/st,stm32mp25-risab.yaml new file mode 100644 index 000000000000..d05a683c594d --- /dev/null +++ b/Documentation/devicetree/bindings/soc/st/st,stm32mp25-risab.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/st/st,stm32mp25-risab.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STM32 Resource isolation peripheral unit for address space protecti= on + (block-based) + +maintainers: + - Gatien Chevallier + +description: + The RIF (resource isolation framework) is a comprehensive set of hardware + blocks designed to enforce and manage isolation of STM32 hardware resour= ces, + like memory and peripherals. The RISAB peripheral is part of the RIF and= is + used to protect internal RAMs by applying access rights per RISAB fixed-= size + page. Through RISAB registers, a trusted domain, or the domain to whom t= he + page configuration has been delegated, assigns memory pages to one or mo= re + security domains (secure, privilege, compartment). + +properties: + compatible: + const: st,stm32mp25-risab + + reg: + maxItems: 1 + + clocks: + items: + - description: RISAB bus clock + + memory-region: + minItems: 1 + maxItems: 32 + description: + Phandle to nodes describing memory regions to be configured in the R= ISAB + by the trusted domain of at least a RISAB page size. + These regions cannot overlap. A zone must be within st,mem-map range= and + can be represented by one or more pages. + + st,mem-map: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: Memory address range covered by the RISAB. + items: + - description: Memory range base address + - description: Memory range size + + st,srwiad: + description: + When set, the trusted domain configures the RISAB to allow secure + read/write data accesses to non-secure blocks and pages. Secure exec= ute + remains illegal. + type: boolean + +required: + - compatible + - reg + - clocks + - st,mem-map + +additionalProperties: false + +examples: + - | + #include + + risab1: risab@420f0000 { + compatible =3D "st,stm32mp25-risab"; + reg =3D <0x420f0000 0x1000>; + clocks =3D <&rcc CK_ICN_LS_MCU>; + st,mem-map =3D <0xa000000 0x20000>; + st,srwiad; + }; diff --git a/MAINTAINERS b/MAINTAINERS index e08767323763..b9a1276e94a9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -25092,6 +25092,11 @@ F: Documentation/arch/arm/stm32/stm32-dma-mdma-cha= ining.rst F: Documentation/devicetree/bindings/dma/stm32/ F: drivers/dma/stm32/ =20 +STM32 SoC FIREWALL DRIVERS +M: Gatien Chevallier +S: Maintained +F: Documentation/devicetree/bindings/soc/st/*risa* + STM32 TIMER/LPTIMER DRIVERS M: Fabrice Gasnier S: Maintained --=20 2.43.0