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Mon, 09 Feb 2026 01:45:38 -0800 (PST) Received: from [169.254.0.6] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82441884b75sm10748666b3a.39.2026.02.09.01.45.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Feb 2026 01:45:37 -0800 (PST) From: Raviteja Laggyshetty Date: Mon, 09 Feb 2026 09:44:29 +0000 Subject: [PATCH v3 2/2] interconnect: qcom: glymur: Add Mahua SoC support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260209-mahua_icc-v3-2-c65f3dfd72c8@oss.qualcomm.com> References: <20260209-mahua_icc-v3-0-c65f3dfd72c8@oss.qualcomm.com> In-Reply-To: <20260209-mahua_icc-v3-0-c65f3dfd72c8@oss.qualcomm.com> To: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Raviteja Laggyshetty , Odelu Kukatla Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov , Konrad Dybcio X-Mailer: b4 0.14.2 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjA5MDA4MCBTYWx0ZWRfX01kXJQ9XY49H pbqqmM7R210eD9f+UzsJfG2mtq0788w74ifyuion7XgIbKkOFdB+Qd0Cwl+oc9TEjo/OFXOEFaH FjiqnyFMnUKnLJYmwB7xlBwyEBZf9V8AN8cCobyJlotAFzQa3y1Owx8FzgId5SQ4yjbi2QrVetQ SG2/eVj1HY9N2v808VxAKT7fMzuadA8/91tl4Lk4xUMLFW2O6MVgznwq78Zkc6jp53Z+NyzSPUc mLH+sE2G8npRFb+A9pYs/sCE9winvVAKwQBYFlOLc5jnRWjgIallS58xhVIb+UraWX8hwnLlFZv lZZF0Cn1LtPz0OKMrmCdVMcRprnXeYEjIVvrhEGTp/QKERmNH0YksuI8QjYJb/4ctC6KRdGy4M0 WoPLhJsEFO2YMYkiOZnHt3GgC2/D+SN5vmgndNCeiC0YS/jx9O1qVzdIDuKDeCVa/BqDZEW5pW9 4/dgtRr24c1n7tbmSxQ== X-Authority-Analysis: v=2.4 cv=Fv0IPmrq c=1 sm=1 tr=0 ts=6989acc3 cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=EUspDBNiAAAA:8 a=niA-Db4sJa1Ec6H3ubUA:9 a=QEXdDO2ut3YA:10 a=x9snwWr2DeNwDh03kgHS:22 X-Proofpoint-ORIG-GUID: XOyzqUjRbA1k7FdDvzgdQzG25WShmQe- X-Proofpoint-GUID: XOyzqUjRbA1k7FdDvzgdQzG25WShmQe- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-08_05,2026-02-09_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 lowpriorityscore=0 adultscore=0 suspectscore=0 spamscore=0 phishscore=0 bulkscore=0 priorityscore=1501 clxscore=1015 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602090080 Mahua is a derivative of the Glymur SoC. Extend the Glymur driver to support Mahua by: 1. Adding new node definitions for interconnects that differ from Glymur (Config NoC, High-Speed Coherent NoC, PCIe West ANOC/Slave NoC). 2. Reusing existing Glymur definitions for identical NoCs. 3. Overriding the channel and buswidth, with Mahua specific values for the differing NoCs Co-developed-by: Odelu Kukatla Signed-off-by: Odelu Kukatla Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Raviteja Laggyshetty --- drivers/interconnect/qcom/glymur.c | 38 +++++++++++++++++++++++++++++++++-= ---- 1 file changed, 33 insertions(+), 5 deletions(-) diff --git a/drivers/interconnect/qcom/glymur.c b/drivers/interconnect/qcom= /glymur.c index e5c07795a6c67ab8a59daf2fc4b8a5fa6dd014d6..cfe061c1a75a692c252c4a0d4ea= 63e71308223ba 100644 --- a/drivers/interconnect/qcom/glymur.c +++ b/drivers/interconnect/qcom/glymur.c @@ -9,6 +9,7 @@ #include #include #include +#include #include =20 #include "bcm-voter.h" @@ -1985,7 +1986,7 @@ static struct qcom_icc_bcm * const cnoc_cfg_bcms[] = =3D { &bcm_cn1, }; =20 -static struct qcom_icc_node * const cnoc_cfg_nodes[] =3D { +static struct qcom_icc_node *cnoc_cfg_nodes[] =3D { [MASTER_CNOC_CFG] =3D &qsm_cfg, [SLAVE_AHB2PHY_SOUTH] =3D &qhs_ahb2phy0, [SLAVE_AHB2PHY_NORTH] =3D &qhs_ahb2phy1, @@ -2093,7 +2094,7 @@ static struct qcom_icc_bcm * const hscnoc_bcms[] =3D { &bcm_sh1, }; =20 -static struct qcom_icc_node * const hscnoc_nodes[] =3D { +static struct qcom_icc_node *hscnoc_nodes[] =3D { [MASTER_GPU_TCU] =3D &alm_gpu_tcu, [MASTER_PCIE_TCU] =3D &alm_pcie_qtc, [MASTER_SYS_TCU] =3D &alm_sys_tcu, @@ -2377,7 +2378,7 @@ static struct qcom_icc_bcm * const pcie_west_anoc_bcm= s[] =3D { &bcm_sn6, }; =20 -static struct qcom_icc_node * const pcie_west_anoc_nodes[] =3D { +static struct qcom_icc_node *pcie_west_anoc_nodes[] =3D { [MASTER_PCIE_WEST_ANOC_CFG] =3D &qsm_pcie_west_anoc_cfg, [MASTER_PCIE_2] =3D &xm_pcie_2, [MASTER_PCIE_3A] =3D &xm_pcie_3a, @@ -2409,7 +2410,7 @@ static struct qcom_icc_bcm * const pcie_west_slv_noc_= bcms[] =3D { &bcm_sn6, }; =20 -static struct qcom_icc_node * const pcie_west_slv_noc_nodes[] =3D { +static struct qcom_icc_node *pcie_west_slv_noc_nodes[] =3D { [MASTER_HSCNOC_PCIE_WEST] =3D &qnm_hscnoc_pcie_west, [MASTER_CNOC_PCIE_WEST_SLAVE_CFG] =3D &qsm_cnoc_pcie_west_slave_cfg, [SLAVE_HSCNOC_PCIE_WEST_MS_MPU_CFG] =3D &qhs_hscnoc_pcie_west_ms_mpu_cfg, @@ -2470,6 +2471,28 @@ static const struct qcom_icc_desc glymur_system_noc = =3D { .num_bcms =3D ARRAY_SIZE(system_noc_bcms), }; =20 +static int glymur_qnoc_probe(struct platform_device *pdev) +{ + if (device_is_compatible(&pdev->dev, "qcom,mahua-mc-virt")) { + llcc_mc.channels =3D 8; + ebi.channels =3D 8; + } else if (device_is_compatible(&pdev->dev, "qcom,mahua-hscnoc")) { + qns_llcc.channels =3D 8; + chm_apps.channels =3D 4; + qnm_pcie_west.buswidth =3D 32; + hscnoc_nodes[MASTER_WLAN_Q6] =3D NULL; + } else if (device_is_compatible(&pdev->dev, "qcom,mahua-pcie-west-anoc"))= { + qns_pcie_west_mem_noc.buswidth =3D 32; + pcie_west_anoc_nodes[MASTER_PCIE_3A] =3D NULL; + } else if (device_is_compatible(&pdev->dev, "qcom,mahua-cnoc-cfg")) { + cnoc_cfg_nodes[SLAVE_PCIE_3A_CFG] =3D NULL; + } else if (device_is_compatible(&pdev->dev, "qcom,mahua-pcie-west-slv-noc= ")) { + pcie_west_slv_noc_nodes[SLAVE_PCIE_3A] =3D NULL; + } + + return qcom_icc_rpmh_probe(pdev); +} + static const struct of_device_id qnoc_of_match[] =3D { { .compatible =3D "qcom,glymur-aggre1-noc", .data =3D &glymur_aggre1_noc}, { .compatible =3D "qcom,glymur-aggre2-noc", .data =3D &glymur_aggre2_noc}, @@ -2477,12 +2500,15 @@ static const struct of_device_id qnoc_of_match[] = =3D { { .compatible =3D "qcom,glymur-aggre4-noc", .data =3D &glymur_aggre4_noc}, { .compatible =3D "qcom,glymur-clk-virt", .data =3D &glymur_clk_virt}, { .compatible =3D "qcom,glymur-cnoc-cfg", .data =3D &glymur_cnoc_cfg}, + { .compatible =3D "qcom,mahua-cnoc-cfg", .data =3D &glymur_cnoc_cfg}, { .compatible =3D "qcom,glymur-cnoc-main", .data =3D &glymur_cnoc_main}, { .compatible =3D "qcom,glymur-hscnoc", .data =3D &glymur_hscnoc}, + { .compatible =3D "qcom,mahua-hscnoc", .data =3D &glymur_hscnoc}, { .compatible =3D "qcom,glymur-lpass-ag-noc", .data =3D &glymur_lpass_ag_= noc}, { .compatible =3D "qcom,glymur-lpass-lpiaon-noc", .data =3D &glymur_lpass= _lpiaon_noc}, { .compatible =3D "qcom,glymur-lpass-lpicx-noc", .data =3D &glymur_lpass_= lpicx_noc}, { .compatible =3D "qcom,glymur-mc-virt", .data =3D &glymur_mc_virt}, + { .compatible =3D "qcom,mahua-mc-virt", .data =3D &glymur_mc_virt}, { .compatible =3D "qcom,glymur-mmss-noc", .data =3D &glymur_mmss_noc}, { .compatible =3D "qcom,glymur-nsinoc", .data =3D &glymur_nsinoc}, { .compatible =3D "qcom,glymur-nsp-noc", .data =3D &glymur_nsp_noc}, @@ -2490,14 +2516,16 @@ static const struct of_device_id qnoc_of_match[] = =3D { { .compatible =3D "qcom,glymur-pcie-east-anoc", .data =3D &glymur_pcie_ea= st_anoc}, { .compatible =3D "qcom,glymur-pcie-east-slv-noc", .data =3D &glymur_pcie= _east_slv_noc}, { .compatible =3D "qcom,glymur-pcie-west-anoc", .data =3D &glymur_pcie_we= st_anoc}, + { .compatible =3D "qcom,mahua-pcie-west-anoc", .data =3D &glymur_pcie_wes= t_anoc}, { .compatible =3D "qcom,glymur-pcie-west-slv-noc", .data =3D &glymur_pcie= _west_slv_noc}, + { .compatible =3D "qcom,mahua-pcie-west-slv-noc", .data =3D &glymur_pcie_= west_slv_noc}, { .compatible =3D "qcom,glymur-system-noc", .data =3D &glymur_system_noc}, { } }; MODULE_DEVICE_TABLE(of, qnoc_of_match); =20 static struct platform_driver qnoc_driver =3D { - .probe =3D qcom_icc_rpmh_probe, + .probe =3D glymur_qnoc_probe, .remove =3D qcom_icc_rpmh_remove, .driver =3D { .name =3D "qnoc-glymur", --=20 2.43.0