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Mon, 09 Feb 2026 01:45:33 -0800 (PST) Received: from [169.254.0.6] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82441884b75sm10748666b3a.39.2026.02.09.01.45.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Feb 2026 01:45:33 -0800 (PST) From: Raviteja Laggyshetty Date: Mon, 09 Feb 2026 09:44:28 +0000 Subject: [PATCH v3 1/2] dt-bindings: interconnect: document the RPMh Network-On-Chip interconnect in Mahua SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260209-mahua_icc-v3-1-c65f3dfd72c8@oss.qualcomm.com> References: <20260209-mahua_icc-v3-0-c65f3dfd72c8@oss.qualcomm.com> In-Reply-To: <20260209-mahua_icc-v3-0-c65f3dfd72c8@oss.qualcomm.com> To: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Raviteja Laggyshetty , Odelu Kukatla Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.2 X-Proofpoint-GUID: oaPK0c-FfjY9sNG8iquepKrAkmS6OHZa X-Authority-Analysis: v=2.4 cv=AJ+v8NAg c=1 sm=1 tr=0 ts=6989acbf cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=XbHj8r4lGLmVoAHgLPwA:9 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjA5MDA4MCBTYWx0ZWRfXyNJ0aEYbCCsl rlmm901dVXhyCOe/EBsTEZ7Xn7+dBrjRuMi1soRfjzSx/7+LGyIxW64jD39WUDoIJsIKGdDQblx NdXz+imPc6uLVCzXjLogs1AUbGtqHKBB7l2Lye4NXn23yylEtkah0lv7SWzqTQIc1fKLwcrmYWl PNaX0VOhTq3wfG/U+YFQY5FJqbNI/c8dkdejPbD1R/JE3B2CvQwZ90X1Isnq8Noj6yNlp36Rvhe LEEfW2AvJtf4dLJ9FoHOzrmglQ9SReDLrWX6SvXb17z7gzfWNfX4MUVnz+GsYJZxZaa6coaMJPk 880pf/zVAgHiwgTAo1mXumcoenJlteSLnECETTqhYCSBLJ+ThpeQ7q3ClpHQO9kdeQIhYdz/EE4 trt+FfAh5cwRyErCJCUBffOQQOiQZAX9z01RlNQzlSW6pAm8bO/QQ/kInJ2sNCANBp6yxR9CunE sKz6BdJ0Ax0rn7lJrRw== X-Proofpoint-ORIG-GUID: oaPK0c-FfjY9sNG8iquepKrAkmS6OHZa X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-08_05,2026-02-09_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 priorityscore=1501 spamscore=0 bulkscore=0 suspectscore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 adultscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602090080 Document the RPMh Network-on-Chip (NoC) interconnect for the Qualcomm Mahua platform. Mahua is a derivative of the Glymur SoC. Many interconnect nodes are identical and continue to use Glymur fallback compatibles. Mahua introduces SoC-specific configurations and topologies for several NoC blocks, including CNOC, HSCNOC, PCIe West ANoC/Slave NoCs. This updates the existing Glymur yaml schema to include Mahua-specific compatible strings, using two-cell "fallback" compatibles wherever the hardware is identical with Glymur. Co-developed-by: Odelu Kukatla Signed-off-by: Odelu Kukatla Acked-by: Konrad Dybcio Signed-off-by: Raviteja Laggyshetty Reviewed-by: Krzysztof Kozlowski --- .../bindings/interconnect/qcom,glymur-rpmh.yaml | 136 +++++++++++++++++= ---- 1 file changed, 111 insertions(+), 25 deletions(-) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,glymur-rpm= h.yaml b/Documentation/devicetree/bindings/interconnect/qcom,glymur-rpmh.ya= ml index d55a7bcf5591eea79c173a12b12c659321ca3c2e..f69b2facb658e076bd622f832b3= e2844b6e72c29 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,glymur-rpmh.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,glymur-rpmh.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/interconnect/qcom,glymur-rpmh.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Qualcomm RPMh Network-On-Chip Interconnect on GLYMUR +title: Qualcomm RPMh Network-On-Chip Interconnect on Glymur and Mahua SoCs =20 maintainers: - Raviteja Laggyshetty @@ -21,28 +21,98 @@ description: | =20 properties: compatible: - enum: - - qcom,glymur-aggre1-noc - - qcom,glymur-aggre2-noc - - qcom,glymur-aggre3-noc - - qcom,glymur-aggre4-noc - - qcom,glymur-clk-virt - - qcom,glymur-cnoc-cfg - - qcom,glymur-cnoc-main - - qcom,glymur-hscnoc - - qcom,glymur-lpass-ag-noc - - qcom,glymur-lpass-lpiaon-noc - - qcom,glymur-lpass-lpicx-noc - - qcom,glymur-mc-virt - - qcom,glymur-mmss-noc - - qcom,glymur-nsinoc - - qcom,glymur-nsp-noc - - qcom,glymur-oobm-ss-noc - - qcom,glymur-pcie-east-anoc - - qcom,glymur-pcie-east-slv-noc - - qcom,glymur-pcie-west-anoc - - qcom,glymur-pcie-west-slv-noc - - qcom,glymur-system-noc + oneOf: + - items: + - enum: + - qcom,mahua-aggre1-noc + - const: qcom,glymur-aggre1-noc + - items: + - enum: + - qcom,mahua-aggre2-noc + - const: qcom,glymur-aggre2-noc + - items: + - enum: + - qcom,mahua-aggre3-noc + - const: qcom,glymur-aggre3-noc + - items: + - enum: + - qcom,mahua-aggre4-noc + - const: qcom,glymur-aggre4-noc + - items: + - enum: + - qcom,mahua-clk-virt + - const: qcom,glymur-clk-virt + - items: + - enum: + - qcom,mahua-cnoc-main + - const: qcom,glymur-cnoc-main + - items: + - enum: + - qcom,mahua-lpass-ag-noc + - const: qcom,glymur-lpass-ag-noc + - items: + - enum: + - qcom,mahua-lpass-lpiaon-noc + - const: qcom,glymur-lpass-lpiaon-noc + - items: + - enum: + - qcom,mahua-lpass-lpicx-noc + - const: qcom,glymur-lpass-lpicx-noc + - items: + - enum: + - qcom,mahua-mmss-noc + - const: qcom,glymur-mmss-noc + - items: + - enum: + - qcom,mahua-nsinoc + - const: qcom,glymur-nsinoc + - items: + - enum: + - qcom,mahua-nsp-noc + - const: qcom,glymur-nsp-noc + - items: + - enum: + - qcom,mahua-oobm-ss-noc + - const: qcom,glymur-oobm-ss-noc + - items: + - enum: + - qcom,mahua-pcie-east-anoc + - const: qcom,glymur-pcie-east-anoc + - items: + - enum: + - qcom,mahua-pcie-east-slv-noc + - const: qcom,glymur-pcie-east-slv-noc + - items: + - enum: + - qcom,mahua-system-noc + - const: qcom,glymur-system-noc + - enum: + - qcom,glymur-aggre1-noc + - qcom,glymur-aggre2-noc + - qcom,glymur-aggre3-noc + - qcom,glymur-aggre4-noc + - qcom,glymur-clk-virt + - qcom,glymur-cnoc-cfg + - qcom,glymur-cnoc-main + - qcom,glymur-hscnoc + - qcom,glymur-lpass-ag-noc + - qcom,glymur-lpass-lpiaon-noc + - qcom,glymur-lpass-lpicx-noc + - qcom,glymur-mc-virt + - qcom,glymur-mmss-noc + - qcom,glymur-nsinoc + - qcom,glymur-nsp-noc + - qcom,glymur-oobm-ss-noc + - qcom,glymur-pcie-east-anoc + - qcom,glymur-pcie-east-slv-noc + - qcom,glymur-pcie-west-anoc + - qcom,glymur-pcie-west-slv-noc + - qcom,glymur-system-noc + - qcom,mahua-cnoc-cfg + - qcom,mahua-hscnoc + - qcom,mahua-mc-virt + - qcom,mahua-pcie-west-anoc + - qcom,mahua-pcie-west-slv-noc =20 reg: maxItems: 1 @@ -63,6 +133,7 @@ allOf: enum: - qcom,glymur-clk-virt - qcom,glymur-mc-virt + - qcom,mahua-mc-virt then: properties: reg: false @@ -85,6 +156,20 @@ allOf: - description: aggre PCIE_4 WEST AXI clock - description: aggre PCIE_6 WEST AXI clock =20 + - if: + properties: + compatible: + contains: + enum: + - qcom,mahua-pcie-west-anoc + then: + properties: + clocks: + items: + - description: aggre PCIE_3B WEST AXI clock + - description: aggre PCIE_4 WEST AXI clock + - description: aggre PCIE_6 WEST AXI clock + - if: properties: compatible: @@ -131,10 +216,11 @@ allOf: compatible: contains: enum: - - qcom,glymur-pcie-west-anoc - - qcom,glymur-pcie-east-anoc - qcom,glymur-aggre2-noc - qcom,glymur-aggre4-noc + - qcom,glymur-pcie-east-anoc + - qcom,glymur-pcie-west-anoc + - qcom,mahua-pcie-west-anoc then: required: - clocks --=20 2.43.0