From nobody Tue Feb 10 04:14:00 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BB74A2FE07D; Mon, 9 Feb 2026 05:49:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770616146; cv=none; b=T5VDhg7N+UaOZx7VlI+xk384nnSksKpUJYmxfQ+jx/Yl+iGKcM4rUqk551RIYPfaa7232juUggjvWATysb+rDJXrWsTBUsxTblrucVCJQGQWepz4EDmpfIDbCX6VlKUg4O8wrY//38cVVHtW5PBGVoP/5pJpTF7rSl6cze6JWh4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770616146; c=relaxed/simple; bh=5esYusbyLxWjj8goWtgBSoRxDiOqg8OOeevMtpYWJis=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=DP1vnCuPM7eBFzgcmrk3rDgddIvlZpSlPlO+5IOqpWvj5/gsMMmdSSRqdO8mL2Jx23XfF6YuShF9+zTfAO6mf/OX/+p+NHdsZHsct6wXmDXquf26G0JnvD9siq+MLeeOnHOlP5V7uKMa7PJdHMkAC6/pxbgc/GHccAUdWNeWV58= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=c24DetAn; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="c24DetAn" Received: by smtp.kernel.org (Postfix) with ESMTPS id 7E987C2BCB7; Mon, 9 Feb 2026 05:49:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1770616146; bh=5esYusbyLxWjj8goWtgBSoRxDiOqg8OOeevMtpYWJis=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=c24DetAngfmfCpgS7os9ijGtEEURSzFqwfvz5BjNqsuHCLPViNIb8h+AiZfzVZaP0 iajKNBMe+eTemtmfx5UmlIRY41bsYoqpupzxyR2yg40Opql/p6PGm6kNlPidEfbX7O 1ncC2Fh0TBs9W6QoAc6BZlgRnJnjrs6myB8zQDZPr/lVWb86JxZBOA41AuGY2r7ZX2 qYAaoQQOKI5Czd1nWIegOeuVVQn1gKCTfGDVEYbKFy8R3uFTYOTS0REDZPnmw7XiPa t+3yOiKKNCNTj4JlZ/DXxEcmMqeNqJ4Cv++Q+BNb5DHw7cp1EycHrsiSlQ3TmC/lxQ nGknVngLT0Ueg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6BE7CEF070E; Mon, 9 Feb 2026 05:49:06 +0000 (UTC) From: Chuan Liu via B4 Relay Date: Mon, 09 Feb 2026 13:48:49 +0800 Subject: [PATCH 03/13] dt-bindings: clock: Add Amlogic A9 misc clock control units Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260209-a9_clock_driver-v1-3-a9198dc03d2a@amlogic.com> References: <20260209-a9_clock_driver-v1-0-a9198dc03d2a@amlogic.com> In-Reply-To: <20260209-a9_clock_driver-v1-0-a9198dc03d2a@amlogic.com> To: Neil Armstrong , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Chuan Liu X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1770616142; l=20139; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=7QE3RPkma3R9c3HdHltjAQG+gp4wGavYW1MtDbZrjh8=; b=jiL5zhA5poL2RgVqOpHMUn/gllWBLd8I905vvD+b/w0mlefG8/1pxAkWz6QgMtD28xKJgTgHv RlCfGtQ3nSyALhxxjDPWV2ITEHMS7uQNEKgBjBCOXGskv5mOyIGZr7P X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu Add dt-binding documentation for various miscellaneous peripheral clock control units in A9 SoC family. Signed-off-by: Chuan Liu --- .../bindings/clock/amlogic,a9-misc-ccu.yaml | 523 +++++++++++++++++= ++++ include/dt-bindings/clock/amlogic,a9-misc-ccu.h | 53 +++ 2 files changed, 576 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/amlogic,a9-misc-ccu.ya= ml b/Documentation/devicetree/bindings/clock/amlogic,a9-misc-ccu.yaml new file mode 100644 index 000000000000..cce209f75a6e --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,a9-misc-ccu.yaml @@ -0,0 +1,523 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2026 Amlogic, Inc. All rights reserved +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/amlogic,a9-misc-ccu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic A9 Family Misc Clock Control Unit + +maintainers: + - Chuan Liu + +description: | + The misc-ccu contains clock control units which are built from dedicated, + non-universal model clock controllers, such as the sc-ccu for smart card= and + the ts-ccu for temperature sensor. + + The clock IDs of the subclocks of these CCUs are defined in + "include/dt-bindings/clock/amlogic,a9-misc-ccu.h". + +properties: + compatible: + oneOf: + - items: + - const: amlogic,a9-sc-ccu + description: Clock control unit of smart card + - items: + - const: amlogic,a9-ts-ccu + description: Clock control unit of temperature sensor(s) + - items: + - const: amlogic,a9-genout-ccu + description: Clock control unit that generates clock output to pin= (s) + - items: + - const: amlogic,a9-clk12_24m-ccu + description: Clock control unit that generates clock output 12MHz = or + 24MHz to pin(s) + - items: + - const: amlogic,a9-vapb_ge2d-ccu + description: Clock control unit for vapb and ge2d + - items: + - const: amlogic,a9-di-ccu + description: Clock control unit of de-interlace + - items: + - const: amlogic,a9-eth-ccu + description: Clock control unit of ethernet + - items: + - const: amlogic,a9-mclk-ccu + description: Clock control unit that provides the clock to the ext= ernal + camera sensor + - items: + - const: amlogic,a9-dualdivmux-ccu + description: Clock control unit using dual divider channel togglin= g for + fractional division + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 32 + + clock-names: + minItems: 1 + maxItems: 32 + + clock-output-names: + minItems: 1 + maxItems: 8 + + '#clock-cells': + description: + The clock controller of a module may contain one or more child clock= (s). + When a clock controller has multiple child clocks, an index is requi= red + to specify a particular clock within the clock controller. + oneOf: + - const: 0 + description: Single clock output, no specifier needed + - const: 1 + description: Multiple clocks, index selects specific output + + amlogic,clock-max-frequency: + description: | + Each clock's maximum output frequency is constrained during hardware + design to ensure proper timing requirements for the clock network. I= f the + clock frequency configured exceeds this design limit, it can lead to + abnormal behavior in modules relying on that clock and may even cause + cross-talk that affects other modules. + + In the driver, this property is parsed, and interface functions from= the + CCF are called to enforce the clock's maximum frequency, preventing + potential issues caused by excessive clock frequency configurations. + $ref: /schemas/types.yaml#/definitions/uint32-array + + amlogic,clock-init-regs: + description: + Certain CCUs and PLLs require initialization through dedicated regis= ters + before becoming operational. This initialization configures internal= clock + drive characteristics, divider parameters, and PLL internal circuitr= y. + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + items: + - description: The register offset address + - description: The value to be written to the register + - description: The delay after the register write (unit is us) + +allOf: + - if: + properties: + compatible: + contains: + const: amlogic,a9-sc-ccu + then: + properties: + clocks: + minItems: 1 + items: + - description: input clock source 0 + - description: input clock source 1 (optional) + - description: input clock source 2 (optional) + - description: input clock source 3 (optional) + clock-names: + minItems: 1 + items: + - const: clkin0 + - const: clkin1 + - const: clkin2 + - const: clkin3 + clock-output-names: + + items: + - description: preprocessing clock + - description: divider clock + required: + - clock-names + + - if: + properties: + compatible: + contains: + const: amlogic,a9-ts-ccu + then: + properties: + clocks: + description: input clock of ts-ccu + clock-output-names: + items: + - description: divider clock + - description: gate clock + + - if: + properties: + compatible: + contains: + const: amlogic,a9-genout-ccu + then: + properties: + clocks: + minItems: 1 + items: + - description: input clock source 0 + - description: input clock source 1 (optional) + - description: input clock source 2 (optional) + - description: input clock source 3 (optional) + - description: input clock source 4 (optional) + - description: input clock source 5 (optional) + - description: input clock source 6 (optional) + - description: input clock source 7 (optional) + - description: input clock source 8 (optional) + - description: input clock source 9 (optional) + - description: input clock source 10 (optional) + - description: input clock source 11 (optional) + - description: input clock source 12 (optional) + - description: input clock source 13 (optional) + - description: input clock source 14 (optional) + - description: input clock source 15 (optional) + - description: input clock source 16 (optional) + - description: input clock source 17 (optional) + - description: input clock source 18 (optional) + - description: input clock source 19 (optional) + - description: input clock source 20 (optional) + - description: input clock source 21 (optional) + - description: input clock source 22 (optional) + - description: input clock source 23 (optional) + - description: input clock source 24 (optional) + - description: input clock source 25 (optional) + - description: input clock source 26 (optional) + - description: input clock source 27 (optional) + - description: input clock source 28 (optional) + - description: input clock source 29 (optional) + - description: input clock source 30 (optional) + - description: input clock source 31 (optional) + clock-names: + minItems: 1 + items: + - const: clkin0 + - const: clkin1 + - const: clkin2 + - const: clkin3 + - const: clkin4 + - const: clkin5 + - const: clkin6 + - const: clkin7 + - const: clkin8 + - const: clkin9 + - const: clkin10 + - const: clkin11 + - const: clkin12 + - const: clkin13 + - const: clkin14 + - const: clkin15 + - const: clkin16 + - const: clkin17 + - const: clkin18 + - const: clkin19 + - const: clkin20 + - const: clkin21 + - const: clkin22 + - const: clkin23 + - const: clkin24 + - const: clkin25 + - const: clkin26 + - const: clkin27 + - const: clkin28 + - const: clkin29 + - const: clkin30 + - const: clkin31 + clock-output-names: + items: + - description: multiplexer clock + - description: divider clock + - description: gate clock + required: + - clock-names + + - if: + properties: + compatible: + contains: + const: amlogic,a9-clk12_24m-ccu + then: + properties: + clocks: + maxItems: 1 + description: 24m-xtal clock + clock-output-names: + items: + - description: input gate clock + - description: divider clock + + - if: + properties: + compatible: + contains: + const: amlogic,a9-vapb_ge2d-ccu + then: + properties: + clocks: + minItems: 1 + items: + - description: input clock source 0 + - description: input clock source 1 (optional) + - description: input clock source 2 (optional) + - description: input clock source 3 (optional) + - description: input clock source 4 (optional) + - description: input clock source 5 (optional) + - description: input clock source 6 (optional) + - description: input clock source 7 (optional) + clock-names: + minItems: 1 + items: + - const: clkin0 + - const: clkin1 + - const: clkin2 + - const: clkin3 + - const: clkin4 + - const: clkin5 + - const: clkin6 + - const: clkin7 + clock-output-names: + items: + - description: vapb clock + - description: ge2d clock + required: + - clock-names + + - if: + properties: + compatible: + contains: + const: amlogic,a9-di-ccu + then: + properties: + clocks: + minItems: 1 + items: + - description: input clock source 0 + - description: input clock source 1 (optional) + - description: input clock source 2 (optional) + - description: input clock source 3 (optional) + clock-names: + minItems: 1 + items: + - const: clkin0 + - const: clkin1 + - const: clkin2 + - const: clkin3 + clock-output-names: + items: + - description: preprocessing clock + - description: divider clock + - description: gate clock + required: + - clock-names + + - if: + properties: + compatible: + contains: + const: amlogic,a9-eth-ccu + then: + properties: + clocks: + minItems: 2 + items: + - description: eth_125m input clock + - description: rmii input clock source 0 + - description: rmii input clock source 1 (optional) + - description: rmii input clock source 2 (optional) + - description: rmii input clock source 3 (optional) + - description: rmii input clock source 4 (optional) + - description: rmii input clock source 5 (optional) + - description: rmii input clock source 6 (optional) + - description: rmii input clock source 7 (optional) + clock-names: + minItems: 2 + items: + - const: clk125m + - const: clkin0 + - const: clkin1 + - const: clkin2 + - const: clkin3 + - const: clkin4 + - const: clkin5 + - const: clkin6 + - const: clkin7 + clock-output-names: + items: + - description: eth_125m clock + - description: eth_rmii clock + required: + - clock-names + + - if: + properties: + compatible: + contains: + const: amlogic,a9-mclk-ccu + then: + properties: + clocks: + minItems: 1 + items: + - description: mclk0/1 predivider clock source + - description: mclk0/1 clock source 1 (optional) + - description: mclk0/1 clock source 2 (optional) + - description: mclk0/1 clock source 3 (optional) + clock-names: + minItems: 1 + items: + - const: divin + - const: clkin1 + - const: clkin2 + - const: clkin3 + clock-output-names: + items: + - description: mclk0 pre-divider clock + - description: mclk0 multiplexer clock + - description: mclk0 divider clock + - description: mclk0 gate clock + - description: mclk1 pre-divider clock + - description: mclk1 multiplexer clock + - description: mclk1 divider clock + - description: mclk1 gate clock + required: + - amlogic,clock-init-regs + - clock-names + + - if: + properties: + compatible: + contains: + const: amlogic,a9-dualdivmux-ccu + then: + properties: + clocks: + minItems: 2 + items: + - description: input clock of dualdiv + - description: mux clock source 0 + - description: mux clock source 1 (optional) + - description: mux clock source 2 (optional) + - description: mux clock source 3 (optional) + clock-names: + minItems: 2 + items: + - const: divin + - const: mux0 + - const: mux1 + - const: mux2 + - const: mux3 + clock-output-names: + items: + - description: dualdiv clock + - description: multiplexer clock + required: + - clock-names + +required: + - compatible + - reg + - clocks + - clock-output-names + - "#clock-cells" + +additionalProperties: false + +examples: + - | + apb { + #address-cells =3D <2>; + #size-cells =3D <2>; + clock-sc@370 { + compatible =3D "amlogic,a9-sc-ccu"; + reg =3D <0x0 0x370 0x0 0x4>; + #clock-cells =3D <1>; + clock-output-names =3D "sc_pre", + "sc"; + clocks =3D <&scmi_clk 6>, + <&scmi_clk 9>, + <&scmi_clk 14>, + <&xtal_24m>; + clock-names =3D "clkin0", + "clkin1", + "clkin2", + "clkin3"; + }; + + clock-ts@3a0 { + compatible =3D "amlogic,a9-ts-ccu"; + reg =3D <0x0 0x3a0 0x0 0x4>; + #clock-cells =3D <1>; + clock-output-names =3D "ts_div", + "ts"; + clocks =3D <&xtal_24m>; + }; + + clock-eth@3a4 { + compatible =3D "amlogic,a9-eth-ccu"; + reg =3D <0x0 0x3a4 0x0 0x4>; + #clock-cells =3D <1>; + clock-output-names =3D "eth_125m", + "eth_rmii"; + clocks =3D <&clk_eth_125m_div>, + <&scmi_clk 6>; + clock-names =3D "clk125m", + "clkin0"; + }; + + clock-mclk@833c { + compatible =3D "amlogic,a9-mclk-ccu"; + reg =3D <0x0 0x833c 0x0 0x8>; + #clock-cells =3D <1>; + amlogic,clock-init-regs =3D <0x0 0x04000400 0>, + <0x4 0x96169616 0>; + clock-output-names =3D "mclk0_pre_div", + "mclk0_sel", + "mclk0_div", + "mclk0", + "mclk1_pre_div", + "mclk1_sel", + "mclk1_div", + "mclk1"; + clocks =3D <&mclk_pll>, + <&xtal_24m>, + <&scmi_clk 4>; + clock-names =3D "divin", + "clkin1", + "clkin2"; + }; + }; + + aobus { + #address-cells =3D <2>; + #size-cells =3D <2>; + clkc_ao_cecb: clock-ao_cecb@38 { + compatible =3D "amlogic,a9-dualdivmux-ccu"; + reg =3D <0x0 0x38 0x0 0x8>; + #clock-cells =3D <1>; + + clock-output-names =3D "ao_cecb_dualdiv", + "ao_cecb"; + clocks =3D <&xtal>, + <&clkc_ao_cecb 0>, + <&clkc_rtc 1>; + clock-names =3D "divin", + "mux0", + "mux1"; + }; + + clkc_rtc: clock-rtc@8014c { + compatible =3D "amlogic,a9-dualdivmux-ccu"; + reg =3D <0x0 0x8014c 0x0 0x8>; + #clock-cells =3D <1>; + clock-output-names =3D "rtc_dualdiv", + "rtc"; + clocks =3D <&xtal>, + <&xtal>, + <&clkc_rtc 0>; + clock-names =3D "divin", + "mux0", + "mux1"; + }; + }; diff --git a/include/dt-bindings/clock/amlogic,a9-misc-ccu.h b/include/dt-b= indings/clock/amlogic,a9-misc-ccu.h new file mode 100644 index 000000000000..102aff8d68e4 --- /dev/null +++ b/include/dt-bindings/clock/amlogic,a9-misc-ccu.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (C) 2026 Amlogic, Inc. All rights reserved + */ + +#ifndef __AMLOGIC_A9_MISC_CCU_H +#define __AMLOGIC_A9_MISC_CCU_H + +/* &clkc_sc (Smart Card) */ +#define A9_CLK_SC_PRE 0 +#define A9_CLK_SC 1 + +/* &clkc_ts (Temperature Sensor) */ +#define A9_CLK_TS_DIV 0 +#define A9_CLK_TS 1 + +/* &clkc_gen_out (Generate Output) */ +#define A9_CLK_GENOUT_SEL 0 +#define A9_CLK_GENOUT_DIV 1 +#define A9_CLK_GENOUT 2 + +/* &clkc_12_24m (12M & 24M) */ +#define A9_CLK_24M_IN 0 +#define A9_CLK_12_24M 1 + +/* &clkc_vapb_ge2d (VAPB & GE2D) */ +#define A9_CLK_VAPB 0 +#define A9_CLK_GE2D 1 + +/* &clkc_di (Deinterlacer) */ +#define A9_CLK_VPU_CLKB_TEMP 0 +#define A9_CLK_VPU_CLKB_DIV 1 +#define A9_CLK_VPU_CLKB 2 + +/* &clkc_eth (ETH) */ +#define A9_CLK_ETH_125M 0 +#define A9_CLK_ETH_RMII 1 + +/* &clkc_mclk or &clkc_mclk1 (mclk-ccu) */ +#define A9_CLK_MCLK_0_PRE_DIV 0 +#define A9_CLK_MCLK_0_SEL 1 +#define A9_CLK_MCLK_0_DIV 2 +#define A9_CLK_MCLK_0 3 +#define A9_CLK_MCLK_1_PRE_DIV 4 +#define A9_CLK_MCLK_1_SEL 5 +#define A9_CLK_MCLK_1_DIV 6 +#define A9_CLK_MCLK_1 7 + +/* &clkc_ao_cecb, &clkc_ao_rtc, &clkc_rtc (dualdivmux-ccu) */ +#define A9_CLK_DUALDIV 0 +#define A9_CLK_DUALDIV_SEL 1 + +#endif /* __AMLOGIC_A9_MISC_CCU_H */ --=20 2.42.0