From nobody Tue Feb 10 00:58:47 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A87A32DB794; Mon, 9 Feb 2026 05:49:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770616146; cv=none; b=ug6obrDxR2Yj9wtXMO2rgnlAsW/bfsJCTE7uyt1xODYWJv/NJKc2HDSzzRfybluDnNEKtus4KQp8sZoXQo1P8CwEpqyOdl0JKqm3jVHHkpI+Pqy2wAWrwOmo9PdBUgMLlVuM5vO0Uq2NBYDrZR/dcvZKrIH0xcbCRPqtEsRxgaE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770616146; c=relaxed/simple; bh=yOeClwznsdl7CGdcam/Szj8V4if7Hp60mh/Ckyb0HAI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=pe5rOgYvRjJUHTha3wZ/X5uZnnrTH7IKnIbmCCR9adOVYyYhC6t5Uh0Cp3yzqzKNLfhb1VfvGC+r+yw5tR9SNC86/pDgqt/2TNVwBvbY6IUUJnEcITP8GzLFQDhIhJ3UUQsq7cvkqg4Jie8NRAt4esxuEji+oeXrG4LtnZSMxb8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=N79vCWwc; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="N79vCWwc" Received: by smtp.kernel.org (Postfix) with ESMTPS id 56ED3C4AF09; Mon, 9 Feb 2026 05:49:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1770616146; bh=yOeClwznsdl7CGdcam/Szj8V4if7Hp60mh/Ckyb0HAI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=N79vCWwcEjqYOIfAW4B/wJi81JrguR8ZVpqiMAtqDhDxAnDI/CHrjQ53PR2r8XuQG jLBaR+X/xA+KBW4jb7B7t8Xsi8bkhW3d315T4fB8sDHvWOXzfpdmsVPUU1JeHK5EBR i5klKc/kaxOhBxKC+xy/yaEoLUyDit2q+qSWtIgiifYSvvmVt2L9h8hAWON5P3dhdB FnkwoFUB47QXdO95canP8gGDtn9lt2XxpBGel1lJkgUYzpC5BOXHPJOrgs65zfiLTs aKU6MfLQ3C08AoHkuT6Mx2yV323ZlQ9SM7XQ27L3/RVk+fCyDcAGSg1FCB5GdKkujm gzPjFOFaKQ4qQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3BAF0EF06E5; Mon, 9 Feb 2026 05:49:06 +0000 (UTC) From: Chuan Liu via B4 Relay Date: Mon, 09 Feb 2026 13:48:47 +0800 Subject: [PATCH 01/13] dt-bindings: clock: Add Amlogic A9 standardized model clock control units Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260209-a9_clock_driver-v1-1-a9198dc03d2a@amlogic.com> References: <20260209-a9_clock_driver-v1-0-a9198dc03d2a@amlogic.com> In-Reply-To: <20260209-a9_clock_driver-v1-0-a9198dc03d2a@amlogic.com> To: Neil Armstrong , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Chuan Liu X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1770616142; l=16188; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=LGR7t5zw1CkYLkatuNOHLf45xN42LhF2iAUlxglSJEw=; b=P8RRTNzfxAdNQaYHVPOQYUJftNvVqKauNV9azhek1IyBjv3EqHVBJbZm81g5dx731tDFkmUBZ 0D0Bv7aLiQZCfrXokH658fUGnlSAAoysQjIbNmal+G5fyQwM/LVF+GC X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu Add dt-binding documentation for standardized model clock control units in A9 SoC family. Signed-off-by: Chuan Liu --- .../bindings/clock/amlogic,a9-model-ccu.yaml | 435 +++++++++++++++++= ++++ 1 file changed, 435 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/amlogic,a9-model-ccu.y= aml b/Documentation/devicetree/bindings/clock/amlogic,a9-model-ccu.yaml new file mode 100644 index 000000000000..56c5cbe1b246 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,a9-model-ccu.yaml @@ -0,0 +1,435 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2026 Amlogic, Inc. All rights reserved +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/amlogic,a9-model-ccu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic A9 Family Standardized Model Clock Control Unit + +maintainers: + - Chuan Liu + +description: + The clock tree within the A9 is composed of numerous instances of these + standardized model CCU (Clock Control Units). + +properties: + compatible: + oneOf: + - items: + - const: amlogic,a9-composite-ccu + description: Supports clock source selection, frequency division, = and + clock gating. + - items: + - const: amlogic,a9-composite-ccu-mult + description: Some modules have multiple input clocks and contain + multiple composite-ccus internally. + - items: + - const: amlogic,a9-noglitch-ccu + description: Provides the same functionality as composite-ccu but + includes glitch suppression during frequency transiti= ons. + - items: + - const: amlogic,a9-noglitch-ccu-mult + description: Some modules have multiple input clocks and contain + multiple noglitch-ccus internally. + - items: + - const: amlogic,a9-sysbus-ccu + description: Consists of multiple gating arrays, commonly used for + Amlogic's sys_clk and axi_clk. + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 16 + + clock-names: + minItems: 1 + maxItems: 16 + + clock-output-names: + minItems: 1 + # The sysbus-ccu of A9 supports up to 128 gates + maxItems: 128 + + '#clock-cells': + description: + The clock controller of a module may contain one or more CCU(s). Whe= n a + clock controller has multiple CCUs, an index is required to specify a + particular CCU within the clock controller. + oneOf: + - const: 0 + description: Single clock output, no specifier needed + - const: 1 + description: Multiple clocks, index selects specific output + + amlogic,clock-max-frequency: + description: | + Each clock's maximum output frequency is constrained during hardware + design to ensure proper timing requirements for the clock network. I= f the + clock frequency configured exceeds this design limit, it can lead to + abnormal behavior in modules relying on that clock and may even cause + cross-talk that affects other modules. + + In the driver, this property is parsed, and interface functions from= the + CCF are called to enforce the clock's maximum frequency, preventing + potential issues caused by excessive clock frequency configurations. + $ref: /schemas/types.yaml#/definitions/uint32-array + + amlogic,reg-layout: + description: + These standardized model CCUs require register configuration for the= ir + clock functions. This property node describes the register layout + parameters for each model's CCU. + $ref: /schemas/types.yaml#/definitions/uint32-matrix + +allOf: + - if: + properties: + compatible: + anyOf: + - contains: + const: amlogic,a9-composite-ccu + - contains: + const: amlogic,a9-noglitch-ccu + then: + properties: + '#clock-cells': + const: 0 + clock-output-names: + minItems: 1 + maxItems: 1 + else: + properties: + '#clock-cells': + const: 1 + clock-output-names: + minItems: 2 + + - if: + properties: + compatible: + contains: + const: amlogic,a9-composite-ccu + then: + properties: + clocks: + minItems: 1 + items: + - description: input clock source 0 + - description: input clock source 1 (optional) + - description: input clock source 2 (optional) + - description: input clock source 3 (optional) + - description: input clock source 4 (optional) + - description: input clock source 5 (optional) + - description: input clock source 6 (optional) + - description: input clock source 7 (optional) + clock-names: + minItems: 1 + items: + - const: clkin0 + - const: clkin1 + - const: clkin2 + - const: clkin3 + - const: clkin4 + - const: clkin5 + - const: clkin6 + - const: clkin7 + amlogic,reg-layout: + description: | + composite-ccu contains three register layout parameters: + * register offset + * bit offset + * divider effective bit width + required: + - amlogic,reg-layout + - clock-names + + - if: + properties: + compatible: + contains: + const: amlogic,a9-composite-ccu-mult + then: + properties: + clocks: + description: + Some clock controllers contain two composite-ccus (labeled + composite_a and composite_b). In certain controllers, composit= e_a + and composite_b share a common clock source, while in others t= hey + have independent clock sources. + minItems: 1 + items: + - description: composite_a/b's input clock source 0 + - description: composite_a/b's input clock source 1 (optional) + - description: composite_a/b's input clock source 2 (optional) + - description: composite_a/b's input clock source 3 (optional) + - description: composite_a/b's input clock source 4 (optional) + - description: composite_a/b's input clock source 5 (optional) + - description: composite_a/b's input clock source 6 (optional) + - description: composite_a/b's input clock source 7 (optional) + - description: composite_b's input clock source 0 (optional) + - description: composite_b's input clock source 1 (optional) + - description: composite_b's input clock source 2 (optional) + - description: composite_b's input clock source 3 (optional) + - description: composite_b's input clock source 4 (optional) + - description: composite_b's input clock source 5 (optional) + - description: composite_b's input clock source 6 (optional) + - description: composite_b's input clock source 7 (optional) + clock-names: + minItems: 1 + items: + - const: clkin0 + - const: clkin1 + - const: clkin2 + - const: clkin3 + - const: clkin4 + - const: clkin5 + - const: clkin6 + - const: clkin7 + - const: bclkin0 + - const: bclkin1 + - const: bclkin2 + - const: bclkin3 + - const: bclkin4 + - const: bclkin5 + - const: bclkin6 + - const: bclkin7 + amlogic,reg-layout: + description: | + composite-ccu contains three register layout parameters: + * register offset + * bit offset + * divider effective bit width + required: + - amlogic,reg-layout + - clock-names + + - if: + properties: + compatible: + contains: + const: amlogic,a9-noglitch-ccu + then: + properties: + clocks: + minItems: 1 + items: + - description: input clock source 0 + - description: input clock source 1 (optional) + - description: input clock source 2 (optional) + - description: input clock source 3 (optional) + - description: input clock source 4 (optional) + - description: input clock source 5 (optional) + - description: input clock source 6 (optional) + - description: input clock source 7 (optional) + clock-names: + minItems: 1 + items: + - const: clkin0 + - const: clkin1 + - const: clkin2 + - const: clkin3 + - const: clkin4 + - const: clkin5 + - const: clkin6 + - const: clkin7 + required: + - clock-names + + - if: + properties: + compatible: + contains: + const: amlogic,a9-noglitch-ccu-mult + then: + properties: + clocks: + minItems: 1 + items: + - description: input clock source 0 + - description: input clock source 1 (optional) + - description: input clock source 2 (optional) + - description: input clock source 3 (optional) + - description: input clock source 4 (optional) + - description: input clock source 5 (optional) + - description: input clock source 6 (optional) + - description: input clock source 7 (optional) + clock-names: + minItems: 1 + items: + - const: clkin0 + - const: clkin1 + - const: clkin2 + - const: clkin3 + - const: clkin4 + - const: clkin5 + - const: clkin6 + - const: clkin7 + amlogic,reg-layout: + description: | + composite-ccu contains one register layout parameters: + * register offset + required: + - amlogic,reg-layout + - clock-names + + - if: + properties: + compatible: + contains: + const: amlogic,a9-sysbus-ccu + then: + properties: + clocks: + maxItems: 1 + description: input clock of sysbus-ccu + amlogic,reg-layout: + description: | + composite-ccu contains two register layout parameters: + * register offset + * bit offset + required: + - amlogic,reg-layout + +required: + - compatible + - reg + - clocks + - clock-output-names + - "#clock-cells" + +additionalProperties: false + +examples: + - | + clk_dummy: clock-dummy { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <0>; + clock-output-names =3D "dummy"; + status =3D "disabled"; + }; + + apb { + #address-cells =3D <2>; + #size-cells =3D <2>; + clock-controller@350 { + compatible =3D "amlogic,a9-composite-ccu"; + reg =3D <0x0 0x350 0x0 0x4>; + #clock-cells =3D <0>; + amlogic,clock-max-frequency =3D <50000000>; + amlogic,reg-layout =3D <0x0 0 7>; + clock-output-names =3D "sar_adc"; + clocks =3D <&xtal_24m>, + <&scmi_clk 17>; + clock-names =3D "clkin0", "clkin1"; + }; + + clock-controller@290 { + compatible =3D "amlogic,a9-composite-ccu-mult"; + reg =3D <0x0 0x290 0x0 0x8>; + #clock-cells =3D <1>; + amlogic,clock-max-frequency =3D <250000000>, + <250000000>, + <1200000000>; + amlogic,reg-layout =3D <0x0 0 7>, + <0x0 16 7>, + <0x4 0 7>; + clock-output-names =3D "sd_emmc_a", + "sd_emmc_b", + "sd_emmc_c"; + clocks =3D <&xtal_24m>, + <&scmi_clk 6>, + <&scmi_clk 10>; + clock-names =3D "clkin0", + "clkin1", + "clkin2"; + }; + + clock-controller@378 { + compatible =3D "amlogic,a9-composite-ccu-mult"; + reg =3D <0x0 0x378 0x0 0x4>; + #clock-cells =3D <1>; + amlogic,clock-max-frequency =3D <500000000>, + <667000000>; + amlogic,reg-layout =3D <0x0 0 7>, + <0x0 16 7>; + clock-output-names =3D "dptx_apb2", + "dptx_aud"; + clocks =3D <&xtal_24m>, + <&scmi_clk 17>, + <&scmi_clk 12>, + <&scmi_clk 14>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&xtal_24m>, /* composite-ccu_b's clock source 0 */ + <&scmi_clk 17>, /* composite-ccu_b's clock source 1 */ + <&scmi_clk 10>, /* composite-ccu_b's clock source 2 */ + <&scmi_clk 12>; /* composite-ccu_b's clock source 3 */ + clock-names =3D "clkin0", + "clkin1", + "clkin2", + "clkin3", + "clkin4", + "clkin5", + "clkin6", + "clkin7", + "bclkin0", + "bclkin1", + "bclkin2", + "bclkin3"; + }; + + clock-controller@420 { + compatible =3D "amlogic,a9-noglitch-ccu"; + reg =3D <0x0 0x420 0x0 0x4>; + #clock-cells =3D <0>; + amlogic,clock-max-frequency =3D <800000000>; + clock-output-names =3D "dspa"; + clocks =3D <&xtal_24m>, + <&scmi_clk 8>, + <&scmi_clk 10>; + clock-names =3D "clkin0", + "clkin1", + "clkin2"; + }; + + clock-controller@400 { + compatible =3D "amlogic,a9-noglitch-ccu-mult"; + reg =3D <0x0 0x400 0x0 0x8>; + #clock-cells =3D <1>; + /* + * If only one maximum frequency is specified, it is shared by= all + * clocks under the current device node. + */ + amlogic,clock-max-frequency =3D <1000000000>; + amlogic,reg-layout =3D <0x0>, + <0x4>; + clock-output-names =3D "mali", + "mali_stack"; + clocks =3D <&xtal_24m>, + <&scmi_clk 23>, + <&scmi_clk 6>; + clock-names =3D "clkin0", + "clkin1", + "clkin2"; + }; + + clock-sysbus@230 { + compatible =3D "amlogic,a9-sysbus-ccu"; + reg =3D <0x0 0x230 0x0 0x10>; + #clock-cells =3D <1>; + amlogic,reg-layout =3D <0 0>, + <0 1>, + <0 3>; + clock-output-names =3D "sys_am_axi", + "sys_dos", + "sys_mipi_dsi"; + clocks =3D <&scmi_clk 17>; + }; + }; --=20 2.42.0