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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2b8647bd6casm5609940eec.7.2026.02.08.20.49.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Feb 2026 20:49:42 -0800 (PST) From: Qiang Yu Date: Sun, 08 Feb 2026 20:49:40 -0800 Subject: [PATCH 2/2] phy: qcom: qmp-pcie: Add vdda-refgen supplies for Glymur Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260208-refgen-v1-2-87ca84fd78b3@oss.qualcomm.com> References: <20260208-refgen-v1-0-87ca84fd78b3@oss.qualcomm.com> In-Reply-To: <20260208-refgen-v1-0-87ca84fd78b3@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Qiang Yu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1770612579; l=1964; i=qiang.yu@oss.qualcomm.com; s=20250513; h=from:subject:message-id; bh=+Qdh1KTp4rpkKuZ6jiND1J5x3Q5cGxD4YjHz6yZWsi4=; b=wLn++a8eAKQQcLHtX5yoaE3oQLpP6Bv24NmK/5D4gIMlCKrlm4Ch/Y0tkMVNImA8JaosSSQLJ yAmAB170VIwB1Om86GFNO7hdvn2MKriep4NGuUSXJLDTPnWHJtpNPeY X-Developer-Key: i=qiang.yu@oss.qualcomm.com; a=ed25519; pk=Rr94t+fykoieF1ngg/bXxEfr5KoQxeXPtYxM8fBQTAI= X-Authority-Analysis: v=2.4 cv=Ddcaa/tW c=1 sm=1 tr=0 ts=69896767 cx=c_pps a=PfFC4Oe2JQzmKTvty2cRDw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=EUspDBNiAAAA:8 a=m2jQVEIWa0EwQwJFt7gA:9 a=QEXdDO2ut3YA:10 a=6Ab_bkdmUrQuMsNx7PHu:22 X-Proofpoint-ORIG-GUID: eU8cQhYyWtjSHYVkWXCM0BXS-Q51rXjL X-Proofpoint-GUID: eU8cQhYyWtjSHYVkWXCM0BXS-Q51rXjL X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjA5MDAzNyBTYWx0ZWRfXzeXuGCkPxZAm k2r5ATnZTAfFcoPFiDOUZhGMiAwKWTKCe42lTKHbNCH7b2IF0B27rICj/43n5jhGUlZM6pABYml HjwAAigKosEkU9U2HUCqZTqkhYPh/ZnPxXLSj0IJC2Pv3NCK5hxE8fX7c7DEn9WlSJnRak9RIpx QtQtWDgIzakBuyNZqo6wRkw87PJfHt7mwhYA+3ea2VD/GVSk6yXLxn3wHbZ2ie9M5ymHGDhY0Ki CZ2tFE437PfnhBZkvkWC3nc3Ezf0r3do81ZD382VnaOVHdxuY89KQ+Ib5KVl+sXp2mznEavhpjV XfSyF2UXPVsij5YjaM2j8x2PnpLE7gcOBX5GOmb7vIyq6odEMlpMhc+Vxg5hdzo4utf1MKKLwO5 Rke7L+ds0pLupdgqhxIfs+Tbj88QXA2CxmzPpyNXNMVADmJZe+MzMHUD1M4xW9aKk43mudvJYV/ 7FWBrOQQVIcLAxDyc+Q== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-08_05,2026-02-05_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 spamscore=0 clxscore=1015 suspectscore=0 impostorscore=0 malwarescore=0 lowpriorityscore=0 adultscore=0 phishscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602090037 The refgen providing reference voltage for PCIe QMP PHY on Glymur requires two power supplies independent from the PHY's core and qref rails. Add support for vdda-refgen0p9 and vdda-refgen1p2 supplies with a dedicated glymur_qmp_phy_vreg_l list. Update both Gen5x4 and Gen4x2 configurations to use the new supply list. Signed-off-by: Qiang Yu --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcom= m/phy-qcom-qmp-pcie.c index fed2fc9bb31108d51f88d34f3379c7744681f485..b24ed260f30a689b5668f38c147= 1c0ab2aced0cc 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -3382,6 +3382,10 @@ static const char * const sm8550_qmp_phy_vreg_l[] = =3D { "vdda-phy", "vdda-pll", "vdda-qref", }; =20 +static const char * const glymur_qmp_phy_vreg_l[] =3D { + "vdda-phy", "vdda-pll", "vdda-refgen0p9", "vdda-refgen1p2", +}; + /* list of resets */ static const char * const ipq8074_pciephy_reset_l[] =3D { "phy", "common", @@ -4623,8 +4627,8 @@ static const struct qmp_phy_cfg glymur_qmp_gen5x4_pci= ephy_cfg =3D { =20 .reset_list =3D sdm845_pciephy_reset_l, .num_resets =3D ARRAY_SIZE(sdm845_pciephy_reset_l), - .vreg_list =3D qmp_phy_vreg_l, - .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + .vreg_list =3D glymur_qmp_phy_vreg_l, + .num_vregs =3D ARRAY_SIZE(glymur_qmp_phy_vreg_l), =20 .regs =3D pciephy_v8_50_regs_layout, =20 @@ -4639,8 +4643,8 @@ static const struct qmp_phy_cfg glymur_qmp_gen4x2_pci= ephy_cfg =3D { =20 .reset_list =3D sdm845_pciephy_reset_l, .num_resets =3D ARRAY_SIZE(sdm845_pciephy_reset_l), - .vreg_list =3D qmp_phy_vreg_l, - .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + .vreg_list =3D glymur_qmp_phy_vreg_l, + .num_vregs =3D ARRAY_SIZE(glymur_qmp_phy_vreg_l), =20 .regs =3D pciephy_v8_regs_layout, =20 --=20 2.34.1