From nobody Mon Feb 9 22:18:49 2026 Received: from canpmsgout02.his.huawei.com (canpmsgout02.his.huawei.com [113.46.200.217]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E88AD2BD030 for ; Sat, 7 Feb 2026 09:56:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=113.46.200.217 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770458174; cv=none; b=LPboeZBOCAXpKX/mrROY9O0aQXDw0Z9qs6p/WEENWAsQ7mzZH48sUNPOu20+cLvKIuPaz1v5szAgGnSOEiiAuwwdoV+YxsJJ3cBP2Fs0LS8LOCA4KV4KZPg8L6vIkYQoy8IJkrVg2zArgLHdp5Z7im7DNXsErHb6z9yqAQynjvY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770458174; c=relaxed/simple; bh=ClDg6SPO44OI2gGnl3ro1WQkdCCqAcoGxKn+cGm2tzM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=EJrKXAo+Csg9lzwdVnrgTV/EJDmWssKJf+d0VL/wV15eAbt6J5DZkhVDVFhPmgWWDIptCX+hxj2mLd/mD6lbU0QvjrgaYafbisPrBQGoodLs06keT4NO58QP7FSV0JpUPQg2bVV5PKkIb/bczy7jZoKwXNPAF+56FLgM0FrhkA0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b=uMmtOERG; arc=none smtp.client-ip=113.46.200.217 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b="uMmtOERG" dkim-signature: v=1; a=rsa-sha256; d=huawei.com; s=dkim; c=relaxed/relaxed; q=dns/txt; h=From; bh=lQzJiDlQmkLEbZnwSaMgzOTay0f0SozmEbd6odkr0R8=; b=uMmtOERGPMiJeZeBfm0AfN948UHRTG1zTuUVMwa12DYerfLW2gIk4HLuSy+Zylb3C3cpU5oEs o95zpVhnXoldz6sIzDKEOIq6/k5IqGocf42R0t8NOWs/9jVKih2j2tBpG3oj9prTXZ8udGcvkD/ 2W2XtMDMsjjPjWSviJKcyZg= Received: from mail.maildlp.com (unknown [172.19.162.223]) by canpmsgout02.his.huawei.com (SkyGuard) with ESMTPS id 4f7R7M5BLwzcb0x; Sat, 7 Feb 2026 17:51:43 +0800 (CST) Received: from dggemv706-chm.china.huawei.com (unknown [10.3.19.33]) by mail.maildlp.com (Postfix) with ESMTPS id BCFD440569; Sat, 7 Feb 2026 17:56:11 +0800 (CST) Received: from kwepemq100007.china.huawei.com (7.202.195.175) by dggemv706-chm.china.huawei.com (10.3.19.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Sat, 7 Feb 2026 17:56:11 +0800 Received: from localhost.huawei.com (10.169.71.169) by kwepemq100007.china.huawei.com (7.202.195.175) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Sat, 7 Feb 2026 17:56:10 +0800 From: Yongbang Shi To: , , , , , , , , CC: , , , , , , , , Subject: [PATCH drm-dp 4/4] drm/hisilicon/hibmc: use clock to look up the PLL value Date: Sat, 7 Feb 2026 17:48:37 +0800 Message-ID: <20260207094837.1468985-5-shiyongbang@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20260207094837.1468985-1-shiyongbang@huawei.com> References: <20260207094837.1468985-1-shiyongbang@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems500002.china.huawei.com (7.221.188.17) To kwepemq100007.china.huawei.com (7.202.195.175) Content-Type: text/plain; charset="utf-8" From: Lin He In the past, we use width and height to look up our PLL value. But actually the actual clock check is also necessnary. There are some resolutions that width and height same, but its clock different. Add the clock check when using pll_table to determine the PLL value. Fixes: da52605eea8f ("drm/hisilicon/hibmc: Add support for display engine") Signed-off-by: Lin He Signed-off-by: Yongbang Shi --- .../gpu/drm/hisilicon/hibmc/hibmc_drm_de.c | 80 +++++++++++-------- 1 file changed, 46 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c b/drivers/gpu/d= rm/hisilicon/hibmc/hibmc_drm_de.c index 89bed78f1466..8561acbbc3c8 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c +++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c @@ -22,6 +22,8 @@ #include "hibmc_drm_drv.h" #include "hibmc_drm_regs.h" =20 +#define CLOCK_TOLERANCE 100 /* kHz tolerance */ + struct hibmc_display_panel_pll { u64 M; u64 N; @@ -32,26 +34,43 @@ struct hibmc_display_panel_pll { struct hibmc_dislay_pll_config { u64 hdisplay; u64 vdisplay; + int clock; u32 pll1_config_value; u32 pll2_config_value; }; =20 static const struct hibmc_dislay_pll_config hibmc_pll_table[] =3D { - {640, 480, CRT_PLL1_HS_25MHZ, CRT_PLL2_HS_25MHZ}, - {800, 600, CRT_PLL1_HS_40MHZ, CRT_PLL2_HS_40MHZ}, - {1024, 768, CRT_PLL1_HS_65MHZ, CRT_PLL2_HS_65MHZ}, - {1152, 864, CRT_PLL1_HS_80MHZ_1152, CRT_PLL2_HS_80MHZ}, - {1280, 768, CRT_PLL1_HS_80MHZ, CRT_PLL2_HS_80MHZ}, - {1280, 720, CRT_PLL1_HS_74MHZ, CRT_PLL2_HS_74MHZ}, - {1280, 960, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ}, - {1280, 1024, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ}, - {1440, 900, CRT_PLL1_HS_106MHZ, CRT_PLL2_HS_106MHZ}, - {1600, 900, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ}, - {1600, 1200, CRT_PLL1_HS_162MHZ, CRT_PLL2_HS_162MHZ}, - {1920, 1080, CRT_PLL1_HS_148MHZ, CRT_PLL2_HS_148MHZ}, - {1920, 1200, CRT_PLL1_HS_193MHZ, CRT_PLL2_HS_193MHZ}, + {640, 480, 25000, CRT_PLL1_HS_25MHZ, CRT_PLL2_HS_25MHZ}, + {800, 600, 40000, CRT_PLL1_HS_40MHZ, CRT_PLL2_HS_40MHZ}, + {1024, 768, 65000, CRT_PLL1_HS_65MHZ, CRT_PLL2_HS_65MHZ}, + {1152, 864, 78750, CRT_PLL1_HS_80MHZ_1152, CRT_PLL2_HS_80MHZ}, + {1280, 768, 80000, CRT_PLL1_HS_80MHZ, CRT_PLL2_HS_80MHZ}, + {1280, 720, 74375, CRT_PLL1_HS_74MHZ, CRT_PLL2_HS_74MHZ}, + {1280, 960, 108000, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ}, + {1280, 1024, 108000, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ}, + {1440, 900, 105952, CRT_PLL1_HS_106MHZ, CRT_PLL2_HS_106MHZ}, + {1600, 900, 108000, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ}, + {1600, 1200, 162500, CRT_PLL1_HS_162MHZ, CRT_PLL2_HS_162MHZ}, + {1920, 1080, 148750, CRT_PLL1_HS_148MHZ, CRT_PLL2_HS_148MHZ}, + {1920, 1200, 193750, CRT_PLL1_HS_193MHZ, CRT_PLL2_HS_193MHZ}, }; =20 +static int hibmc_get_best_clock_idx(const struct drm_display_mode *mode) +{ + int i, diff; + + for (i =3D 0; i < ARRAY_SIZE(hibmc_pll_table); i++) { + if (hibmc_pll_table[i].hdisplay =3D=3D mode->hdisplay && + hibmc_pll_table[i].vdisplay =3D=3D mode->vdisplay) { + diff =3D abs(mode->clock - hibmc_pll_table[i].clock); + if (diff < mode->clock / 100) /* tolerance 1/100 */ + return i; + } + } + + return -EOPNOTSUPP; +} + static int hibmc_plane_atomic_check(struct drm_plane *plane, struct drm_atomic_state *state) { @@ -214,17 +233,13 @@ static enum drm_mode_status hibmc_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode) { - size_t i =3D 0; int vrefresh =3D drm_mode_vrefresh(mode); =20 if (vrefresh < 59 || vrefresh > 61) return MODE_NOCLOCK; =20 - for (i =3D 0; i < ARRAY_SIZE(hibmc_pll_table); i++) { - if (hibmc_pll_table[i].hdisplay =3D=3D mode->hdisplay && - hibmc_pll_table[i].vdisplay =3D=3D mode->vdisplay) - return MODE_OK; - } + if (hibmc_get_best_clock_idx(mode) >=3D 0) + return MODE_OK; =20 return MODE_BAD; } @@ -281,23 +296,20 @@ static void set_vclock_hisilicon(struct drm_device *d= ev, u64 pll) writel(val, priv->mmio + CRT_PLL1_HS); } =20 -static void get_pll_config(u64 x, u64 y, u32 *pll1, u32 *pll2) +static void get_pll_config(struct drm_display_mode *mode, u32 *pll1, u32 *= pll2) { - size_t i; - size_t count =3D ARRAY_SIZE(hibmc_pll_table); - - for (i =3D 0; i < count; i++) { - if (hibmc_pll_table[i].hdisplay =3D=3D x && - hibmc_pll_table[i].vdisplay =3D=3D y) { - *pll1 =3D hibmc_pll_table[i].pll1_config_value; - *pll2 =3D hibmc_pll_table[i].pll2_config_value; - return; - } + int idx; + + idx =3D hibmc_get_best_clock_idx(mode); + if (idx < 0) { + /* if found none, we use default value */ + *pll1 =3D CRT_PLL1_HS_25MHZ; + *pll2 =3D CRT_PLL2_HS_25MHZ; + return; } =20 - /* if found none, we use default value */ - *pll1 =3D CRT_PLL1_HS_25MHZ; - *pll2 =3D CRT_PLL2_HS_25MHZ; + *pll1 =3D hibmc_pll_table[idx].pll1_config_value; + *pll2 =3D hibmc_pll_table[idx].pll2_config_value; } =20 /* @@ -319,7 +331,7 @@ static u32 display_ctrl_adjust(struct drm_device *dev, x =3D mode->hdisplay; y =3D mode->vdisplay; =20 - get_pll_config(x, y, &pll1, &pll2); + get_pll_config(mode, &pll1, &pll2); writel(pll2, priv->mmio + CRT_PLL2_HS); set_vclock_hisilicon(dev, pll1); =20 --=20 2.33.0