From nobody Mon Feb 9 03:11:23 2026 Received: from mail-pj1-f73.google.com (mail-pj1-f73.google.com [209.85.216.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DA1AE28725A for ; Sat, 7 Feb 2026 01:23:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.73 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770427437; cv=none; b=XiDfACGgh3n6X6LFOyHoVMTq5NjdW4iNS4QOzTarx2WWG8DnxKjwnMVP9UsqXyEKlHyhALS2FoteEraI99q15JAeSNbh373Zcka9qbzt2xC4DDfwxUG41OXFigIP/5idcPJbm4z5ueFilrW77bpX5rCtLJzYWtcLv7tCbNtCD/I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770427437; c=relaxed/simple; bh=I+RxoIGb1w+j2Z99Cy0rUjANHksL4tl1ovFMTp7mg1c=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=K6iS7MOXmSV/vRcA+TCuh8mV84J9QpWCrBGavim7nHws2o3GnKCLauAjotszQW/GtOOMcrgUfQRINyLYBrgRQGykwOgWFI6wb7rs7qzWf2JBBaRdqycmjBS0DXKT9XwxuVVqBEd2d7Rp9lbGbAOEHVLxx/SwLePgo744B6C51R4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--jmattson.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=v+Ea/bvt; arc=none smtp.client-ip=209.85.216.73 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--jmattson.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="v+Ea/bvt" Received: by mail-pj1-f73.google.com with SMTP id 98e67ed59e1d1-3545dbb7f14so2489805a91.0 for ; Fri, 06 Feb 2026 17:23:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1770427436; x=1771032236; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=dU5KMBJtS4wTduPehGSWJG7pWtZ+gBpfTPOt7bZn03I=; b=v+Ea/bvt3/x60lb1ffT5HH8hd7QIAVlYryxw8vP6rCYm/Q105iTczl5BFw5ZvnUgdh M5iiCb0oLA2sz+bEKCxL0Wf8LrTkH4JQWvZVwtCSxtJehcksSZxOTZx6BQMu9XM00vSy Tov+g+EXN/i5GPn8WNmd8UygWqvZoFWTQUegriL2enDzdHU9JvpQbaSg1pV5viOdvhJF JFe7upyZ4bcrc0yWBjuN9dOBRCpA0xv38X9AhyPSBz5j6C+LfFAjulH3/VlQJpazje11 atc04gqaj2AtLEnjx/2W5D5QSiKkCn6T1sgHk9Edb1OLsNBBqZ1Z1lXsd4UyU/yqXkxU lmBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770427436; x=1771032236; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=dU5KMBJtS4wTduPehGSWJG7pWtZ+gBpfTPOt7bZn03I=; b=tWmxcrcWnDPD8761PSy2eUW11GjHb2VFyHEfh/4L5zxTkq040skXdC8D5cy3xUMGqy n8i9nFSwtkKb0V3/fNGmHybq5qtWLrk1fs2jfVi4inei4Gj50siHNvUp3kP/nj2i/6ZX Nx0pbENobdH/oZtVlbhplhqsXg2RDaHXBwxEyVOpm6146HpI4ePsDcqaGOIps7DJ1dXy bSvCeHeCdUoR1ZWQirWfG+AH2PlodkAJGlA5GYlN6eVVsDDcsW9NXbC4QF2nWecbPUlm zRxYHdaQFxj3m90TQUizpGMZ64320/jzXSoqXbgigoyQ8d70E+JVvhHnJmkynNmuyQOF Terw== X-Forwarded-Encrypted: i=1; AJvYcCWca4+S0imCycsiv6EiVeHGUbHhyY6nHvbalY0v7IwBNl1eAaVyai0fUN5otgEB0LxU6XLtdztfvv7YC4o=@vger.kernel.org X-Gm-Message-State: AOJu0YzEKVcm3cVsGpdnhz4v01tGUui9xAcBW9z3q3iA7GSEJMSV7qZg 1jznSTdBbGQB64X8/WSqI382HOwo0d4Uksrx423L4cbPk7Me+oic2hj/gLAMBVs1nl+9tRwhrgp 9PGsjdCrWgi5WBw== X-Received: from pgbbd9.prod.google.com ([2002:a65:6e09:0:b0:bac:6acd:8182]) (user=jmattson job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a20:3d10:b0:390:ca32:da20 with SMTP id adf61e73a8af0-393aeea94fbmr4223884637.10.1770427436293; Fri, 06 Feb 2026 17:23:56 -0800 (PST) Date: Fri, 6 Feb 2026 17:23:28 -0800 In-Reply-To: <20260207012339.2646196-1-jmattson@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260207012339.2646196-1-jmattson@google.com> X-Mailer: git-send-email 2.53.0.rc2.204.g2597b5adb4-goog Message-ID: <20260207012339.2646196-3-jmattson@google.com> Subject: [PATCH v3 2/5] KVM: x86/pmu: Disable Host-Only/Guest-Only events as appropriate for vCPU state From: Jim Mattson To: Sean Christopherson , Paolo Bonzini , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Peter Zijlstra , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , Shuah Khan , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kselftest@vger.kernel.org, Yosry Ahmed , Mingwei Zhang , Sandipan Das Cc: Jim Mattson Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update amd_pmu_set_eventsel_hw() to clear the event selector's hardware enable bit when the PMC should not count based on the guest's Host-Only and Guest-Only event selector bits and the current vCPU state. Signed-off-by: Jim Mattson --- arch/x86/include/asm/perf_event.h | 2 ++ arch/x86/kvm/svm/pmu.c | 18 ++++++++++++++++++ 2 files changed, 20 insertions(+) diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_= event.h index 0d9af4135e0a..4dfe12053c09 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -58,6 +58,8 @@ #define AMD64_EVENTSEL_INT_CORE_ENABLE (1ULL << 36) #define AMD64_EVENTSEL_GUESTONLY (1ULL << 40) #define AMD64_EVENTSEL_HOSTONLY (1ULL << 41) +#define AMD64_EVENTSEL_HOST_GUEST_MASK \ + (AMD64_EVENTSEL_HOSTONLY | AMD64_EVENTSEL_GUESTONLY) =20 #define AMD64_EVENTSEL_INT_CORE_SEL_SHIFT 37 #define AMD64_EVENTSEL_INT_CORE_SEL_MASK \ diff --git a/arch/x86/kvm/svm/pmu.c b/arch/x86/kvm/svm/pmu.c index d9ca633f9f49..8d451110a94d 100644 --- a/arch/x86/kvm/svm/pmu.c +++ b/arch/x86/kvm/svm/pmu.c @@ -149,8 +149,26 @@ static int amd_pmu_get_msr(struct kvm_vcpu *vcpu, stru= ct msr_data *msr_info) =20 static void amd_pmu_set_eventsel_hw(struct kvm_pmc *pmc) { + struct kvm_vcpu *vcpu =3D pmc->vcpu; + u64 host_guest_bits; + pmc->eventsel_hw =3D (pmc->eventsel & ~AMD64_EVENTSEL_HOSTONLY) | AMD64_EVENTSEL_GUESTONLY; + + if (!(pmc->eventsel & ARCH_PERFMON_EVENTSEL_ENABLE)) + return; + + if (!(vcpu->arch.efer & EFER_SVME)) + return; + + host_guest_bits =3D pmc->eventsel & AMD64_EVENTSEL_HOST_GUEST_MASK; + if (!host_guest_bits || host_guest_bits =3D=3D AMD64_EVENTSEL_HOST_GUEST_= MASK) + return; + + if (!!(host_guest_bits & AMD64_EVENTSEL_GUESTONLY) =3D=3D is_guest_mode(v= cpu)) + return; + + pmc->eventsel_hw &=3D ~ARCH_PERFMON_EVENTSEL_ENABLE; } =20 static int amd_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_inf= o) --=20 2.53.0.rc2.204.g2597b5adb4-goog