From nobody Mon Feb 9 07:06:22 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C77D1286D72; Sun, 8 Feb 2026 01:28:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770514089; cv=none; b=dZE21ssNvyAceEgN8qPU6jZdRgOU4TA5rm+Ntwhl/333uWrNJdxFz0B2GiEOZ/FMVmS6nckzHQsOcN0s1/WaR3wN/VXZC0hybCcFZNzbN/eRe8f5Y7zu42QGm5c8sbLRyqOIg4oZOamm6NswAZNZ4NCEVgD/F9ekaplC0VBMmuM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770514089; c=relaxed/simple; bh=o3S+HSi/kG9FeIwRWsohuDx7WihMkM9o1fwaD7LBPOs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=bY5kc5hxkh7T+L0ZE2rqLRctwDv2ViMNLuaNp6NS5ldWOBdsy2tjcrwI9n2z+5MRJwTDMCHYb0NrErK9tCq8jkTVkwn8EuvgMAHxUE+FFMn99R5ZM99WxoEDTDMwTDGnaPAuuIaPqfy6ckrObJ/r4KtJWJg+GI+Uc4FqJRs9+aw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=FG/yG5TG; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="FG/yG5TG" Received: by smtp.kernel.org (Postfix) with ESMTPS id 9FBA9C19421; Sun, 8 Feb 2026 01:28:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1770514089; bh=o3S+HSi/kG9FeIwRWsohuDx7WihMkM9o1fwaD7LBPOs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=FG/yG5TGhf2IgKuBCSaV93/BTtnXMoR8BMiCRT39F4wBT+zf5r9kA7FxyYNq10+Pe n8JOqm7R1YKrBvBRgZXzTbSu5iETotO7jOxxSLSOwhJvALDyk2yASQZ+WJPC3zDDbf URqXXnvQSL5bwcusg9d6Gj8gIu3zkFv9qtnZR+NkEnsqDUXC/mOu6HsrsNq8df5Jwq 35b3NXYJNeQCms0gP9NZn+4y/3W3VlA3Miv30KhiFdi4DjPdxF6VdDhUENprWva6bg sRWrXI2VcHJa/5TxujMCL4WzSOZW53x921qgTB0q18TxYq4WNUizk6E2NwWxZKOryZ 8UjUw06wjAlwQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 904EDECD9A7; Sun, 8 Feb 2026 01:28:09 +0000 (UTC) From: Aaron Kling via B4 Relay Date: Sat, 07 Feb 2026 19:28:06 -0600 Subject: [PATCH 1/3] arm64: dts: qcom: sm8550: add OSM L3 node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260207-sm8550-ddr-bw-scaling-v1-1-d96c3f39ac4b@gmail.com> References: <20260207-sm8550-ddr-bw-scaling-v1-0-d96c3f39ac4b@gmail.com> In-Reply-To: <20260207-sm8550-ddr-bw-scaling-v1-0-d96c3f39ac4b@gmail.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Aaron Kling X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1770514088; l=956; i=webgeek1234@gmail.com; s=20250217; h=from:subject:message-id; bh=XLpCHDBhLPaFbTEErN+K9hodJ6I3TDiSUik5mhlq4gc=; b=hDm6iEfmbjE/Ey+PgCqp5Pr5LLkQ5R6ckGJcNJN/W59aexXZN3Sr+ssfZFSyZAC1statRIGOI n8hzKB6+0n6Dbrs0+03PdQ9zlBOxRSR8a7GXSYpr+UDz80DCXIwCmmb X-Developer-Key: i=webgeek1234@gmail.com; a=ed25519; pk=TQwd6q26txw7bkK7B8qtI/kcAohZc7bHHGSD7domdrU= X-Endpoint-Received: by B4 Relay for webgeek1234@gmail.com/20250217 with auth_id=342 X-Original-From: Aaron Kling Reply-To: webgeek1234@gmail.com From: Aaron Kling Add the OSC L3 Cache controller node. Signed-off-by: Aaron Kling --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qco= m/sm8550.dtsi index e3f93f4f412ded9583a6bc9215185a0daf5f1b57..80fc437c9874fd5009ff1eaf422= 7b75bec5fe883 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -5437,6 +5437,16 @@ rpmhpd_opp_turbo_l1: opp-416 { }; }; =20 + epss_l3: interconnect@17d90000 { + compatible =3D "qcom,sm8650-epss-l3", "qcom,epss-l3"; + reg =3D <0 0x17d90000 0 0x1000>; + + clocks =3D <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; + clock-names =3D "xo", "alternate"; + + #interconnect-cells =3D <1>; + }; + cpufreq_hw: cpufreq@17d91000 { compatible =3D "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss"; reg =3D <0 0x17d91000 0 0x1000>, --=20 2.52.0 From nobody Mon Feb 9 07:06:22 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E9D6A3002D6; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260207-sm8550-ddr-bw-scaling-v1-2-d96c3f39ac4b@gmail.com> References: <20260207-sm8550-ddr-bw-scaling-v1-0-d96c3f39ac4b@gmail.com> In-Reply-To: <20260207-sm8550-ddr-bw-scaling-v1-0-d96c3f39ac4b@gmail.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Aaron Kling X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1770514088; l=5398; i=webgeek1234@gmail.com; s=20250217; h=from:subject:message-id; bh=2DQFTqocYnlEtQ1A9h8gp6SzPLa2G4b3jlSjbKTlVq8=; b=K8foaZe+2eHgZ7Jv9v4DfdTTdqrhjqQC6sxUTMlTF0naEhY92nbG6rWm7B9RcJ5KKWq55njIO zRXor+moOopAntrPlO6lGUWkojTcwLls0Wup3jNDq1mbVidsPZwWrIK X-Developer-Key: i=webgeek1234@gmail.com; a=ed25519; pk=TQwd6q26txw7bkK7B8qtI/kcAohZc7bHHGSD7domdrU= X-Endpoint-Received: by B4 Relay for webgeek1234@gmail.com/20250217 with auth_id=342 X-Original-From: Aaron Kling Reply-To: webgeek1234@gmail.com From: Aaron Kling Add the interconnect entry for each cpu, with 3 different paths: - CPU to Last Level Cache Controller (LLCC) - Last Level Cache Controller (LLCC) to DDR - L3 Cache from CPU to DDR interface Signed-off-by: Aaron Kling --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 49 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qco= m/sm8550.dtsi index 80fc437c9874fd5009ff1eaf4227b75bec5fe883..ff479684144a2b3ebf6312e3ba4= ff0be88fe1803 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -78,6 +79,12 @@ cpu0: cpu@0 { qcom,freq-domain =3D <&cpufreq_hw 0>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells =3D <2>; l2_0: l2-cache { compatible =3D "cache"; @@ -104,6 +111,12 @@ cpu1: cpu@100 { qcom,freq-domain =3D <&cpufreq_hw 0>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells =3D <2>; l2_100: l2-cache { compatible =3D "cache"; @@ -125,6 +138,12 @@ cpu2: cpu@200 { qcom,freq-domain =3D <&cpufreq_hw 0>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells =3D <2>; l2_200: l2-cache { compatible =3D "cache"; @@ -146,6 +165,12 @@ cpu3: cpu@300 { qcom,freq-domain =3D <&cpufreq_hw 1>; capacity-dmips-mhz =3D <1792>; dynamic-power-coefficient =3D <270>; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells =3D <2>; l2_300: l2-cache { compatible =3D "cache"; @@ -167,6 +192,12 @@ cpu4: cpu@400 { qcom,freq-domain =3D <&cpufreq_hw 1>; capacity-dmips-mhz =3D <1792>; dynamic-power-coefficient =3D <270>; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells =3D <2>; l2_400: l2-cache { compatible =3D "cache"; @@ -188,6 +219,12 @@ cpu5: cpu@500 { qcom,freq-domain =3D <&cpufreq_hw 1>; capacity-dmips-mhz =3D <1792>; dynamic-power-coefficient =3D <270>; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells =3D <2>; l2_500: l2-cache { compatible =3D "cache"; @@ -209,6 +246,12 @@ cpu6: cpu@600 { qcom,freq-domain =3D <&cpufreq_hw 1>; capacity-dmips-mhz =3D <1792>; dynamic-power-coefficient =3D <270>; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260207-sm8550-ddr-bw-scaling-v1-3-d96c3f39ac4b@gmail.com> References: <20260207-sm8550-ddr-bw-scaling-v1-0-d96c3f39ac4b@gmail.com> In-Reply-To: <20260207-sm8550-ddr-bw-scaling-v1-0-d96c3f39ac4b@gmail.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Aaron Kling X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1770514088; l=12258; i=webgeek1234@gmail.com; s=20250217; h=from:subject:message-id; bh=YYEbyK7Wf/XKdHV5+E334eDw5gUBCSBvgXLFRmyj8GI=; b=iC7Ti0H+7Cn1d20sD8uB8qprR26I4qPaAIH78mYMubYTB+JPJ/J7gNOjJbTMgjc1Qv/xXVhYm 63k8vX+wbDSDKXLI52W34/zUoCd9r6VyFI27jEH0G4UiaheRoNwdO2+ X-Developer-Key: i=webgeek1234@gmail.com; a=ed25519; pk=TQwd6q26txw7bkK7B8qtI/kcAohZc7bHHGSD7domdrU= X-Endpoint-Received: by B4 Relay for webgeek1234@gmail.com/20250217 with auth_id=342 X-Original-From: Aaron Kling Reply-To: webgeek1234@gmail.com From: Aaron Kling Add the OPP tables for each CPU clusters (cpu0-1-2, cpu3-4-5-6 & cpu7) to permit scaling the Last Level Cache Controller (LLCC), DDR and L3 cache frequency by aggregating bandwidth requests of all CPU core with referenc to the current OPP they are configured in by the LMH/EPSS hardware. The effect is a proper caches & DDR frequency scaling when CPU cores changes frequency. The OPP tables were built using the downstream memlat ddr, llcc & l3 tables for each cluster types with the actual EPSS cpufreq LUT tables from running a QCS8550 device. Signed-off-by: Aaron Kling --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 308 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 308 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qco= m/sm8550.dtsi index ff479684144a2b3ebf6312e3ba4ff0be88fe1803..658ef48e978bc9ed73060dc865e= 393abd8d1fd4d 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -79,6 +79,7 @@ cpu0: cpu@0 { qcom,freq-domain =3D <&cpufreq_hw 0>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; + operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY @@ -111,6 +112,7 @@ cpu1: cpu@100 { qcom,freq-domain =3D <&cpufreq_hw 0>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; + operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY @@ -138,6 +140,7 @@ cpu2: cpu@200 { qcom,freq-domain =3D <&cpufreq_hw 0>; capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; + operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY @@ -165,6 +168,7 @@ cpu3: cpu@300 { qcom,freq-domain =3D <&cpufreq_hw 1>; capacity-dmips-mhz =3D <1792>; dynamic-power-coefficient =3D <270>; + operating-points-v2 =3D <&cpu3_opp_table>; interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY @@ -192,6 +196,7 @@ cpu4: cpu@400 { qcom,freq-domain =3D <&cpufreq_hw 1>; capacity-dmips-mhz =3D <1792>; dynamic-power-coefficient =3D <270>; + operating-points-v2 =3D <&cpu3_opp_table>; interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY @@ -219,6 +224,7 @@ cpu5: cpu@500 { qcom,freq-domain =3D <&cpufreq_hw 1>; capacity-dmips-mhz =3D <1792>; dynamic-power-coefficient =3D <270>; + operating-points-v2 =3D <&cpu3_opp_table>; interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY @@ -246,6 +252,7 @@ cpu6: cpu@600 { qcom,freq-domain =3D <&cpufreq_hw 1>; capacity-dmips-mhz =3D <1792>; dynamic-power-coefficient =3D <270>; + operating-points-v2 =3D <&cpu3_opp_table>; interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY @@ -273,6 +280,7 @@ cpu7: cpu@700 { qcom,freq-domain =3D <&cpufreq_hw 2>; capacity-dmips-mhz =3D <1894>; dynamic-power-coefficient =3D <588>; + operating-points-v2 =3D <&cpu7_opp_table>; interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY @@ -446,6 +454,306 @@ memory@a0000000 { reg =3D <0 0xa0000000 0 0>; }; =20 + cpu0_opp_table: opp-table-cpu0 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-307200000 { + opp-hz =3D /bits/ 64 <307200000>; + opp-peak-kBps =3D <(300000 * 16) (547000 * 4) (307200 * 32)>; + }; + + opp-441600000 { + opp-hz =3D /bits/ 64 <441600000>; + opp-peak-kBps =3D <(300000 * 16) (547000 * 4) (384000 * 32)>; + }; + + opp-556800000 { + opp-hz =3D /bits/ 64 <556800000>; + opp-peak-kBps =3D <(300000 * 16) (547000 * 4) (499200 * 32)>; + }; + + opp-672000000 { + opp-hz =3D /bits/ 64 <672000000>; + opp-peak-kBps =3D <(300000 * 16) (547000 * 4) (729600 * 32)>; + }; + + opp-787200000 { + opp-hz =3D /bits/ 64 <787200000>; + opp-peak-kBps =3D <(300000 * 16) (547000 * 4) (729600 * 32)>; + }; + + opp-902400000 { + opp-hz =3D /bits/ 64 <902400000>; + opp-peak-kBps =3D <(300000 * 16) (547000 * 4) (844800 * 32)>; + }; + + opp-1017600000 { + opp-hz =3D /bits/ 64 <1017600000>; + opp-peak-kBps =3D <(466000 * 16) (547000 * 4) (940800 * 32)>; + }; + + opp-1113600000 { + opp-hz =3D /bits/ 64 <1113600000>; + opp-peak-kBps =3D <(466000 * 16) (547000 * 4) (1056000 * 32)>; + }; + + opp-1228800000 { + opp-hz =3D /bits/ 64 <1228800000>; + opp-peak-kBps =3D <(466000 * 16) (768000 * 4) (1152000 * 32)>; + }; + + opp-1344000000 { + opp-hz =3D /bits/ 64 <1344000000>; + opp-peak-kBps =3D <(466000 * 16) (768000 * 4) (1267200 * 32)>; + }; + + opp-1459200000 { + opp-hz =3D /bits/ 64 <1459200000>; + opp-peak-kBps =3D <(466000 * 16) (768000 * 4) (1478400 * 32)>; + }; + + opp-1555200000 { + opp-hz =3D /bits/ 64 <1555200000>; + opp-peak-kBps =3D <(466000 * 16) (768000 * 4) (1478400 * 32)>; + }; + + opp-1670400000 { + opp-hz =3D /bits/ 64 <1670400000>; + opp-peak-kBps =3D <(600000 * 16) (1555000 * 4) (1689600 * 32)>; + }; + + opp-1785600000 { + opp-hz =3D /bits/ 64 <1785600000>; + opp-peak-kBps =3D <(600000 * 16) (1555000 * 4) (1689600 * 32)>; + }; + + opp-1900800000 { + opp-hz =3D /bits/ 64 <1900800000>; + opp-peak-kBps =3D <(600000 * 16) (1555000 * 4) (1689600 * 32)>; + }; + + opp-2016000000 { + opp-hz =3D /bits/ 64 <2016000000>; + opp-peak-kBps =3D <(600000 * 16) (1555000 * 4) (1804800 * 32)>; + }; + }; + + cpu3_opp_table: opp-table-cpu3 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-499200000 { + opp-hz =3D /bits/ 64 <499200000>; + opp-peak-kBps =3D <(300000 * 16) (547000 * 4) (307200 * 32)>; + }; + + opp-614400000 { + opp-hz =3D /bits/ 64 <614400000>; + opp-peak-kBps =3D <(300000 * 16) (547000 * 4) (499200 * 32)>; + }; + + opp-729600000 { + opp-hz =3D /bits/ 64 <729600000>; + opp-peak-kBps =3D <(466000 * 16) (768000 * 4) (729600 * 32)>; + }; + + opp-844800000 { + opp-hz =3D /bits/ 64 <844800000>; + opp-peak-kBps =3D <(466000 * 16) (768000 * 4) (729600 * 32)>; + }; + + opp-940800000 { + opp-hz =3D /bits/ 64 <940800000>; + opp-peak-kBps =3D <(466000 * 16) (768000 * 4) (729600 * 32)>; + }; + + opp-1056000000 { + opp-hz =3D /bits/ 64 <1056000000>; + opp-peak-kBps =3D <(466000 * 16) (1555000 * 4) (940800 * 32)>; + }; + + opp-1171200000 { + opp-hz =3D /bits/ 64 <1171200000>; + opp-peak-kBps =3D <(466000 * 16) (1555000 * 4) (940800 * 32)>; + }; + + opp-1286400000 { + opp-hz =3D /bits/ 64 <1286400000>; + opp-peak-kBps =3D <(600000 * 16) (1708000 * 4) (1056000 * 32)>; + }; + + opp-1401600000 { + opp-hz =3D /bits/ 64 <1401600000>; + opp-peak-kBps =3D <(600000 * 16) (1708000 * 4) (1056000 * 32)>; + }; + + opp-1536000000 { + opp-hz =3D /bits/ 64 <1536000000>; + opp-peak-kBps =3D <(806000 * 16) (2736000 * 4) (1267200 * 32)>; + }; + + opp-1651200000 { + opp-hz =3D /bits/ 64 <1651200000>; + opp-peak-kBps =3D <(806000 * 16) (2736000 * 4) (1267200 * 32)>; + }; + + opp-1785600000 { + opp-hz =3D /bits/ 64 <1785600000>; + opp-peak-kBps =3D <(806000 * 16) (2736000 * 4) (1478400 * 32)>; + }; + + opp-1920000000 { + opp-hz =3D /bits/ 64 <1920000000>; + opp-peak-kBps =3D <(806000 * 16) (2736000 * 4) (1478400 * 32)>; + }; + + opp-2054400000 { + opp-hz =3D /bits/ 64 <2054400000>; + opp-peak-kBps =3D <(933000 * 16) (3686000 * 4) (1478400 * 32)>; + }; + + opp-2188800000 { + opp-hz =3D /bits/ 64 <2188800000>; + opp-peak-kBps =3D <(933000 * 16) (3686000 * 4) (1689600 * 32)>; + }; + + opp-2323200000 { + opp-hz =3D /bits/ 64 <2323200000>; + opp-peak-kBps =3D <(933000 * 16) (3686000 * 4) (1689600 * 32)>; + }; + + opp-2457600000 { + opp-hz =3D /bits/ 64 <2457600000>; + opp-peak-kBps =3D <(933000 * 16) (3686000 * 4) (1689600 * 32)>; + }; + + opp-2592000000 { + opp-hz =3D /bits/ 64 <2592000000>; + opp-peak-kBps =3D <(933000 * 16) (3686000 * 4) (1689600 * 32)>; + }; + + opp-2707200000 { + opp-hz =3D /bits/ 64 <2707200000>; + opp-peak-kBps =3D <(933000 * 16) (3686000 * 4) (1689600 * 32)>; + }; + + opp-2803200000 { + opp-hz =3D /bits/ 64 <2803200000>; + opp-peak-kBps =3D <(1066000 * 16) (4224000 * 4) (1689600 * 32)>; + }; + }; + + cpu7_opp_table: opp-table-cpu7 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-595200000 { + opp-hz =3D /bits/ 64 <595200000>; + opp-peak-kBps =3D <(300000 * 16) (547000 * 4) (307200 * 32)>; + }; + + opp-729600000 { + opp-hz =3D /bits/ 64 <729600000>; + opp-peak-kBps =3D <(466000 * 16) (768000 * 4) (729600 * 32)>; + }; + + opp-864000000 { + opp-hz =3D /bits/ 64 <864000000>; + opp-peak-kBps =3D <(466000 * 16) (768000 * 4) (729600 * 32)>; + }; + + opp-998400000 { + opp-hz =3D /bits/ 64 <998400000>; + opp-peak-kBps =3D <(466000 * 16) (1555000 * 4) (940800 * 32)>; + }; + + opp-1132800000 { + opp-hz =3D /bits/ 64 <1132800000>; + opp-peak-kBps =3D <(466000 * 16) (1555000 * 4) (940800 * 32)>; + }; + + opp-1248000000 { + opp-hz =3D /bits/ 64 <1248000000>; + opp-peak-kBps =3D <(600000 * 16) (1708000 * 4) (1056000 * 32)>; + }; + + opp-1363200000 { + opp-hz =3D /bits/ 64 <1363200000>; + opp-peak-kBps =3D <(600000 * 16) (1708000 * 4) (1056000 * 32)>; + }; + + opp-1478400000 { + opp-hz =3D /bits/ 64 <1478400000>; + opp-peak-kBps =3D <(806000 * 16) (2736000 * 4) (1267200 * 32)>; + }; + + opp-1593600000 { + opp-hz =3D /bits/ 64 <1593600000>; + opp-peak-kBps =3D <(806000 * 16) (2736000 * 4) (1267200 * 32)>; + }; + + opp-1708800000 { + opp-hz =3D /bits/ 64 <1708800000>; + opp-peak-kBps =3D <(806000 * 16) (2736000 * 4) (1478400 * 32)>; + }; + + opp-1843200000 { + opp-hz =3D /bits/ 64 <1843200000>; + opp-peak-kBps =3D <(806000 * 16) (2736000 * 4) (1478400 * 32)>; + }; + + opp-1977600000 { + opp-hz =3D /bits/ 64 <1977600000>; + opp-peak-kBps =3D <(806000 * 16) (3686000 * 4) (1478400 * 32)>; + }; + + opp-2092800000 { + opp-hz =3D /bits/ 64 <2092800000>; + opp-peak-kBps =3D <(933000 * 16) (3686000 * 4) (1689600 * 32)>; + }; + + opp-2227200000 { + opp-hz =3D /bits/ 64 <2227200000>; + opp-peak-kBps =3D <(933000 * 16) (3686000 * 4) (1689600 * 32)>; + }; + + opp-2342400000 { + opp-hz =3D /bits/ 64 <2342400000>; + opp-peak-kBps =3D <(933000 * 16) (3686000 * 4) (1689600 * 32)>; + }; + + opp-2476800000 { + opp-hz =3D /bits/ 64 <2476800000>; + opp-peak-kBps =3D <(933000 * 16) (3686000 * 4) (1689600 * 32)>; + }; + + opp-2592000000 { + opp-hz =3D /bits/ 64 <2592000000>; + opp-peak-kBps =3D <(933000 * 16) (3686000 * 4) (1689600 * 32)>; + }; + + opp-2726400000 { + opp-hz =3D /bits/ 64 <2726400000>; + opp-peak-kBps =3D <(933000 * 16) (3686000 * 4) (1689600 * 32)>; + }; + + opp-2841600000 { + opp-hz =3D /bits/ 64 <2841600000>; + opp-peak-kBps =3D <(1066000 * 16) (4224000 * 4) (1804800 * 32)>; + }; + + opp-2956800000 { + opp-hz =3D /bits/ 64 <2956800000>; + opp-peak-kBps =3D <(1066000 * 16) (4224000 * 4) (1804800 * 32)>; + }; + + opp-3187200000 { + opp-hz =3D /bits/ 64 <3187200000>; + opp-peak-kBps =3D <(1066000 * 16) (4224000 * 4) (1804800 * 32)>; + }; + }; + pmu-a510 { compatible =3D "arm,cortex-a510-pmu"; interrupts =3D ; --=20 2.52.0