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Sat, 07 Feb 2026 02:28:38 -0800 (PST) From: Guodong Xu Date: Sat, 07 Feb 2026 18:28:01 +0800 Subject: [PATCH 7/8] riscv: cpufeature: Add parsing for Ssccptr, Sscounterenw, Sstvala, Sstvecd, and Ssu64xl Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260207-isa-ext-parse-export-v1-7-a64d3a8bc20a@riscstar.com> References: <20260207-isa-ext-parse-export-v1-0-a64d3a8bc20a@riscstar.com> In-Reply-To: <20260207-isa-ext-parse-export-v1-0-a64d3a8bc20a@riscstar.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Jonathan Corbet , Shuah Khan , Conor Dooley Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Guodong Xu X-Mailer: b4 0.14.2 Add ISA extension parsing for five supervisor-level extensions ratified in RISC-V Profiles Version 1.0: - Ssccptr: main memory hardware page-table reads - Sscounterenw: writable enables in scounteren for any supported counter - Sstvala: stval provides all needed values - Sstvecd: stvec supports Direct mode - Ssu64xl: UXLEN=3D64 must be supported These are simple extensions with no dependencies. All of them are labeled as mandatory in RVA23 Profile 1.0. Signed-off-by: Guodong Xu --- arch/riscv/include/asm/hwcap.h | 5 +++++ arch/riscv/kernel/cpufeature.c | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 5a050fae5302c7717596799967d8d514e7dfc536..75f64f5b7355db6ea5218f544ce= da3be9619a58a 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -118,6 +118,11 @@ #define RISCV_ISA_EXT_ZICCAMOA 108 #define RISCV_ISA_EXT_ZICCIF 109 #define RISCV_ISA_EXT_ZICCLSM 110 +#define RISCV_ISA_EXT_SSCCPTR 111 +#define RISCV_ISA_EXT_SSCOUNTERENW 112 +#define RISCV_ISA_EXT_SSTVALA 113 +#define RISCV_ISA_EXT_SSTVECD 114 +#define RISCV_ISA_EXT_SSU64XL 115 =20 #define RISCV_ISA_EXT_XLINUXENVCFG 127 =20 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index fee5b20bb171334e8ca60af25485f43a9acef619..fff35a3e85db70f5610df2667f2= b4f45f091cb2b 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -643,9 +643,14 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_SUPERSET(smnpm, RISCV_ISA_EXT_SMNPM, riscv_supm_exts), __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN), __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), + __RISCV_ISA_EXT_DATA(ssccptr, RISCV_ISA_EXT_SSCCPTR), __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), + __RISCV_ISA_EXT_DATA(sscounterenw, RISCV_ISA_EXT_SSCOUNTERENW), __RISCV_ISA_EXT_SUPERSET(ssnpm, RISCV_ISA_EXT_SSNPM, riscv_supm_exts), __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), + __RISCV_ISA_EXT_DATA(sstvala, RISCV_ISA_EXT_SSTVALA), + __RISCV_ISA_EXT_DATA(sstvecd, RISCV_ISA_EXT_SSTVECD), + __RISCV_ISA_EXT_DATA(ssu64xl, RISCV_ISA_EXT_SSU64XL), __RISCV_ISA_EXT_DATA_VALIDATE(supm, RISCV_ISA_EXT_SUPM, riscv_ext_supm_va= lidate), __RISCV_ISA_EXT_DATA(svade, RISCV_ISA_EXT_SVADE), __RISCV_ISA_EXT_DATA_VALIDATE(svadu, RISCV_ISA_EXT_SVADU, riscv_ext_svadu= _validate), --=20 2.43.0