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Sat, 07 Feb 2026 02:28:34 -0800 (PST) From: Guodong Xu Date: Sat, 07 Feb 2026 18:28:00 +0800 Subject: [PATCH 6/8] riscv: hwprobe: Add support for probing Ziccif Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260207-isa-ext-parse-export-v1-6-a64d3a8bc20a@riscstar.com> References: <20260207-isa-ext-parse-export-v1-0-a64d3a8bc20a@riscstar.com> In-Reply-To: <20260207-isa-ext-parse-export-v1-0-a64d3a8bc20a@riscstar.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Jonathan Corbet , Shuah Khan , Conor Dooley Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Guodong Xu X-Mailer: b4 0.14.2 Ziccif guarantees that instruction fetches from main memory regions with cacheability and coherence PMAs are atomic for naturally aligned power-of-2 sizes up to min(ILEN,XLEN). This is a mandatory extension in the RVA23U64 user-mode profile (and has been since RVA20U64). Exposing Ziccif through hwprobe allows userspace performing concurrent code modification (CMODX) to confirm the underlying hardware guarantees atomic instruction fetches for naturally aligned instructions. Previous communitiy discussion exists [1]. Link: https://lore.kernel.org/all/20250407180838.42877-12-andybnac@gmail.co= m/ [1] Signed-off-by: Guodong Xu --- Documentation/arch/riscv/hwprobe.rst | 3 +++ arch/riscv/include/uapi/asm/hwprobe.h | 1 + arch/riscv/kernel/sys_hwprobe.c | 1 + 3 files changed, 5 insertions(+) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/risc= v/hwprobe.rst index 198b31bc9a20c2739988849cf7d2948a4fe1bdc4..89ff3d4e9f299de2b7d14b7ed77= a04409f821621 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -399,3 +399,6 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_EXT_ZICCLSM`: The Zicclsm extension for main memory that must support misaligned loads and stores, as ratified in RISC-V Profiles Version 1.0. + + * :c:macro:`RISCV_HWPROBE_EXT_ZICCIF`: The Ziccif extension for main mem= ory + instruction fetch atomicity, as ratified in RISC-V Profiles Version 1.= 0. diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uap= i/asm/hwprobe.h index 323c488de5548883ddceac256bf312ec854ee899..ebf1434f54e6dc640b3414e8a23= ab8e29ab243e4 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -118,6 +118,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZICFISS (1ULL << 0) #define RISCV_HWPROBE_IMA_B (1ULL << 1) #define RISCV_HWPROBE_EXT_ZICCLSM (1ULL << 2) +#define RISCV_HWPROBE_EXT_ZICCIF (1ULL << 3) =20 /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ =20 diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprob= e.c index 6997c6007a8e86dff85b5b83d14924e7c2466eb2..8d774a0be9110c997a200c4eeeb= 434e8afd5c7f9 100644 --- a/arch/riscv/kernel/sys_hwprobe.c +++ b/arch/riscv/kernel/sys_hwprobe.c @@ -209,6 +209,7 @@ static void hwprobe_isa_ext1(struct riscv_hwprobe *pair, */ EXT_KEY(isainfo->isa, ZICFISS, pair->value, missing); EXT_KEY(isainfo->isa, ZICCLSM, pair->value, missing); + EXT_KEY(isainfo->isa, ZICCIF, pair->value, missing); } =20 /* Now turn off reporting features if any CPU is missing it. */ --=20 2.43.0