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Sat, 07 Feb 2026 02:28:30 -0800 (PST) From: Guodong Xu Date: Sat, 07 Feb 2026 18:27:59 +0800 Subject: [PATCH 5/8] riscv: hwprobe: Add support for probing Zicclsm Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260207-isa-ext-parse-export-v1-5-a64d3a8bc20a@riscstar.com> References: <20260207-isa-ext-parse-export-v1-0-a64d3a8bc20a@riscstar.com> In-Reply-To: <20260207-isa-ext-parse-export-v1-0-a64d3a8bc20a@riscstar.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Jonathan Corbet , Shuah Khan , Conor Dooley Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Guodong Xu X-Mailer: b4 0.14.2 Zicclsm guarantees that misaligned loads and stores to main memory regions are supported. This is a mandatory extension in the RVA23U64 user-mode profile. Export Zicclsm through hwprobe to help userspace check the existence of this capability. "Misaligned vector accesses are only supported if Zicclsm extension is supported", as clarified in: commit 982a7eb97be6 ("Documentation: RISC-V: uabi: Only scalar misaligned loads are supported") Link: https://lore.kernel.org/all/20240524185600.5919-1-palmer@rivosinc.com/ Link: https://lore.kernel.org/all/20240524-ruckus-trickily-1cda26c1a455@spu= d/ Signed-off-by: Guodong Xu --- Documentation/arch/riscv/hwprobe.rst | 4 ++++ arch/riscv/include/uapi/asm/hwprobe.h | 1 + arch/riscv/kernel/sys_hwprobe.c | 1 + 3 files changed, 6 insertions(+) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/risc= v/hwprobe.rst index 8430bc94fdba073e1e3ded973322c773c598a0b5..198b31bc9a20c2739988849cf7d= 2948a4fe1bdc4 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -395,3 +395,7 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_IMA_B`: The B extension is supported, as defin= ed by version 20240411 of the RISC-V Instruction Set Manual, Volume I Unprivileged Architecture. + + * :c:macro:`RISCV_HWPROBE_EXT_ZICCLSM`: The Zicclsm extension for main + memory that must support misaligned loads and stores, as ratified in + RISC-V Profiles Version 1.0. diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uap= i/asm/hwprobe.h index e7bd2e9ea33459572d01495f4063e32e3207e48f..323c488de5548883ddceac256bf= 312ec854ee899 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -117,6 +117,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_KEY_IMA_EXT_1 16 #define RISCV_HWPROBE_EXT_ZICFISS (1ULL << 0) #define RISCV_HWPROBE_IMA_B (1ULL << 1) +#define RISCV_HWPROBE_EXT_ZICCLSM (1ULL << 2) =20 /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ =20 diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprob= e.c index 491af3c5b66a0cb30471dafc8b31c70df2f9bed1..6997c6007a8e86dff85b5b83d14= 924e7c2466eb2 100644 --- a/arch/riscv/kernel/sys_hwprobe.c +++ b/arch/riscv/kernel/sys_hwprobe.c @@ -208,6 +208,7 @@ static void hwprobe_isa_ext1(struct riscv_hwprobe *pair, * in the hart_isa bitmap, are made. */ EXT_KEY(isainfo->isa, ZICFISS, pair->value, missing); + EXT_KEY(isainfo->isa, ZICCLSM, pair->value, missing); } =20 /* Now turn off reporting features if any CPU is missing it. */ --=20 2.43.0