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Sat, 07 Feb 2026 02:28:26 -0800 (PST) From: Guodong Xu Date: Sat, 07 Feb 2026 18:27:58 +0800 Subject: [PATCH 4/8] riscv: cpufeature: Add parsing for Za64rs, Ziccamoa, Ziccif, and Zicclsm Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260207-isa-ext-parse-export-v1-4-a64d3a8bc20a@riscstar.com> References: <20260207-isa-ext-parse-export-v1-0-a64d3a8bc20a@riscstar.com> In-Reply-To: <20260207-isa-ext-parse-export-v1-0-a64d3a8bc20a@riscstar.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Jonathan Corbet , Shuah Khan , Conor Dooley Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Guodong Xu X-Mailer: b4 0.14.2 Add ISA extension parsing for four memory system related extensions: - Za64rs: reservation set size of at most 64 bytes - Ziccamoa: main memory must support all atomics in A - Ziccif: main memory instruction fetch atomicity - Zicclsm: main memory must support misaligned loads and stores Za64rs depends on Zalrsc (or the A extension, which implies Zalrsc). Ziccamoa depends on Zaamo (or the A extension, which implies Zaamo). Both use dependency callbacks to enforce these requirements. All of them are labeled as mandatory in RVA23 Profile 1.0. Signed-off-by: Guodong Xu --- arch/riscv/include/asm/hwcap.h | 4 ++++ arch/riscv/kernel/cpufeature.c | 13 +++++++++++++ 2 files changed, 17 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 35e87e4a8475a9201e84e7f9f8a4d10dfd9e4759..5a050fae5302c7717596799967d= 8d514e7dfc536 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -114,6 +114,10 @@ #define RISCV_ISA_EXT_ZICFILP 104 #define RISCV_ISA_EXT_ZICFISS 105 #define RISCV_ISA_EXT_SUPM 106 +#define RISCV_ISA_EXT_ZA64RS 107 +#define RISCV_ISA_EXT_ZICCAMOA 108 +#define RISCV_ISA_EXT_ZICCIF 109 +#define RISCV_ISA_EXT_ZICCLSM 110 =20 #define RISCV_ISA_EXT_XLINUXENVCFG 127 =20 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 68c94fe29cd1b26925fa38a5c877d699bbc88e25..fee5b20bb171334e8ca60af2548= 5f43a9acef619 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -347,6 +347,15 @@ static int riscv_ext_zalrsc_depends(const struct riscv= _isa_ext_data *data, return -EPROBE_DEFER; } =20 +static int riscv_ext_zaamo_depends(const struct riscv_isa_ext_data *data, + const unsigned long *isa_bitmap) +{ + if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZAAMO)) + return 0; + + return -EPROBE_DEFER; +} + static const unsigned int riscv_a_exts[] =3D { RISCV_ISA_EXT_ZAAMO, RISCV_ISA_EXT_ZALRSC, @@ -552,6 +561,9 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xli= nuxenvcfg_exts, riscv_ext_zicbom_validate), __RISCV_ISA_EXT_DATA_VALIDATE(zicbop, RISCV_ISA_EXT_ZICBOP, riscv_ext_zic= bop_validate), __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xli= nuxenvcfg_exts, riscv_ext_zicboz_validate), + __RISCV_ISA_EXT_DATA_VALIDATE(ziccamoa, RISCV_ISA_EXT_ZICCAMOA, riscv_ext= _zaamo_depends), + __RISCV_ISA_EXT_DATA(ziccif, RISCV_ISA_EXT_ZICCIF), + __RISCV_ISA_EXT_DATA(zicclsm, RISCV_ISA_EXT_ZICCLSM), __RISCV_ISA_EXT_DATA_VALIDATE(ziccrse, RISCV_ISA_EXT_ZICCRSE, riscv_ext_z= alrsc_depends), __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicfilp, RISCV_ISA_EXT_ZICFILP, riscv_x= linuxenvcfg_exts, riscv_cfilp_validate), @@ -565,6 +577,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM), __RISCV_ISA_EXT_DATA(zimop, RISCV_ISA_EXT_ZIMOP), + __RISCV_ISA_EXT_DATA_VALIDATE(za64rs, RISCV_ISA_EXT_ZA64RS, riscv_ext_zal= rsc_depends), __RISCV_ISA_EXT_DATA(zaamo, RISCV_ISA_EXT_ZAAMO), __RISCV_ISA_EXT_DATA(zabha, RISCV_ISA_EXT_ZABHA), __RISCV_ISA_EXT_DATA(zacas, RISCV_ISA_EXT_ZACAS), --=20 2.43.0