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Sat, 07 Feb 2026 02:28:18 -0800 (PST) From: Guodong Xu Date: Sat, 07 Feb 2026 18:27:56 +0800 Subject: [PATCH 2/8] riscv: hwprobe: Add support for probing B Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260207-isa-ext-parse-export-v1-2-a64d3a8bc20a@riscstar.com> References: <20260207-isa-ext-parse-export-v1-0-a64d3a8bc20a@riscstar.com> In-Reply-To: <20260207-isa-ext-parse-export-v1-0-a64d3a8bc20a@riscstar.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Jonathan Corbet , Shuah Khan , Conor Dooley Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Guodong Xu X-Mailer: b4 0.14.2 The B extension is a shorthand for the Zba, Zbb, and Zbs extensions combined, as defined by version 20240411 of the RISC-V Instruction Set Manual Volume I Unprivileged Architecture. The B bit is added as a system-wide check in RISCV_HWPROBE_KEY_IMA_EXT_1 using the global ISA bitmap. It should be noted that the kernel already exports Zba, Zbb, and Zbs individually in RISCV_HWPROBE_KEY_IMA_EXT_0 with per-CPU granularity. Signed-off-by: Guodong Xu --- Documentation/arch/riscv/hwprobe.rst | 4 ++++ arch/riscv/include/uapi/asm/hwprobe.h | 1 + arch/riscv/kernel/sys_hwprobe.c | 3 +++ 3 files changed, 8 insertions(+) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/risc= v/hwprobe.rst index c420a8349bc6811573051154bc9c64617f3d7464..8430bc94fdba073e1e3ded97332= 2c773c598a0b5 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -391,3 +391,7 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_KEY_IMA_EXT_1`: A bitmask containing additional extensions that are compatible with the :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior. + + * :c:macro:`RISCV_HWPROBE_IMA_B`: The B extension is supported, as defin= ed + by version 20240411 of the RISC-V Instruction Set Manual, Volume I + Unprivileged Architecture. diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uap= i/asm/hwprobe.h index 9139edba0aecbf466098ace486658aaeeb6667e3..e7bd2e9ea33459572d01495f406= 3e32e3207e48f 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -116,6 +116,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE 15 #define RISCV_HWPROBE_KEY_IMA_EXT_1 16 #define RISCV_HWPROBE_EXT_ZICFISS (1ULL << 0) +#define RISCV_HWPROBE_IMA_B (1ULL << 1) =20 /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ =20 diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprob= e.c index 1659d31fd288fc296d711c111e8d1a2e2fc8026a..491af3c5b66a0cb30471dafc8b3= 1c70df2f9bed1 100644 --- a/arch/riscv/kernel/sys_hwprobe.c +++ b/arch/riscv/kernel/sys_hwprobe.c @@ -191,6 +191,9 @@ static void hwprobe_isa_ext1(struct riscv_hwprobe *pair, =20 pair->value =3D 0; =20 + if (riscv_isa_extension_available(NULL, b)) + pair->value |=3D RISCV_HWPROBE_IMA_B; + /* * Loop through and record extensions that 1) anyone has, and 2) anyone * doesn't have. --=20 2.43.0