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Fri, 06 Feb 2026 03:17:05 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Thomas Gleixner Cc: Biju Das , linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v3 8/9] irqchip/renesas-rzg2l: Add shared irq support Date: Fri, 6 Feb 2026 11:16:51 +0000 Message-ID: <20260206111658.231934-9-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260206111658.231934-1-biju.das.jz@bp.renesas.com> References: <20260206111658.231934-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The total number of External IRQs in RZ/G2L and RZ/G3L SoC are different. The RZ/G3L has 16 external IRQs out of which it shares 8 IRQs with TINT, where as RZ/G2L has only 8 external IRQ. Add shared_irq variable in struct rzg2l_hw_info to handle this differences by adding the callback irq_{request,release}_resources(). Signed-off-by: Biju Das --- v2->v3: * No change v1->v2: * No change --- drivers/irqchip/irq-renesas-rzg2l.c | 94 +++++++++++++++++++++++++++++ 1 file changed, 94 insertions(+) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-rene= sas-rzg2l.c index 06c439c98ff5..59108e1d53ec 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -29,6 +29,8 @@ #define TITSR(n) (0x24 + (n) * 4) #define TITSR0_MAX_INT 16 #define TITSEL_WIDTH 0x2 +#define INTTSEL 0x2c +#define TINTSEL(n) BIT(n) #define TSSR(n) (0x30 + ((n) * 4)) #define TIEN BIT(7) #define TSSEL_SHIFT(n) (8 * (n)) @@ -58,10 +60,12 @@ /** * struct rzg2l_irqc_reg_cache - registers cache (necessary for suspend/re= sume) * @iitsr: IITSR register + * @inttsel: INTTSEL register * @titsr: TITSR registers */ struct rzg2l_irqc_reg_cache { u32 iitsr; + u32 inttsel; u32 titsr[2]; }; =20 @@ -71,12 +75,14 @@ struct rzg2l_irqc_reg_cache { * @irq_count: Number of IRQC interrupts * @tint_start: Start of TINT interrupts * @num_irq: Total Number of interrupts + * @shared_irq_cnt: Number of shared interrupts */ struct rzg2l_hw_info { const u8 *tssel_lut; u8 irq_count; u8 tint_start; u8 num_irq; + u8 shared_irq_cnt; }; =20 /** @@ -295,6 +301,87 @@ static void rzg2l_irqc_irq_enable(struct irq_data *d) irq_chip_enable_parent(d); } =20 +static bool rzg2l_irqc_is_shared_irqc(const struct rzg2l_hw_info *info, un= signed int hw_irq) +{ + return ((hw_irq >=3D (info->tint_start - info->shared_irq_cnt)) && + hw_irq < info->tint_start); +} + +static bool rzg2l_irqc_is_shared_tint(const struct rzg2l_hw_info *info, un= signed int hw_irq) +{ + return ((hw_irq >=3D (info->num_irq - info->shared_irq_cnt)) && + hw_irq < info->num_irq); +} + +static int rzg2l_irqc_irq_request_resources(struct irq_data *d) +{ + unsigned int hw_irq =3D irqd_to_hwirq(d); + struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); + const struct rzg2l_hw_info *info =3D priv->info; + u32 offset, tssr_offset; + u8 tssr_index, tssel_shift; + u32 reg, inttsel_reg; + u8 value; + + if (!info->shared_irq_cnt) + return 0; + + if (rzg2l_irqc_is_shared_irqc(info, hw_irq)) { + offset =3D hw_irq + IRQC_TINT_COUNT - info->tint_start; + tssr_offset =3D TSSR_OFFSET(offset); + tssr_index =3D TSSR_INDEX(offset); + tssel_shift =3D TSSEL_SHIFT(tssr_offset); + + reg =3D readl_relaxed(priv->base + TSSR(tssr_index)); + value =3D (reg & (TIEN << tssel_shift)) >> tssel_shift; + if (value) + goto err_conflict; + + raw_spin_lock(&priv->lock); + inttsel_reg =3D readl_relaxed(priv->base + INTTSEL); + inttsel_reg |=3D TINTSEL(offset); + writel_relaxed(inttsel_reg, priv->base + INTTSEL); + raw_spin_unlock(&priv->lock); + } else if (rzg2l_irqc_is_shared_tint(info, hw_irq)) { + offset =3D hw_irq - info->tint_start; + tssr_offset =3D TSSR_OFFSET(offset); + tssr_index =3D TSSR_INDEX(offset); + + inttsel_reg =3D readl_relaxed(priv->base + INTTSEL); + value =3D (inttsel_reg & TINTSEL(offset)) >> offset; + if (value) + goto err_conflict; + } + + return 0; + +err_conflict: + pr_err("%s: Shared SPI conflict!\n", __func__); + return -EBUSY; +} + +static void rzg2l_irqc_irq_release_resources(struct irq_data *d) +{ + unsigned int hw_irq =3D irqd_to_hwirq(d); + struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); + const struct rzg2l_hw_info *info =3D priv->info; + u32 offset; + u8 inttsel_reg; + + if (!priv->info->shared_irq_cnt) + return; + + if (rzg2l_irqc_is_shared_irqc(info, hw_irq)) { + offset =3D hw_irq + IRQC_TINT_COUNT - info->tint_start; + + raw_spin_lock(&priv->lock); + inttsel_reg =3D readl_relaxed(priv->base + INTTSEL); + inttsel_reg &=3D ~TINTSEL(offset); + writel_relaxed(inttsel_reg, priv->base + INTTSEL); + raw_spin_unlock(&priv->lock); + } +} + static int rzg2l_irq_set_type(struct irq_data *d, unsigned int type) { struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); @@ -422,6 +509,8 @@ static int rzg2l_irqc_irq_suspend(void *data) void __iomem *base =3D rzg2l_irqc_data->base; =20 cache->iitsr =3D readl_relaxed(base + IITSR); + if (rzg2l_irqc_data->info->shared_irq_cnt) + cache->inttsel =3D readl_relaxed(base + INTTSEL); for (u8 i =3D 0; i < 2; i++) cache->titsr[i] =3D readl_relaxed(base + TITSR(i)); =20 @@ -440,6 +529,8 @@ static void rzg2l_irqc_irq_resume(void *data) */ for (u8 i =3D 0; i < 2; i++) writel_relaxed(cache->titsr[i], base + TITSR(i)); + if (rzg2l_irqc_data->info->shared_irq_cnt) + writel_relaxed(cache->inttsel, base + INTTSEL); writel_relaxed(cache->iitsr, base + IITSR); } =20 @@ -459,6 +550,8 @@ static const struct irq_chip rzg2l_irqc_chip =3D { .irq_unmask =3D irq_chip_unmask_parent, .irq_disable =3D rzg2l_irqc_irq_disable, .irq_enable =3D rzg2l_irqc_irq_enable, + .irq_request_resources =3D rzg2l_irqc_irq_request_resources, + .irq_release_resources =3D rzg2l_irqc_irq_release_resources, .irq_get_irqchip_state =3D irq_chip_get_parent_state, .irq_set_irqchip_state =3D irq_chip_set_parent_state, .irq_retrigger =3D irq_chip_retrigger_hierarchy, @@ -640,6 +733,7 @@ static const struct rzg2l_hw_info rzg3l_hw_params =3D { .irq_count =3D 16, .tint_start =3D IRQC_IRQ_START + 16, .num_irq =3D IRQC_IRQ_START + 16 + IRQC_TINT_COUNT, + .shared_irq_cnt =3D 8, }; =20 static const struct rzg2l_hw_info rzg2l_hw_params =3D { --=20 2.43.0