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Fri, 06 Feb 2026 03:17:03 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Thomas Gleixner Cc: Biju Das , linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v3 5/9] irqchip/renesas-rzg2l: Drop IRQC_TINT_START macro Date: Fri, 6 Feb 2026 11:16:48 +0000 Message-ID: <20260206111658.231934-6-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260206111658.231934-1-biju.das.jz@bp.renesas.com> References: <20260206111658.231934-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The IRQC_TINT_START value is different for RZ/G3L and RZ/G2L SoC. Add tint_start variable in struct rzg2l_hw_info to handle this differences and drop the macro IRQC_TINT_START. Signed-off-by: Biju Das --- v2->v3: * No change v1->v2: * No change --- drivers/irqchip/irq-renesas-rzg2l.c | 30 +++++++++++++++-------------- 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-rene= sas-rzg2l.c index cd9909a85280..e5393306f610 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -22,7 +22,6 @@ =20 #define IRQC_IRQ_START 1 #define IRQC_IRQ_COUNT 8 -#define IRQC_TINT_START (IRQC_IRQ_START + IRQC_IRQ_COUNT) #define IRQC_TINT_COUNT 32 =20 #define ISCR 0x10 @@ -69,9 +68,11 @@ struct rzg2l_irqc_reg_cache { =20 /** * struct rzg2l_hw_info - Interrupt Control Unit controller hardware info = structure. + * @tint_start: Start of TINT interrupts * @num_irq: Total Number of interrupts */ struct rzg2l_hw_info { + u8 tint_start; u8 num_irq; }; =20 @@ -123,7 +124,7 @@ static void rzg2l_clear_irq_int(struct rzg2l_irqc_priv = *priv, unsigned int hwirq =20 static void rzg2l_clear_tint_int(struct rzg2l_irqc_priv *priv, unsigned in= t hwirq) { - u32 bit =3D BIT(hwirq - IRQC_TINT_START); + u32 bit =3D BIT(hwirq - priv->info->tint_start); u32 reg; =20 reg =3D readl_relaxed(priv->base + TSCR); @@ -145,7 +146,7 @@ static void rzg2l_irqc_eoi(struct irq_data *d) raw_spin_lock(&priv->lock); if (hw_irq >=3D IRQC_IRQ_START && hw_irq <=3D IRQC_IRQ_COUNT) rzg2l_clear_irq_int(priv, hw_irq); - else if (hw_irq >=3D IRQC_TINT_START && hw_irq < priv->info->num_irq) + else if (hw_irq >=3D priv->info->tint_start && hw_irq < priv->info->num_i= rq) rzg2l_clear_tint_int(priv, hw_irq); raw_spin_unlock(&priv->lock); irq_chip_eoi_parent(d); @@ -170,7 +171,7 @@ static void rzfive_irqc_unmask_irq_interrupt(struct rzg= 2l_irqc_priv *priv, static void rzfive_irqc_mask_tint_interrupt(struct rzg2l_irqc_priv *priv, unsigned int hwirq) { - u32 bit =3D BIT(hwirq - IRQC_TINT_START); + u32 bit =3D BIT(hwirq - priv->info->tint_start); =20 writel_relaxed(readl_relaxed(priv->base + TMSK) | bit, priv->base + TMSK); } @@ -178,7 +179,7 @@ static void rzfive_irqc_mask_tint_interrupt(struct rzg2= l_irqc_priv *priv, static void rzfive_irqc_unmask_tint_interrupt(struct rzg2l_irqc_priv *priv, unsigned int hwirq) { - u32 bit =3D BIT(hwirq - IRQC_TINT_START); + u32 bit =3D BIT(hwirq - priv->info->tint_start); =20 writel_relaxed(readl_relaxed(priv->base + TMSK) & ~bit, priv->base + TMSK= ); } @@ -191,7 +192,7 @@ static void rzfive_irqc_mask(struct irq_data *d) raw_spin_lock(&priv->lock); if (hwirq >=3D IRQC_IRQ_START && hwirq <=3D IRQC_IRQ_COUNT) rzfive_irqc_mask_irq_interrupt(priv, hwirq); - else if (hwirq >=3D IRQC_TINT_START && hwirq < priv->info->num_irq) + else if (hwirq >=3D priv->info->tint_start && hwirq < priv->info->num_irq) rzfive_irqc_mask_tint_interrupt(priv, hwirq); raw_spin_unlock(&priv->lock); irq_chip_mask_parent(d); @@ -205,7 +206,7 @@ static void rzfive_irqc_unmask(struct irq_data *d) raw_spin_lock(&priv->lock); if (hwirq >=3D IRQC_IRQ_START && hwirq <=3D IRQC_IRQ_COUNT) rzfive_irqc_unmask_irq_interrupt(priv, hwirq); - else if (hwirq >=3D IRQC_TINT_START && hwirq < priv->info->num_irq) + else if (hwirq >=3D priv->info->tint_start && hwirq < priv->info->num_irq) rzfive_irqc_unmask_tint_interrupt(priv, hwirq); raw_spin_unlock(&priv->lock); irq_chip_unmask_parent(d); @@ -216,8 +217,8 @@ static void rzfive_tint_irq_endisable(struct irq_data *= d, bool enable) struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); unsigned int hwirq =3D irqd_to_hwirq(d); =20 - if (hwirq >=3D IRQC_TINT_START && hwirq < priv->info->num_irq) { - u32 offset =3D hwirq - IRQC_TINT_START; + if (hwirq >=3D priv->info->tint_start && hwirq < priv->info->num_irq) { + u32 offset =3D hwirq - priv->info->tint_start; u32 tssr_offset =3D TSSR_OFFSET(offset); u8 tssr_index =3D TSSR_INDEX(offset); u32 reg; @@ -261,9 +262,9 @@ static void rzg2l_tint_irq_endisable(struct irq_data *d= , bool enable) struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); unsigned int hw_irq =3D irqd_to_hwirq(d); =20 - if (hw_irq >=3D IRQC_TINT_START && hw_irq < priv->info->num_irq) { + if (hw_irq >=3D priv->info->tint_start && hw_irq < priv->info->num_irq) { struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); - u32 offset =3D hw_irq - IRQC_TINT_START; + u32 offset =3D hw_irq - priv->info->tint_start; u32 tssr_offset =3D TSSR_OFFSET(offset); u8 tssr_index =3D TSSR_INDEX(offset); u32 reg; @@ -354,7 +355,7 @@ static int rzg2l_tint_set_edge(struct irq_data *d, unsi= gned int type) { struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); unsigned int hwirq =3D irqd_to_hwirq(d); - u32 titseln =3D hwirq - IRQC_TINT_START; + u32 titseln =3D hwirq - priv->info->tint_start; u32 tssr_offset =3D TSSR_OFFSET(titseln); u8 tssr_index =3D TSSR_INDEX(titseln); u8 index, sense; @@ -401,7 +402,7 @@ static int rzg2l_irqc_set_type(struct irq_data *d, unsi= gned int type) =20 if (hw_irq >=3D IRQC_IRQ_START && hw_irq <=3D IRQC_IRQ_COUNT) ret =3D rzg2l_irq_set_type(d, type); - else if (hw_irq >=3D IRQC_TINT_START && hw_irq < priv->info->num_irq) + else if (hw_irq >=3D priv->info->tint_start && hw_irq < priv->info->num_i= rq) ret =3D rzg2l_tint_set_edge(d, type); if (ret) return ret; @@ -503,7 +504,7 @@ static int rzg2l_irqc_alloc(struct irq_domain *domain, = unsigned int virq, tint =3D TINT_EXTRACT_GPIOINT(hwirq); hwirq =3D TINT_EXTRACT_HWIRQ(hwirq); =20 - if (hwirq < IRQC_TINT_START) + if (hwirq < priv->info->tint_start) return -EINVAL; } =20 @@ -606,6 +607,7 @@ static int rzg2l_irqc_common_probe(struct platform_devi= ce *pdev, struct device_n } =20 static const struct rzg2l_hw_info rzg2l_hw_params =3D { + .tint_start =3D IRQC_IRQ_START + IRQC_IRQ_COUNT, .num_irq =3D IRQC_IRQ_START + IRQC_IRQ_COUNT + IRQC_TINT_COUNT, }; =20 --=20 2.43.0