From nobody Mon Feb 9 04:07:41 2026 Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E0A33347BDC for ; Fri, 6 Feb 2026 11:17:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770376623; cv=none; b=YFcA2Yf+uwtLq1FfmifdplAqxidIALQl3/4eNXqkh1FgM4gqvaKQr3ERkTdx2bGHYRHiqMMljfJNKS/bwjWctYvq15mBV1bgBYhtbepz56duDHNbJV3+2CqFqYD2Qmr9uZaUKL0qTUtLd+HpG9ti2/Uqyqn1/qQr/5HVPB2jlbU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770376623; c=relaxed/simple; bh=Izq0cUu5w2nF36O0r35AWK5tHeyy5cnVSuhACXKr6Ew=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Mu3Af93glmUcfEOOql1hsq4rQq7IJf2RFOtNw/bodk5n3SR4qbcrpwV1iV69ow11/x5ZGPBtI/VczkUKK3uzlenC3OlZvTDIjmDWvIRHeNEqQWfQsx2P90on816s8/hzcei/TLCq6IvpExdJ1ikCqbF/cE2rUg9QZGEIgrkHg60= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=MPaoxtGq; arc=none smtp.client-ip=209.85.128.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="MPaoxtGq" Received: by mail-wm1-f49.google.com with SMTP id 5b1f17b1804b1-4801c2fae63so15618145e9.2 for ; Fri, 06 Feb 2026 03:17:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1770376621; x=1770981421; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=js7qKdAU/TJ7iQQDl75PpIldtNM8YY+mFLcGjFDXtNk=; b=MPaoxtGqob0dY8iP+Te79yVJipmnerX7pG273vItwAZIA6h++l95pz4rsUdV9+BwiT 43orNWsZYRkl9b04UGLVn8yvNylWebTi18Qi2eraDssPViRUK19KhRrk4f/vCQZW2tCd C/O75ngvAxjnFsSNt0UfpI+Bo8ezesF2H/DseKDq7k3wKKSaCtHS6U1jyRb+Wg+OdR2/ Gvr1Y4EmSQoRVO1sAH8T9Oafa15kYR/BKymTgGJux26Mx4b3PAUSRYzvCzf+Zv1Tx4aw /yTnxgocTfpfXFgIysIJO+m/eESKax40lS1LnLPYYXZSAxi8hpSsNBxWBUfP/h4vXyxD UG1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770376621; x=1770981421; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=js7qKdAU/TJ7iQQDl75PpIldtNM8YY+mFLcGjFDXtNk=; b=N5NkpvX+TwXVwQUdwCFJyXb23flsKHnK2dqUsDzwK/QQ9XsDa0zX8AuEYamBzef+w9 7r/Gn2GriU7dqqJ8izoV61YIEaU1PuY9jC3DWZMtoLs+q2RHaOIC0XUsIhSirJKw7Li+ C2/rcCTNP+jC+i9LEsVxxG83/adinXU9NEMNokp00xxj7SsB9jeBjnRQpa1aLXb7HGoK PGNYsExUXKQMaudeVdb5uSfh5LRLmw8jNfP8pu8txgkyRwXSd3V1XRvxeILX8hAsRTbZ OIaxoMX1nirU69oFZtbhWTIekogPZ6d89A40Ad62sit1Fpw6JTt6xXQC+mRGhsGrCMzC 0nXQ== X-Forwarded-Encrypted: i=1; AJvYcCW4iUm7wfwV4XvfSXomzX7Ckulb+wBHr9z13v9WDVn4xO4Jn+ibNhXbdpeF07B+rWdHzRo2uW8qrWVUd5o=@vger.kernel.org X-Gm-Message-State: AOJu0YyxS0daU9lhFmU6yQFVkXHDsEnT6pUpIBfuQ1NZUe4hxXngetMV x5xwWF2FNDOippRWgQ2Uox0TfOGmP/mvjgvaMePR9fO7BwPgzrZKqFGw X-Gm-Gg: AZuq6aIGlrM+K6J547O9cNhBd8A9asSP6/ZzO+Qp6WCjN7F/X7ieHqRzIklqrle2ksl HuMHdnjuA8XvXC/9RKEJ2Mb2HiVWiC4m+1BnInq28fsqAelDqQpdcBrSVJULNvjvpYan44LJVNg Ic+HBNspGqTBsE0LPD6mrqvut8YwV0SnkE6HNkTu3H7aczR8SVSBmPcIecWQAKjYkcCro+eXLI0 EM/QyHJjYRTAVSWCVlMtfoxVDMWRcMd3X3o+6vBysIRc5oY6vczvSCvfPa/fN96uAXW0k8+BauN 46kjyqEI/6uL8+syGHNXcChBq2LPYqn2++ym9kt11Qj4Od4jNeENfb+4zhHcQ3jDwuNPAVvbNX8 F/oFoFA5rxISgd4Iage1+Xc6ntp5v6SNjCcwFef/RcoJo/yUBcL5gmAevbMoDMMWhwn1mRr+Bs3 z6h1ujZT0SdwClXiKyog== X-Received: by 2002:a05:6000:40ca:b0:436:192d:76f8 with SMTP id ffacd0b85a97d-4362933c7f4mr3097029f8f.2.1770376621146; Fri, 06 Feb 2026 03:17:01 -0800 (PST) Received: from biju.lan ([2a00:23c4:a758:8a01:1e64:f8d5:9d7a:19d4]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4362972fa4csm4746380f8f.26.2026.02.06.03.17.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Feb 2026 03:17:00 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , Lad Prabhakar , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Biju Das Subject: [PATCH v3 1/9] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Use pattern for interrupt-names Date: Fri, 6 Feb 2026 11:16:44 +0000 Message-ID: <20260206111658.231934-2-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260206111658.231934-1-biju.das.jz@bp.renesas.com> References: <20260206111658.231934-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Simplify the bindings by using pattern property for interrupt-names. Signed-off-by: Biju Das --- v2->v3: * No change v1->v2: * New patch. --- .../renesas,rzg2l-irqc.yaml | 120 ++++-------------- 1 file changed, 23 insertions(+), 97 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas= ,rzg2l-irqc.yaml b/Documentation/devicetree/bindings/interrupt-controller/r= enesas,rzg2l-irqc.yaml index 44b6ae5fc802..a0b57d808639 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-= irqc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-= irqc.yaml @@ -48,107 +48,33 @@ properties: =20 interrupts: minItems: 45 - items: - - description: NMI interrupt - - description: IRQ0 interrupt - - description: IRQ1 interrupt - - description: IRQ2 interrupt - - description: IRQ3 interrupt - - description: IRQ4 interrupt - - description: IRQ5 interrupt - - description: IRQ6 interrupt - - description: IRQ7 interrupt - - description: GPIO interrupt, TINT0 - - description: GPIO interrupt, TINT1 - - description: GPIO interrupt, TINT2 - - description: GPIO interrupt, TINT3 - - description: GPIO interrupt, TINT4 - - description: GPIO interrupt, TINT5 - - description: GPIO interrupt, TINT6 - - description: GPIO interrupt, TINT7 - - description: GPIO interrupt, TINT8 - - description: GPIO interrupt, TINT9 - - description: GPIO interrupt, TINT10 - - description: GPIO interrupt, TINT11 - - description: GPIO interrupt, TINT12 - - description: GPIO interrupt, TINT13 - - description: GPIO interrupt, TINT14 - - description: GPIO interrupt, TINT15 - - description: GPIO interrupt, TINT16 - - description: GPIO interrupt, TINT17 - - description: GPIO interrupt, TINT18 - - description: GPIO interrupt, TINT19 - - description: GPIO interrupt, TINT20 - - description: GPIO interrupt, TINT21 - - description: GPIO interrupt, TINT22 - - description: GPIO interrupt, TINT23 - - description: GPIO interrupt, TINT24 - - description: GPIO interrupt, TINT25 - - description: GPIO interrupt, TINT26 - - description: GPIO interrupt, TINT27 - - description: GPIO interrupt, TINT28 - - description: GPIO interrupt, TINT29 - - description: GPIO interrupt, TINT30 - - description: GPIO interrupt, TINT31 - - description: Bus error interrupt - - description: ECCRAM0 or combined ECCRAM0/1 1bit error interrupt - - description: ECCRAM0 or combined ECCRAM0/1 2bit error interrupt - - description: ECCRAM0 or combined ECCRAM0/1 error overflow interrupt - - description: ECCRAM1 1bit error interrupt - - description: ECCRAM1 2bit error interrupt - - description: ECCRAM1 error overflow interrupt + maxItems: 48 =20 interrupt-names: minItems: 45 + maxItems: 48 items: - - const: nmi - - const: irq0 - - const: irq1 - - const: irq2 - - const: irq3 - - const: irq4 - - const: irq5 - - const: irq6 - - const: irq7 - - const: tint0 - - const: tint1 - - const: tint2 - - const: tint3 - - const: tint4 - - const: tint5 - - const: tint6 - - const: tint7 - - const: tint8 - - const: tint9 - - const: tint10 - - const: tint11 - - const: tint12 - - const: tint13 - - const: tint14 - - const: tint15 - - const: tint16 - - const: tint17 - - const: tint18 - - const: tint19 - - const: tint20 - - const: tint21 - - const: tint22 - - const: tint23 - - const: tint24 - - const: tint25 - - const: tint26 - - const: tint27 - - const: tint28 - - const: tint29 - - const: tint30 - - const: tint31 - - const: bus-err - - const: ec7tie1-0 - - const: ec7tie2-0 - - const: ec7tiovf-0 - - const: ec7tie1-1 - - const: ec7tie2-1 - - const: ec7tiovf-1 + oneOf: + - description: NMI interrupt + const: nmi + - description: External IRQ interrupt + pattern: '^irq([0-7])$' + - description: GPIO interrupt + pattern: '^tint([0-9]|1[0-9]|2[0-9]|3[0-1])$' + - description: Bus error interrupt + const: bus-err + - description: ECCRAM0 or combined ECCRAM0/1 1bit error interrupt + const: ec7tie1-0 + - description: ECCRAM0 or combined ECCRAM0/1 2bit error interrupt + const: ec7tie2-0 + - description: ECCRAM0 or combined ECCRAM0/1 error overflow interr= upt + const: ec7tiovf-0 + - description: ECCRAM1 1bit error interrupt + const: ec7tie1-1 + - description: ECCRAM1 2bit error interrupt + const: ec7tie2-1 + - description: ECCRAM1 error overflow interrupt + const: ec7tiovf-1 =20 clocks: maxItems: 2 --=20 2.43.0 From nobody Mon Feb 9 04:07:41 2026 Received: from mail-wr1-f65.google.com (mail-wr1-f65.google.com [209.85.221.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 81A7739A816 for ; Fri, 6 Feb 2026 11:17:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.65 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770376623; cv=none; b=DC/qjKtqIQl78pFtHcyZpSoy1k7Cs4W4RbZfarqPIDN+wtlshLcIUUf1ROUrPxJFAjYjJxFSy0VVJ+prRT0PcZDh3/E9xq4zIiwLlWnIX/y/pQkI2Ypd4UaPaxnsO7uas6LWMcvINXjga4ZncWmv+XiAFyzUDAckZH//ZqjUZ3I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770376623; c=relaxed/simple; bh=sRZ8NNxWKbYHIVgVsApwxzatEQoFGwYTfEOA+5UQKjs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FiBrABys6RwJo8ULchvdvISo1idlwS3X3Hji3x+6V3yUVv4Ru6Q84znDGhDI29k4heqKLTvU5wTACwN+BtbqeHyTId+BmiPCcs+TRM6slie7JI0aWkiXVfcInwko4sK6LL1XoRGt1os9B7mFfrrsIc0EwBLGDBAuWst1SkTaKuU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=ROy3lGR7; arc=none smtp.client-ip=209.85.221.65 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ROy3lGR7" Received: by mail-wr1-f65.google.com with SMTP id ffacd0b85a97d-4327790c4e9so1180222f8f.2 for ; Fri, 06 Feb 2026 03:17:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1770376622; x=1770981422; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eq8ZhxrGXuOTWmcmPXPAszI3EhqRT9WZnElfRiN+dWk=; b=ROy3lGR7T1zT7wHgGk/8q7SEA2fHS07X99AN9Y4fCuEv8P/vbhCWVMDaLGMiWcrp99 UQXbPPQsa6u43fyFjCQLvtVD2lwYfw7pwoUUMhs0k213cTeY2S5LF+LWpavM2xHA6Cn3 UIa4/Af0ZC+M18i3a1Pu3HKeHQJtd4kMOSp4HVi92r848vMh4ZIAt3M5JtnwvULsf7Ve sX+6cYR7QnU+oJ0TrJwa7Wyy1bpFigIQ8Cr6lLr8u7mmEtjpLKsPyTYnsNYq6luvH7BV lT+gKKVND1keMnX0vPdOvxm/+XoZrwDhgH1KpVXXNq+1bWwtVvho10BOn/AV0mFfM5Cn YyFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770376622; x=1770981422; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=eq8ZhxrGXuOTWmcmPXPAszI3EhqRT9WZnElfRiN+dWk=; b=lOdYgMilzhWvcdlK18OwAAEqJ0xicz6n69WWf9E0wDF2H8WchS3kaWaRz9cr9weSFn ubgM5zoA6Ck8KYZg2QxFz8E472K63lSbI+ZTeRik1n2AiUInw7jIgzndbKOEUp76zvG6 PY30LaJDvaOe8OZhCDg+5QHcoMcC5kqjq0MxTh9W//Z57MXvgw52ZAZw0RdGLrkWkHYy nfHyUMHVNKRMUpMWu1+6z2hUry//tGmyCDYu9iWbhQOsPeXtcFrsRZSEnmEZBQVDGt+W VGSGVaOGbeTJ6/1TpP05Phbvh3dZxRbzlRbCEWPAYfXULswS8ZhSSlLdhCjrWX+TCh1R LDMQ== X-Forwarded-Encrypted: i=1; AJvYcCXygQXyPForRK5SyUiZtTvyEQ3usuWdzgcdj8NTSYTfrwQOnzBhmwW83cyGgzQei36LsI4XaF7Dy3Nr2eg=@vger.kernel.org X-Gm-Message-State: AOJu0Yxo64/ya5wQ4l+HcojK0N0r4sHyAi8ux8k0APbm4UsZCa0hOa48 PvVO1eZQsQ66hWysMWbtMsF5t+Ph+jmBZUe5S9B2gaXnzfZJd7h2RrNL X-Gm-Gg: AZuq6aKrAlI5YnD5WHUA+Yn9b4pUWBvNMqYaaWDEvGoXFwSbSFSE2pZ33/44nJDJ6Az sqZ77B0HPjhhIhUng88H0FCLBJp48o4VEAlsUlPpBuwoHtDaA2FuMlcNy2GJAwMMuwba59nnJJW INFFbWHMpwtuL0B4himbWKg5Ke+aZpLd2hKgUM08+plPEvdQZdEGXFZ4C5iwXcUFtGqpTMqoanV p0C2fDsKmMi9UZjxqG9NO4VxcPqqEdQ9eI+oyYQ7Ber5q4gI19kRzTS+j/sda6Wl3ina9jIYDBM UTfMXx3zEEqb53tIm+3BRw1IGxeZ1uGdJM1DqOxbU3ES9zpnBEyvIRIHL045dTkk7Pvx/d0uEmf K9rUuu/G92iTSdZ5IyiPIHn72hncccmQGFsdhpndNtVgG6hUGuLOPlQxh6b8vKlBUvvP/0p6oJm YNEjPpT3cZ3Gpx1FcM0w== X-Received: by 2002:a5d:5d87:0:b0:435:9f41:d54 with SMTP id ffacd0b85a97d-436293b29c8mr3344918f8f.60.1770376621784; Fri, 06 Feb 2026 03:17:01 -0800 (PST) Received: from biju.lan ([2a00:23c4:a758:8a01:1e64:f8d5:9d7a:19d4]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4362972fa4csm4746380f8f.26.2026.02.06.03.17.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Feb 2026 03:17:01 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , Lad Prabhakar , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Biju Das Subject: [PATCH v3 2/9] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3L SoC Date: Fri, 6 Feb 2026 11:16:45 +0000 Message-ID: <20260206111658.231934-3-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260206111658.231934-1-biju.das.jz@bp.renesas.com> References: <20260206111658.231934-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Document RZ/G3L (R9A08G046) IRQC bindings. The IRQC block on RZ/G3L SoC is almost identical to one found on the RZ/G3S SoC with the difference like it support more External IRQs, GPT Error Interrupts and also has additional registers for GPT/MTU IRQ selection, shared IRQ selection between external IRQ and TINT. Hence new generic compatible string "renesas,r9a08g046-irqc" is added for RZ/G3L SoC. Signed-off-by: Biju Das --- v2->v3: * Dropped items and instead used enum for single compatible values * Add minItems for interrupts and interrupt-names properties of=20 the RZ/{G2L,G2UL,Five,V2L} SoCs * Replaced maxItems->minItems for interrupts and interrupt-names properties of the RZ/G3L SoC. v1->v2: * Simplified the binding using pattern --- .../renesas,rzg2l-irqc.yaml | 43 ++++++++++++++++--- 1 file changed, 36 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas= ,rzg2l-irqc.yaml b/Documentation/devicetree/bindings/interrupt-controller/r= enesas,rzg2l-irqc.yaml index a0b57d808639..3a221e1800a0 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-= irqc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-= irqc.yaml @@ -30,7 +30,9 @@ properties: - renesas,r9a08g045-irqc # RZ/G3S - const: renesas,rzg2l-irqc =20 - - const: renesas,r9a07g043f-irqc # RZ/Five + - enum: + - renesas,r9a07g043f-irqc # RZ/Five + - renesas,r9a08g046-irqc # RZ/G3L =20 '#interrupt-cells': description: The first cell should contain a macro RZG2L_{NMI,IRQX} in= cluded in the @@ -48,17 +50,17 @@ properties: =20 interrupts: minItems: 45 - maxItems: 48 + maxItems: 61 =20 interrupt-names: minItems: 45 - maxItems: 48 + maxItems: 61 items: oneOf: - description: NMI interrupt const: nmi - description: External IRQ interrupt - pattern: '^irq([0-7])$' + pattern: '^irq([0-9]|1[0-5])$' - description: GPIO interrupt pattern: '^tint([0-9]|1[0-9]|2[0-9]|3[0-1])$' - description: Bus error interrupt @@ -75,6 +77,8 @@ properties: const: ec7tie2-1 - description: ECCRAM1 error overflow interrupt const: ec7tiovf-1 + - description: Integrated GPT Error interrupt + pattern: '^ovfunf([0-7])$' =20 clocks: maxItems: 2 @@ -106,6 +110,24 @@ required: allOf: - $ref: /schemas/interrupt-controller.yaml# =20 + - if: + properties: + compatible: + contains: + enum: + - renesas,r9a07g043f-irqc + - renesas,r9a07g043u-irqc + - renesas,r9a07g044-irqc + - renesas,r9a07g054-irqc + then: + properties: + interrupts: + minItems: 48 + maxItems: 48 + interrupt-names: + minItems: 48 + maxItems: 48 + - if: properties: compatible: @@ -118,12 +140,19 @@ allOf: maxItems: 45 interrupt-names: maxItems: 45 - else: + + - if: + properties: + compatible: + contains: + enum: + - renesas,r9a08g046-irqc + then: properties: interrupts: - minItems: 48 + minItems: 61 interrupt-names: - minItems: 48 + minItems: 61 =20 unevaluatedProperties: false =20 --=20 2.43.0 From nobody Mon Feb 9 04:07:41 2026 Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 14A013A0B0E for ; Fri, 6 Feb 2026 11:17:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770376624; cv=none; b=KxM4OVfN9s7a7Zscye/KhI5If/V8BEJPtqwnqklsnfztUdGJE53PbrXu0wNha6qkaWDv9Hlm6IgeIJPQE1/V9QAEVeTMBWZCYiNw9Vsx8m2B9Qa2CTWP64yyFGVfD+Xmzh4yUUbi15gbwOxcoFQRDGf+EWsQQiCuVKPJHfublAo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770376624; c=relaxed/simple; bh=Hbg3emuCT1am9B/27fxHBDXfsVOms2s0E6GBR0y519g=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qqyXnFOAX84g26awv2mlBtENus/H5Jls6NMsLXaZ/pRQw+H0A1R0lNDLnLY5eVRofG215rmnR28mRQ8k28w0sXXfAtaa75HUPccksRoamwpZNeN5IVzS2rWMr7W4dy1VCrTcDIvF72oB6yW06X85+rFMbbRJt83eErL1h1FV5Ao= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=Ord80ujy; arc=none smtp.client-ip=209.85.221.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Ord80ujy" Received: by mail-wr1-f48.google.com with SMTP id ffacd0b85a97d-435a11957f6so1568405f8f.0 for ; Fri, 06 Feb 2026 03:17:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1770376622; x=1770981422; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9J1iVCwTS7iX2pXRRIO5Px5zYQH04DMA0QCRC7iMC5A=; b=Ord80ujym7lLzDywtwiUip3on4aExg8wVEHQ7LsysNwdQxWAdeO+bhdk6l6odhvXC0 SXm4ZKTXtkgZWCaHOGB4GVdVdeadx3Y76jrEaHzOMey3MZIp1hiaGfchpLYhCY71a89t TSaP5ComZyTFQyjeRweUSihEgnRe50Kr+mXVpOYSkS+7ANZI3jHt0i5WnXORrPDjmffD 8U24tk9yNUfwtCPiNleRlklDaW6RLrk2AlMtZ74NfZNoftgUci0X8wGVgl16euxZd0iS zU39OwcxRS8R9qB6gw4JjCsF2k6YLcnNMH4lSRNe866qk4aPeZENskRXJOkxHaa6SMh4 z2nQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770376622; x=1770981422; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=9J1iVCwTS7iX2pXRRIO5Px5zYQH04DMA0QCRC7iMC5A=; b=XmGy6CQjeDMS6GaE37MB1hBq4HNezzzfz+qsSyPEmEdYnTamNkaehT8yDDMMbVXWkS majINeirCikISpp0UnlaTstMo5Sv4O4G6ahxR3IzKquy2r5euyqFr/T32G60NY5t0KRA 4dukfYzjM2Ago58W7Yl0xqnJXYnztxHlG7vhSrUf91lZXyzp37zR2eGaaodH3fU86UkP lCgbwQViW0FLwshSnQ1rBHQsMLjZiURLQZc5hiqUWe2l6mVc1dBjLTyRP/3HOvGoSUCu qI9i8aPMDmdgDygcJvH9q/xxqBR3DYKxxtSL5dAsBUiK2UB/enyuaVoG63+GbHylvvVH mA8A== X-Forwarded-Encrypted: i=1; AJvYcCUxl75+GTv8SFKOWQ77YkaiaZ4l/noGu4C9UUCkDaZe2g8Ugs+9c7Hh0ITQAHRtf16fYMEtrV2UW2qZcIA=@vger.kernel.org X-Gm-Message-State: AOJu0Yxh3i7V5zo5maABSmv5fgXNCFLy6ctgFVcslHzT/vcEPhqMdlFX eNcprgEzMmdNsUiPoWYYYFI8tYcqTdxE87pA8w9Tk4HQju/nQQuiBw9RB7tSB5co X-Gm-Gg: AZuq6aKd53OTZE5oJvGlUpkFOuxjy92146P3Fb0aF8Mg7kJT0kApAlyepBDEiBWarIn GVmbDi3RxfluIFkEk0er8HMfPdsiHWuVHa2FMpcgLlw4VMMPs4mjkAPrCGWpatIep3RY5OGWYxN 6lsLPPYMybMP70N/zwgl0Yu0znyZ28kU72DUEDsJTebLXDorh3kbVth4uzgjASpzPyH3+avSUNN fG/F+NfIgcfWXHdMWGLXYeUwTnpy5wh6YkDRfjVJXvfevsKG6u8sftl+0nueM8Tj5wRi3/vUMGW u82Yb0diiWKjW+2ZqLQ7e1cQQe82V4Vb4LksovYepbcJG8bDSMcObMXbbHr1uMcCh8zxqGvX6cA S2sBcb57NvuXqjE0cuJKi0ESzc3HPa6u5g8myL/cFG5SA1Cru1Krsr1MeTug6KIoj+1rdInBGk6 q77rz+2EO9ZnXDoBqQow== X-Received: by 2002:a05:6000:25c7:b0:431:5ac:1fc with SMTP id ffacd0b85a97d-43629341bb4mr3445076f8f.14.1770376622281; Fri, 06 Feb 2026 03:17:02 -0800 (PST) Received: from biju.lan ([2a00:23c4:a758:8a01:1e64:f8d5:9d7a:19d4]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4362972fa4csm4746380f8f.26.2026.02.06.03.17.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Feb 2026 03:17:02 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Thomas Gleixner Cc: Biju Das , linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v3 3/9] irqchip/renesas-rzg2l: Make fwspec variable as pointer in struct rzg2l_irqc_priv Date: Fri, 6 Feb 2026 11:16:46 +0000 Message-ID: <20260206111658.231934-4-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260206111658.231934-1-biju.das.jz@bp.renesas.com> References: <20260206111658.231934-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The total number of IRQs in RZ/G2L and RZ/G3L SoC are different. The RZ/G3L has 16 external IRQs where as RZ/G2L has only 8 external IRQ. Dynamicaly allocate fwspec memory instead of static allocation to support both SoCs. Signed-off-by: Biju Das --- v2->v3: * No change v1->v2: * No change --- drivers/irqchip/irq-renesas-rzg2l.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-rene= sas-rzg2l.c index e73d426cea6d..20e2b1c4587b 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -79,7 +79,7 @@ struct rzg2l_irqc_reg_cache { static struct rzg2l_irqc_priv { void __iomem *base; const struct irq_chip *irqchip; - struct irq_fwspec fwspec[IRQC_NUM_IRQ]; + struct irq_fwspec *fwspec; raw_spinlock_t lock; struct rzg2l_irqc_reg_cache cache; } *rzg2l_irqc_data; @@ -554,6 +554,11 @@ static int rzg2l_irqc_common_probe(struct platform_dev= ice *pdev, struct device_n if (IS_ERR(rzg2l_irqc_data->base)) return PTR_ERR(rzg2l_irqc_data->base); =20 + rzg2l_irqc_data->fwspec =3D devm_kcalloc(&pdev->dev, IRQC_NUM_IRQ, + sizeof(*rzg2l_irqc_data->fwspec), GFP_KERNEL); + if (!rzg2l_irqc_data->fwspec) + return -ENOMEM; + ret =3D rzg2l_irqc_parse_interrupts(rzg2l_irqc_data, node); if (ret) return dev_err_probe(dev, ret, "cannot parse interrupts: %d\n", ret); --=20 2.43.0 From nobody Mon Feb 9 04:07:41 2026 Received: from mail-wr1-f50.google.com (mail-wr1-f50.google.com [209.85.221.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D2A393A0E98 for ; Fri, 6 Feb 2026 11:17:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770376625; cv=none; b=SM5Xd52M4WeGkZ+G5jWUra5QTeR9ZyyheOM+I7PafP7XSNxH/qWWPWX98kbL0NnUrEPbu+Ej0tOGFHW9YMjL7GtVo+AVRz+L+tXHBRZkHYHsFE3YePdPZ83hwx8d2jSVcHALXLdvLWoq9GKCyIIs5Y7vtZNbf5+VDRUK1Y+ve20= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770376625; c=relaxed/simple; bh=86OhowibGWeEfEvV9wCBm+XwXiwHWiOcVYBqqYti1RQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=psOHNb+XHWDWilMoEYrzaxS2kOFxMVtw8BglSTYLVQIPEKWqA1H7MFhtJfze8LmJRq8TJomJVi0q4PfzNv2KfhZOm5lEvuk0ygvHO9m4rwQj0Ur6S3kC080eXJZdsPFJygHBrlH057/4gx3LH1Cl4uKc12p8WmhMQ+H9D5DK948= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=dVEwddPI; arc=none smtp.client-ip=209.85.221.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="dVEwddPI" Received: by mail-wr1-f50.google.com with SMTP id ffacd0b85a97d-4358fb60802so1341763f8f.1 for ; Fri, 06 Feb 2026 03:17:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1770376623; x=1770981423; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WHVwM3agHEhyWogQbMgCPjNf0AYujgedtHyS/pdWjpo=; b=dVEwddPIMVajx77wdtuMoWwVU7r2r7qzl1S/4bRdfkcMRA/lZkO7pxML0VK8fbLTj0 ed/2bXycCR0s2P5rABgF3h5bdCtO15leLgSAHJhD+74s+cS/gvjjFlEYdMuBC8YFx82M P6G0+3UrozYHLlPPvL5n75Ldb3JX4bwBCH57nxBA5KXumoo/hA0t+/cAVAhZ039/WDvL 3YER0G+tGs8vtxFDM9rQFLjq56FZyPiExRDexT7oV8/xDT8QUFhBW+7EaWIgKZGlBmcc mN3vySlNQhhOg4Nsl+lPKxDuFgXrJHtE5BLrQdcZYTcuU4L3u7u0hPCts/8JuGaMWe1P 97mA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770376623; x=1770981423; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=WHVwM3agHEhyWogQbMgCPjNf0AYujgedtHyS/pdWjpo=; b=a+S3OvA6x15GXwx2C2u1h8YJkDucscIvjHd8eYNaO3/zp4IgXIBWeGfSbx7X4nS2kB ymcdJTAa8c1ZpWb77aD3g/twoRD3K0Ls/aAnmSSbk85oBlM4ZOhS0E9ikHYYRFHdAXoQ EBp5xdXWG2ux9QGnGrnvCLkSWKip93xloVtDqq19zBdU7ZbNROMbu6VPR6dlU5ndHWpH uJEcpfbnUzW3Jitp6bBft9uqhdTKXIjjsUAum07bJNeN/erBth1ZaIs3vFMC9L2kFeL/ TzgpFPxQbWNk3K7pl5rfPwObdBGas0MJ+YlkiNkXSppzivgevdnoCEqWNXQmX0zJM3AP dDDg== X-Forwarded-Encrypted: i=1; AJvYcCVOeDSW1GJQRTUmyytgpy0I3FQEmYrWETYF0G1mUZ86ScIf99By/HvEHm4unyerW/6/+12AoIUUWqIpADM=@vger.kernel.org X-Gm-Message-State: AOJu0YytQfYsUsMqdM/lssdnVHvZbCJPuXHjAuEy/ZvZW+5JlwtokL7n qX5AOg2CZQKfiP5N4rXMsD+OHk28ZphZYQoh1J9Ps85aqlXuLQybqUmF X-Gm-Gg: AZuq6aLS2htc2kyoVsJ2CGG8F8QQmZNSSkxHSqvjqBfe0lV0p3edRWt9Wck1vaXxMVr uLXlyzy6QuFxT0VMoKzgsAqoKUXQDQ6xqaePDWvGs9ahNalDzbsK3u6jUFoTsoIB71XZLpL1Qv0 Cef0lC+U/ZFXZ5U3M3q/iIkg+V369Us90IxLrAdno60JMPuH3sdqzxsdB5UAk+nhuQvQqGLqF/i 3YeI0eFozIb9/XFPksIawHCTHcajZRr8TrZeKyRZ85Jqi8f/hT7UbX4Ljsg2OHq8mXMHkLq6+Ze n6zbztQO9VOLt5kbe0JpZ6u9tUWb+feIArt6dcsS3aEz2vred3d7zw6pX5omOPHAds+b2UohOBj csCxJZFzcuwlIJ64Y5Qqzc/Q6e0BkQyGCeJauAvSP2toR/DBIRd89/f/oSACyHk5A5HKyfAgnqM WtnF0lfugO8Ob2x8jS963qLdLCzZ3R X-Received: by 2002:a05:6000:605:b0:436:1405:3ef8 with SMTP id ffacd0b85a97d-4362098779dmr9315241f8f.1.1770376623077; Fri, 06 Feb 2026 03:17:03 -0800 (PST) Received: from biju.lan ([2a00:23c4:a758:8a01:1e64:f8d5:9d7a:19d4]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4362972fa4csm4746380f8f.26.2026.02.06.03.17.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Feb 2026 03:17:02 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Thomas Gleixner Cc: Biju Das , linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v3 4/9] irqchip/renesas-rzg2l: Drop IRQC_NUM_IRQ macro Date: Fri, 6 Feb 2026 11:16:47 +0000 Message-ID: <20260206111658.231934-5-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260206111658.231934-1-biju.das.jz@bp.renesas.com> References: <20260206111658.231934-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The total number of IRQs in RZ/G2L and RZ/G3L SoC are different. Introduce struct rzg2l_hw_info to handle the hardware differences and replace the macro IRQC_NUM_IRQ with num_irq variable in struct rzg2l_hw_info. Signed-off-by: Biju Das --- v2->v3: * No change v1->v2: * No change --- drivers/irqchip/irq-renesas-rzg2l.c | 46 ++++++++++++++++++++--------- 1 file changed, 32 insertions(+), 14 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-rene= sas-rzg2l.c index 20e2b1c4587b..cd9909a85280 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -24,7 +24,6 @@ #define IRQC_IRQ_COUNT 8 #define IRQC_TINT_START (IRQC_IRQ_START + IRQC_IRQ_COUNT) #define IRQC_TINT_COUNT 32 -#define IRQC_NUM_IRQ (IRQC_TINT_START + IRQC_TINT_COUNT) =20 #define ISCR 0x10 #define IITSR 0x14 @@ -68,12 +67,21 @@ struct rzg2l_irqc_reg_cache { u32 titsr[2]; }; =20 +/** + * struct rzg2l_hw_info - Interrupt Control Unit controller hardware info = structure. + * @num_irq: Total Number of interrupts + */ +struct rzg2l_hw_info { + u8 num_irq; +}; + /** * struct rzg2l_irqc_priv - IRQ controller private data structure * @base: Controller's base address * @irqchip: Pointer to struct irq_chip * @fwspec: IRQ firmware specific data * @lock: Lock to serialize access to hardware registers + * @info: Pointer to struct rzg2l_hw_info * @cache: Registers cache for suspend/resume */ static struct rzg2l_irqc_priv { @@ -81,6 +89,7 @@ static struct rzg2l_irqc_priv { const struct irq_chip *irqchip; struct irq_fwspec *fwspec; raw_spinlock_t lock; + const struct rzg2l_hw_info *info; struct rzg2l_irqc_reg_cache cache; } *rzg2l_irqc_data; =20 @@ -136,7 +145,7 @@ static void rzg2l_irqc_eoi(struct irq_data *d) raw_spin_lock(&priv->lock); if (hw_irq >=3D IRQC_IRQ_START && hw_irq <=3D IRQC_IRQ_COUNT) rzg2l_clear_irq_int(priv, hw_irq); - else if (hw_irq >=3D IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) + else if (hw_irq >=3D IRQC_TINT_START && hw_irq < priv->info->num_irq) rzg2l_clear_tint_int(priv, hw_irq); raw_spin_unlock(&priv->lock); irq_chip_eoi_parent(d); @@ -182,7 +191,7 @@ static void rzfive_irqc_mask(struct irq_data *d) raw_spin_lock(&priv->lock); if (hwirq >=3D IRQC_IRQ_START && hwirq <=3D IRQC_IRQ_COUNT) rzfive_irqc_mask_irq_interrupt(priv, hwirq); - else if (hwirq >=3D IRQC_TINT_START && hwirq < IRQC_NUM_IRQ) + else if (hwirq >=3D IRQC_TINT_START && hwirq < priv->info->num_irq) rzfive_irqc_mask_tint_interrupt(priv, hwirq); raw_spin_unlock(&priv->lock); irq_chip_mask_parent(d); @@ -196,7 +205,7 @@ static void rzfive_irqc_unmask(struct irq_data *d) raw_spin_lock(&priv->lock); if (hwirq >=3D IRQC_IRQ_START && hwirq <=3D IRQC_IRQ_COUNT) rzfive_irqc_unmask_irq_interrupt(priv, hwirq); - else if (hwirq >=3D IRQC_TINT_START && hwirq < IRQC_NUM_IRQ) + else if (hwirq >=3D IRQC_TINT_START && hwirq < priv->info->num_irq) rzfive_irqc_unmask_tint_interrupt(priv, hwirq); raw_spin_unlock(&priv->lock); irq_chip_unmask_parent(d); @@ -207,7 +216,7 @@ static void rzfive_tint_irq_endisable(struct irq_data *= d, bool enable) struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); unsigned int hwirq =3D irqd_to_hwirq(d); =20 - if (hwirq >=3D IRQC_TINT_START && hwirq < IRQC_NUM_IRQ) { + if (hwirq >=3D IRQC_TINT_START && hwirq < priv->info->num_irq) { u32 offset =3D hwirq - IRQC_TINT_START; u32 tssr_offset =3D TSSR_OFFSET(offset); u8 tssr_index =3D TSSR_INDEX(offset); @@ -249,9 +258,10 @@ static void rzfive_irqc_irq_enable(struct irq_data *d) =20 static void rzg2l_tint_irq_endisable(struct irq_data *d, bool enable) { + struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); unsigned int hw_irq =3D irqd_to_hwirq(d); =20 - if (hw_irq >=3D IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) { + if (hw_irq >=3D IRQC_TINT_START && hw_irq < priv->info->num_irq) { struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); u32 offset =3D hw_irq - IRQC_TINT_START; u32 tssr_offset =3D TSSR_OFFSET(offset); @@ -385,12 +395,13 @@ static int rzg2l_tint_set_edge(struct irq_data *d, un= signed int type) =20 static int rzg2l_irqc_set_type(struct irq_data *d, unsigned int type) { + struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); unsigned int hw_irq =3D irqd_to_hwirq(d); int ret =3D -EINVAL; =20 if (hw_irq >=3D IRQC_IRQ_START && hw_irq <=3D IRQC_IRQ_COUNT) ret =3D rzg2l_irq_set_type(d, type); - else if (hw_irq >=3D IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) + else if (hw_irq >=3D IRQC_TINT_START && hw_irq < priv->info->num_irq) ret =3D rzg2l_tint_set_edge(d, type); if (ret) return ret; @@ -496,7 +507,7 @@ static int rzg2l_irqc_alloc(struct irq_domain *domain, = unsigned int virq, return -EINVAL; } =20 - if (hwirq > (IRQC_NUM_IRQ - 1)) + if (hwirq > (priv->info->num_irq - 1)) return -EINVAL; =20 ret =3D irq_domain_set_hwirq_and_chip(domain, virq, hwirq, priv->irqchip, @@ -520,7 +531,7 @@ static int rzg2l_irqc_parse_interrupts(struct rzg2l_irq= c_priv *priv, unsigned int i; int ret; =20 - for (i =3D 0; i < IRQC_NUM_IRQ; i++) { + for (i =3D 0; i < priv->info->num_irq; i++) { ret =3D of_irq_parse_one(np, i, &map); if (ret) return ret; @@ -532,7 +543,8 @@ static int rzg2l_irqc_parse_interrupts(struct rzg2l_irq= c_priv *priv, } =20 static int rzg2l_irqc_common_probe(struct platform_device *pdev, struct de= vice_node *parent, - const struct irq_chip *irq_chip) + const struct irq_chip *irq_chip, + const struct rzg2l_hw_info *info) { struct irq_domain *irq_domain, *parent_domain; struct device_node *node =3D pdev->dev.of_node; @@ -554,7 +566,9 @@ static int rzg2l_irqc_common_probe(struct platform_devi= ce *pdev, struct device_n if (IS_ERR(rzg2l_irqc_data->base)) return PTR_ERR(rzg2l_irqc_data->base); =20 - rzg2l_irqc_data->fwspec =3D devm_kcalloc(&pdev->dev, IRQC_NUM_IRQ, + rzg2l_irqc_data->info =3D info; + + rzg2l_irqc_data->fwspec =3D devm_kcalloc(&pdev->dev, info->num_irq, sizeof(*rzg2l_irqc_data->fwspec), GFP_KERNEL); if (!rzg2l_irqc_data->fwspec) return -ENOMEM; @@ -579,7 +593,7 @@ static int rzg2l_irqc_common_probe(struct platform_devi= ce *pdev, struct device_n =20 raw_spin_lock_init(&rzg2l_irqc_data->lock); =20 - irq_domain =3D irq_domain_create_hierarchy(parent_domain, 0, IRQC_NUM_IRQ= , dev_fwnode(dev), + irq_domain =3D irq_domain_create_hierarchy(parent_domain, 0, info->num_ir= q, dev_fwnode(dev), &rzg2l_irqc_domain_ops, rzg2l_irqc_data); if (!irq_domain) { pm_runtime_put(dev); @@ -591,14 +605,18 @@ static int rzg2l_irqc_common_probe(struct platform_de= vice *pdev, struct device_n return 0; } =20 +static const struct rzg2l_hw_info rzg2l_hw_params =3D { + .num_irq =3D IRQC_IRQ_START + IRQC_IRQ_COUNT + IRQC_TINT_COUNT, +}; + static int rzg2l_irqc_probe(struct platform_device *pdev, struct device_no= de *parent) { - return rzg2l_irqc_common_probe(pdev, parent, &rzg2l_irqc_chip); + return rzg2l_irqc_common_probe(pdev, parent, &rzg2l_irqc_chip, &rzg2l_hw_= params); } =20 static int rzfive_irqc_probe(struct platform_device *pdev, struct device_n= ode *parent) { - return rzg2l_irqc_common_probe(pdev, parent, &rzfive_irqc_chip); + return rzg2l_irqc_common_probe(pdev, parent, &rzfive_irqc_chip, &rzg2l_hw= _params); } =20 IRQCHIP_PLATFORM_DRIVER_BEGIN(rzg2l_irqc) --=20 2.43.0 From nobody Mon Feb 9 04:07:41 2026 Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 711563A1A41 for ; Fri, 6 Feb 2026 11:17:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770376625; cv=none; b=tESJHdO/nHD7XaiwXGF4Nanb/0Bxk1+bxlScxN1/bjr0Xm63P+5+kngBcUPDvTuCQGYJmjGZgYjFsn1OJj2JGVG942PfQOR2WNMud4BW8Rk2FHlx7a2Cl/CpeDoVi3u674hfXo/8hu5vQGb8PpDSofecuXh9kMkc/ERxQyaqVEA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770376625; c=relaxed/simple; bh=CZL93i9lwGn5bvjaHgHDOUILkMxch2ACe0LhGZi3AZw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=n+z3Eo3MusxcJw9r/VjRNw4lw0qYURqZmfB7aGFQQxSJxxYKUS1NxWb64vXxL49o7SfgaebGloH8qVWLVsTPtursywkEZyRJIuQIkBjO2UXlCWsX47pclw2R6dL2FI+7EBuFFmSgj49JWA/7yj5TMLDqxvqbM+5Fq2UD4J8luiI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=Bbkw+QRU; arc=none smtp.client-ip=209.85.221.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Bbkw+QRU" Received: by mail-wr1-f41.google.com with SMTP id ffacd0b85a97d-4362197d174so1254619f8f.3 for ; Fri, 06 Feb 2026 03:17:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1770376624; x=1770981424; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FwF99Mr55yenScot/Bs5ZL0xH8vE7aXRKx78QjXo8xg=; b=Bbkw+QRUAh9YF5bWLvYZBpj6qIHNzMY/XtPsz6TgAfsijRdKZ/YtA+JpoB7SBApgec PcqiU9JgZNGAQ+nZQPyDMFI4Z9XQwl3bZimh9u7rxurBFvGajFUA3Lmptr0u0Ok6KXdm 6qg1MhI3kHKUhAw1x4MttgWqKogQ03zL4P79EQ9wwBSd8n5LmQSMnNS6YQC/ptyVdTwj GX0P3OztPa3ghuS564Luy6PCfdWR4epF/YHYO6cTL2YahzXwrRKO3KioPIbwkhyFU1wZ Zt7wCQVeFEk4/PS+l7WNQW34vIjpB+TJp1hDBp/f6ync+MOYOLJ9c8DxF/t9xBdMOUyU D7IA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770376624; x=1770981424; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=FwF99Mr55yenScot/Bs5ZL0xH8vE7aXRKx78QjXo8xg=; b=wqjZn/KlYxLjRuQJv4+DkLLYaIQ9xTVLcNqOYp4A8rZk0MXQv0328kGnhcwAPKghsz HVRhm/WwR36JUxXe5yRnHOLIor3tLOXA0TsCoIbmalAYJc+JPcvQj5gdqgEA7x6Pcg+Q QrTep5C2cpk1coUVOnaPyieTza12gLnNKju61JziW1QrZDVb7Lfmmrq82/e20KwfCSDv ThdRQafcsZLKQaLCoLRa0BfxqdnH9ODLtVLbeR2yHJZH2kG1o9AF1RpC+yphz9u0AOHV MCx+ZNI5UGeyDBGIw9s9ESu9R5gTBxXxlRF+D8jO+ZtDo7u7kzELtDEAVY1HtqMAOyEp rmfg== X-Forwarded-Encrypted: i=1; AJvYcCUGcWPDe5EKN+Ux5usN+RtenveaSLDLFJpC4C4DAj1rRSMpsL7xBYladrcUzxMzHfdRE7pwQhrMj2i8Dp4=@vger.kernel.org X-Gm-Message-State: AOJu0Yx5sgDBUIlDFNfp2+XGp4nQVvTiYpYFiDfNVLfP9nIkDWrMEdTF msyMXvhDm97lENPPi0zjcHdRl2KnixFvjcXm5AZxpsJlfKELjTnnP72k X-Gm-Gg: AZuq6aLWh5wzi4+abhGuwvmwZjaikvXVmIjKjBrtkdBbqGiqNXl1fNjm3Dl64b2Gs91 pyuassBtHdcMmaWBzN8qS9DTYBLwuyNrpclA9+0UUcs3QnMxgTrLdVEiLo6Y8hxSoRwClrIy2vS KRgpspOip4EMhwVBghW91jDmkDqWvpGVf0FmVYWB3M+aI8lZjZnK+2LrFo6QCVcQZ4148rpIVrd 75rusfFc5CJLwUCMUy4l+TVvKiHVYOS7ISeHXLkAnd9IBU4CENzFFINI5U62ryDv1Gk4okrcWuW 0z/JjCSlVf/8sn6f2F3TcHZmydd4c7cancn4DtA7MregRZ4CDBPd6vI3D/Pr79syRm1JqVLJuKI 78r9JC/mqm/PBqCUqhWo1DJnljup8ZmNDTVcY73chj3NsTw50eqNc0sFMA2RYImsERUBC36vFRk ChOqFtTcy5Fu4PXT2uHw== X-Received: by 2002:a05:6000:1a86:b0:433:1d30:45f with SMTP id ffacd0b85a97d-4362904b88dmr3350439f8f.1.1770376623678; Fri, 06 Feb 2026 03:17:03 -0800 (PST) Received: from biju.lan ([2a00:23c4:a758:8a01:1e64:f8d5:9d7a:19d4]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4362972fa4csm4746380f8f.26.2026.02.06.03.17.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Feb 2026 03:17:03 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Thomas Gleixner Cc: Biju Das , linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v3 5/9] irqchip/renesas-rzg2l: Drop IRQC_TINT_START macro Date: Fri, 6 Feb 2026 11:16:48 +0000 Message-ID: <20260206111658.231934-6-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260206111658.231934-1-biju.das.jz@bp.renesas.com> References: <20260206111658.231934-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The IRQC_TINT_START value is different for RZ/G3L and RZ/G2L SoC. Add tint_start variable in struct rzg2l_hw_info to handle this differences and drop the macro IRQC_TINT_START. Signed-off-by: Biju Das --- v2->v3: * No change v1->v2: * No change --- drivers/irqchip/irq-renesas-rzg2l.c | 30 +++++++++++++++-------------- 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-rene= sas-rzg2l.c index cd9909a85280..e5393306f610 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -22,7 +22,6 @@ =20 #define IRQC_IRQ_START 1 #define IRQC_IRQ_COUNT 8 -#define IRQC_TINT_START (IRQC_IRQ_START + IRQC_IRQ_COUNT) #define IRQC_TINT_COUNT 32 =20 #define ISCR 0x10 @@ -69,9 +68,11 @@ struct rzg2l_irqc_reg_cache { =20 /** * struct rzg2l_hw_info - Interrupt Control Unit controller hardware info = structure. + * @tint_start: Start of TINT interrupts * @num_irq: Total Number of interrupts */ struct rzg2l_hw_info { + u8 tint_start; u8 num_irq; }; =20 @@ -123,7 +124,7 @@ static void rzg2l_clear_irq_int(struct rzg2l_irqc_priv = *priv, unsigned int hwirq =20 static void rzg2l_clear_tint_int(struct rzg2l_irqc_priv *priv, unsigned in= t hwirq) { - u32 bit =3D BIT(hwirq - IRQC_TINT_START); + u32 bit =3D BIT(hwirq - priv->info->tint_start); u32 reg; =20 reg =3D readl_relaxed(priv->base + TSCR); @@ -145,7 +146,7 @@ static void rzg2l_irqc_eoi(struct irq_data *d) raw_spin_lock(&priv->lock); if (hw_irq >=3D IRQC_IRQ_START && hw_irq <=3D IRQC_IRQ_COUNT) rzg2l_clear_irq_int(priv, hw_irq); - else if (hw_irq >=3D IRQC_TINT_START && hw_irq < priv->info->num_irq) + else if (hw_irq >=3D priv->info->tint_start && hw_irq < priv->info->num_i= rq) rzg2l_clear_tint_int(priv, hw_irq); raw_spin_unlock(&priv->lock); irq_chip_eoi_parent(d); @@ -170,7 +171,7 @@ static void rzfive_irqc_unmask_irq_interrupt(struct rzg= 2l_irqc_priv *priv, static void rzfive_irqc_mask_tint_interrupt(struct rzg2l_irqc_priv *priv, unsigned int hwirq) { - u32 bit =3D BIT(hwirq - IRQC_TINT_START); + u32 bit =3D BIT(hwirq - priv->info->tint_start); =20 writel_relaxed(readl_relaxed(priv->base + TMSK) | bit, priv->base + TMSK); } @@ -178,7 +179,7 @@ static void rzfive_irqc_mask_tint_interrupt(struct rzg2= l_irqc_priv *priv, static void rzfive_irqc_unmask_tint_interrupt(struct rzg2l_irqc_priv *priv, unsigned int hwirq) { - u32 bit =3D BIT(hwirq - IRQC_TINT_START); + u32 bit =3D BIT(hwirq - priv->info->tint_start); =20 writel_relaxed(readl_relaxed(priv->base + TMSK) & ~bit, priv->base + TMSK= ); } @@ -191,7 +192,7 @@ static void rzfive_irqc_mask(struct irq_data *d) raw_spin_lock(&priv->lock); if (hwirq >=3D IRQC_IRQ_START && hwirq <=3D IRQC_IRQ_COUNT) rzfive_irqc_mask_irq_interrupt(priv, hwirq); - else if (hwirq >=3D IRQC_TINT_START && hwirq < priv->info->num_irq) + else if (hwirq >=3D priv->info->tint_start && hwirq < priv->info->num_irq) rzfive_irqc_mask_tint_interrupt(priv, hwirq); raw_spin_unlock(&priv->lock); irq_chip_mask_parent(d); @@ -205,7 +206,7 @@ static void rzfive_irqc_unmask(struct irq_data *d) raw_spin_lock(&priv->lock); if (hwirq >=3D IRQC_IRQ_START && hwirq <=3D IRQC_IRQ_COUNT) rzfive_irqc_unmask_irq_interrupt(priv, hwirq); - else if (hwirq >=3D IRQC_TINT_START && hwirq < priv->info->num_irq) + else if (hwirq >=3D priv->info->tint_start && hwirq < priv->info->num_irq) rzfive_irqc_unmask_tint_interrupt(priv, hwirq); raw_spin_unlock(&priv->lock); irq_chip_unmask_parent(d); @@ -216,8 +217,8 @@ static void rzfive_tint_irq_endisable(struct irq_data *= d, bool enable) struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); unsigned int hwirq =3D irqd_to_hwirq(d); =20 - if (hwirq >=3D IRQC_TINT_START && hwirq < priv->info->num_irq) { - u32 offset =3D hwirq - IRQC_TINT_START; + if (hwirq >=3D priv->info->tint_start && hwirq < priv->info->num_irq) { + u32 offset =3D hwirq - priv->info->tint_start; u32 tssr_offset =3D TSSR_OFFSET(offset); u8 tssr_index =3D TSSR_INDEX(offset); u32 reg; @@ -261,9 +262,9 @@ static void rzg2l_tint_irq_endisable(struct irq_data *d= , bool enable) struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); unsigned int hw_irq =3D irqd_to_hwirq(d); =20 - if (hw_irq >=3D IRQC_TINT_START && hw_irq < priv->info->num_irq) { + if (hw_irq >=3D priv->info->tint_start && hw_irq < priv->info->num_irq) { struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); - u32 offset =3D hw_irq - IRQC_TINT_START; + u32 offset =3D hw_irq - priv->info->tint_start; u32 tssr_offset =3D TSSR_OFFSET(offset); u8 tssr_index =3D TSSR_INDEX(offset); u32 reg; @@ -354,7 +355,7 @@ static int rzg2l_tint_set_edge(struct irq_data *d, unsi= gned int type) { struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); unsigned int hwirq =3D irqd_to_hwirq(d); - u32 titseln =3D hwirq - IRQC_TINT_START; + u32 titseln =3D hwirq - priv->info->tint_start; u32 tssr_offset =3D TSSR_OFFSET(titseln); u8 tssr_index =3D TSSR_INDEX(titseln); u8 index, sense; @@ -401,7 +402,7 @@ static int rzg2l_irqc_set_type(struct irq_data *d, unsi= gned int type) =20 if (hw_irq >=3D IRQC_IRQ_START && hw_irq <=3D IRQC_IRQ_COUNT) ret =3D rzg2l_irq_set_type(d, type); - else if (hw_irq >=3D IRQC_TINT_START && hw_irq < priv->info->num_irq) + else if (hw_irq >=3D priv->info->tint_start && hw_irq < priv->info->num_i= rq) ret =3D rzg2l_tint_set_edge(d, type); if (ret) return ret; @@ -503,7 +504,7 @@ static int rzg2l_irqc_alloc(struct irq_domain *domain, = unsigned int virq, tint =3D TINT_EXTRACT_GPIOINT(hwirq); hwirq =3D TINT_EXTRACT_HWIRQ(hwirq); =20 - if (hwirq < IRQC_TINT_START) + if (hwirq < priv->info->tint_start) return -EINVAL; } =20 @@ -606,6 +607,7 @@ static int rzg2l_irqc_common_probe(struct platform_devi= ce *pdev, struct device_n } =20 static const struct rzg2l_hw_info rzg2l_hw_params =3D { + .tint_start =3D IRQC_IRQ_START + IRQC_IRQ_COUNT, .num_irq =3D IRQC_IRQ_START + IRQC_IRQ_COUNT + IRQC_TINT_COUNT, }; =20 --=20 2.43.0 From nobody Mon Feb 9 04:07:41 2026 Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E4AAA3A1A5F for ; Fri, 6 Feb 2026 11:17:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770376626; cv=none; b=q4DkxxU43YCI6KtyvWJMYkf+8QK5l+HBrUvwFhgrYyxkHnmDKh1mulyJcb8xK9R+qc8RB4QU9lshc3lKVovU0Q18+MK/WsQc05G0cD+HGlLIYOGnm/N0n8cIdaJkeet/RBJmxjS95Qb47clvU3u1BIOstQOI5AE0aD5P/dZsFUM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770376626; c=relaxed/simple; bh=3C74JNFXi3uKwy8kFvk6HfAp8K0Gq6R+KU/xJsdc5fA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=JDjfR2Lxr+YUVKtmvBvDjGIfIk7JIr68yzHLNrUXXo5eX5omAQ2Faa8g9uzZarDvy2PLRYMdP06+kKoTl2prrQ3LYdNHNcDgwtpuGSARhfeGR3nvP79lUjTWIBJijVr0WStqq+KtZmFbZuelWbcKy2nksY/flA90Wii6jZTVx7E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=L3ggPMsJ; arc=none smtp.client-ip=209.85.221.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="L3ggPMsJ" Received: by mail-wr1-f48.google.com with SMTP id ffacd0b85a97d-4359249bbacso1897549f8f.0 for ; Fri, 06 Feb 2026 03:17:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1770376624; x=1770981424; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1TFRvg3GiC3fTa3U71n08qAP9/3weHGAPlVvCNhEDkk=; b=L3ggPMsJhpa1PddOs2AJ7IS/tIuLPR/BzxJ8Z3MJV6goyQ0KScIXqmVcIx/z5Cg1jX rlSNUM6Xw5jPJ7Pw/390sn3QvY3BSKjiFHeIGRHzyZUp4WNwwfH1WCfQMUKYGEpCwydj LqrNS6EJezg0PY6+ybFgg7me1JT0SqvZ6cXsibGFhelZJLl8gAhUp7EmsAPS0Pr8zLQi tfjLjARhhca5rwqlcbsmdDknHDYMs4OEC/Q6PF25W/w4Xr0gC7FwLNNjdKZSmocfY2Oy nmnvrtgbut7i3Oz3ajw0I3A4fUL1JwO6BadGW1GO+WHlJssIZcTcj+lKMSKI5ym9FQ1p V1SQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770376624; x=1770981424; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=1TFRvg3GiC3fTa3U71n08qAP9/3weHGAPlVvCNhEDkk=; b=kvhZlURHf6xAKtrInrAmPGJ8yDroawABseSLFSvp67EM8+f4jJzOiUkcyp6yD///FT TAVROgXf8uDaHuZdyCoeJNtbephydv0Y82xrnw/FHm/b5fsQ007u7SmhNRCgeNn15dqp BQZeK1B7dxSE9uEJWjWRWNqjbkGcEtxUQZsrDxDUzL3YFn8Izlophy+IJQvCn3yi3shP 4U87GCFsKeRHQ+iWv0fwrhcLNIXDsDLfq2Fh/yBUinJt+i7OHxUPg1uplQ/FgPveL+gi lFzPrFKYU0AzbbfAWokm/T5OXcRrxTDNkiSalHdVF0q/RluPqKm75IGbOGUohRYzPCHY bDCw== X-Forwarded-Encrypted: i=1; AJvYcCWQLO4lMXBdcwAxkXTcKsb8fxcRf9JR2fvFCxXV3nn+a2xE/QwgnhYF3vOCqy84TDbTctzlnzQPuqkECvo=@vger.kernel.org X-Gm-Message-State: AOJu0YxuFuNo/U9o25s6Mf3lY5gvPi3Xwxr1DNdjYorTsPR46NrbdYoh B65nKFMCVs1cU1pmJ7JEGnideIbUTw/i7AbuL3XBf1MWdhR4d8uz81h8 X-Gm-Gg: AZuq6aIwO08jzJmpqhWKgCEXL/fW9J0dDXf0rbvfzIjgrJc9Gvz6TEz1bnuTV2plDnw fy69zmSoh/PiZtWE/Z2BcQoL6VeiN39Z/DGVrNs4C+JkSBl2DOzVSEtAxy+Zg4vVw4L8fGZHx4o oJQ/Wyfylkpm6SKurf46arg0dsQjMzLVAtVK1GOeW8dGOYSu4P4zE+knSJ1/2ByrvEFOx7rkjna BbbfRpjwgv4np8XwNCvAM+7EzG8vSE0R3AI0C46uEUWml0nCfGksh3B8R1pu8iwmXxha1tuBBLK GrYHL5DxgJmoBq2se0ZRRT06CiqisKk87xG6nxjGZWbtNPWY5xx2jEJmmiz7mG6eEV8O9tcrYSl R5gIOxYs73yvgEMpUtLWQGcB7hZsM03SxtPyeRCBCX1imY+/oNrH5duX8XF8o65nNec5SRFGRgd 0lKIZn5BUYcbkU/eMb5g== X-Received: by 2002:a05:6000:2306:b0:435:b674:c9b1 with SMTP id ffacd0b85a97d-4362903c4c0mr4529994f8f.11.1770376624214; Fri, 06 Feb 2026 03:17:04 -0800 (PST) Received: from biju.lan ([2a00:23c4:a758:8a01:1e64:f8d5:9d7a:19d4]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4362972fa4csm4746380f8f.26.2026.02.06.03.17.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Feb 2026 03:17:03 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Thomas Gleixner Cc: Biju Das , linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v3 6/9] irqchip/renesas-rzg2l: Drop IRQC_IRQ_COUNT macro Date: Fri, 6 Feb 2026 11:16:49 +0000 Message-ID: <20260206111658.231934-7-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260206111658.231934-1-biju.das.jz@bp.renesas.com> References: <20260206111658.231934-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The total number of External IRQs in RZ/G2L and RZ/G3L SoC are different. The RZ/G3L has 16 external IRQs where as RZ/G2L has only 8 external IRQ. Add irq_count variable in struct rzg2l_hw_info to handle this differences and drop the macro IRQC_IRQ_COUNT. Signed-off-by: Biju Das --- v2->v3: * No change v1->v2: * No change --- drivers/irqchip/irq-renesas-rzg2l.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-rene= sas-rzg2l.c index e5393306f610..0de7db45d4c8 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -21,7 +21,6 @@ #include =20 #define IRQC_IRQ_START 1 -#define IRQC_IRQ_COUNT 8 #define IRQC_TINT_COUNT 32 =20 #define ISCR 0x10 @@ -68,10 +67,12 @@ struct rzg2l_irqc_reg_cache { =20 /** * struct rzg2l_hw_info - Interrupt Control Unit controller hardware info = structure. + * @irq_count: Number of IRQC interrupts * @tint_start: Start of TINT interrupts * @num_irq: Total Number of interrupts */ struct rzg2l_hw_info { + u8 irq_count; u8 tint_start; u8 num_irq; }; @@ -144,7 +145,7 @@ static void rzg2l_irqc_eoi(struct irq_data *d) unsigned int hw_irq =3D irqd_to_hwirq(d); =20 raw_spin_lock(&priv->lock); - if (hw_irq >=3D IRQC_IRQ_START && hw_irq <=3D IRQC_IRQ_COUNT) + if (hw_irq >=3D IRQC_IRQ_START && hw_irq <=3D priv->info->irq_count) rzg2l_clear_irq_int(priv, hw_irq); else if (hw_irq >=3D priv->info->tint_start && hw_irq < priv->info->num_i= rq) rzg2l_clear_tint_int(priv, hw_irq); @@ -190,7 +191,7 @@ static void rzfive_irqc_mask(struct irq_data *d) unsigned int hwirq =3D irqd_to_hwirq(d); =20 raw_spin_lock(&priv->lock); - if (hwirq >=3D IRQC_IRQ_START && hwirq <=3D IRQC_IRQ_COUNT) + if (hwirq >=3D IRQC_IRQ_START && hwirq <=3D priv->info->irq_count) rzfive_irqc_mask_irq_interrupt(priv, hwirq); else if (hwirq >=3D priv->info->tint_start && hwirq < priv->info->num_irq) rzfive_irqc_mask_tint_interrupt(priv, hwirq); @@ -204,7 +205,7 @@ static void rzfive_irqc_unmask(struct irq_data *d) unsigned int hwirq =3D irqd_to_hwirq(d); =20 raw_spin_lock(&priv->lock); - if (hwirq >=3D IRQC_IRQ_START && hwirq <=3D IRQC_IRQ_COUNT) + if (hwirq >=3D IRQC_IRQ_START && hwirq <=3D priv->info->irq_count) rzfive_irqc_unmask_irq_interrupt(priv, hwirq); else if (hwirq >=3D priv->info->tint_start && hwirq < priv->info->num_irq) rzfive_irqc_unmask_tint_interrupt(priv, hwirq); @@ -400,7 +401,7 @@ static int rzg2l_irqc_set_type(struct irq_data *d, unsi= gned int type) unsigned int hw_irq =3D irqd_to_hwirq(d); int ret =3D -EINVAL; =20 - if (hw_irq >=3D IRQC_IRQ_START && hw_irq <=3D IRQC_IRQ_COUNT) + if (hw_irq >=3D IRQC_IRQ_START && hw_irq <=3D priv->info->irq_count) ret =3D rzg2l_irq_set_type(d, type); else if (hw_irq >=3D priv->info->tint_start && hw_irq < priv->info->num_i= rq) ret =3D rzg2l_tint_set_edge(d, type); @@ -500,7 +501,7 @@ static int rzg2l_irqc_alloc(struct irq_domain *domain, = unsigned int virq, * from 16-31 bits. TINT from the pinctrl driver needs to be programmed * in IRQC registers to enable a given gpio pin as interrupt. */ - if (hwirq > IRQC_IRQ_COUNT) { + if (hwirq > priv->info->irq_count) { tint =3D TINT_EXTRACT_GPIOINT(hwirq); hwirq =3D TINT_EXTRACT_HWIRQ(hwirq); =20 @@ -607,8 +608,9 @@ static int rzg2l_irqc_common_probe(struct platform_devi= ce *pdev, struct device_n } =20 static const struct rzg2l_hw_info rzg2l_hw_params =3D { - .tint_start =3D IRQC_IRQ_START + IRQC_IRQ_COUNT, - .num_irq =3D IRQC_IRQ_START + IRQC_IRQ_COUNT + IRQC_TINT_COUNT, + .irq_count =3D 8, + .tint_start =3D IRQC_IRQ_START + 8, + .num_irq =3D IRQC_IRQ_START + 8 + IRQC_TINT_COUNT, }; =20 static int rzg2l_irqc_probe(struct platform_device *pdev, struct device_no= de *parent) --=20 2.43.0 From nobody Mon Feb 9 04:07:41 2026 Received: from mail-wr1-f45.google.com (mail-wr1-f45.google.com [209.85.221.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 82B823A1E63 for ; Fri, 6 Feb 2026 11:17:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770376626; cv=none; b=s/bgQNvCL/KxE5ijYME/efM0vuBm9a3J5XC1ODwVi6ZAsHllNEiFYuy2gUU9H6rfMMH2iO4RnAnKXDtSvW+YUkb1Py2LzBNL8kt+895RmV/rWBipoc78g3ZJIJGr0D2fsiMgTvZ7Zvz8rzSz7t2fA1gzov0rmTiwJM42n9iDrgQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770376626; c=relaxed/simple; bh=vuj8A8gInyVOoPQEbw+wDwkjQav4BmP98QD0xl0JRR4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ImlCz/jrVjmfoPCZohby2rTekdlPZ7bDvPbODM6XOKMjb9PvHVH2inthvtQ+PFzDPyzJxjOYp/z7r3AM6RzYOyQt1HU8tdnlRIC0xmIevXdb4cHykqRuph16VYck4qe0pBxRVENF7ehq/0/y26KbQEE6EYSVa5kwXHV5LbEzbXQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=hqTmfG0x; arc=none smtp.client-ip=209.85.221.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="hqTmfG0x" Received: by mail-wr1-f45.google.com with SMTP id ffacd0b85a97d-435f177a8f7so611154f8f.1 for ; Fri, 06 Feb 2026 03:17:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1770376625; x=1770981425; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IczN5ipnnJMcQcEavsKqC9A8Jd1PQep+78i4Emgw8gU=; b=hqTmfG0xeIH9aOwRTJScZXeXJIhxnO0wRXJJ2MpYI+8YG5XmF8zgt/Gvck6hTuR+uc rVkBFeAjRJXer6lQMR6B7+USG3Om4dwkNdVc1VPXWf4dTtgBgtYo+5tHpXouo7td/elo xMN0xBr+PhZpXb+QM60PtAdR7LGdMYAt2lNrPh0pDg5u/Pswg2LWD9LbTQeqobL/XcAt D84E6OoNkaYEB3uOa8eQvEsUhCjAZLfaloXBysGfnEC9qmpkDdYaSkgkS5sifGPIIFMd aldscpXjzb6ufCfHGRLW39lnFPZIlh5yAY/ktN7Xy6DQ8tcPx7zeL12Ty06rTN/c/oTf HNaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770376625; x=1770981425; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=IczN5ipnnJMcQcEavsKqC9A8Jd1PQep+78i4Emgw8gU=; b=KD0l2y3c5hkOTLuDW3ERtrTVDN7KmndjpO5Fjv6raOKU8Omqwv167R1fqqzbyQflxr lAbcQTQPJvB9ipDZkElpJAK81bDwbAbzAaHS48u/ARszWEDschqtmUzTB1oFAXjZ1JG3 9H7v0WWjdVEURmAYJHLdQE/iiaS0T9I5+wdKhCoo7/w36plKAt9J1oE0MamaaOKDRlGG 8dWx6Tt0yaa3yg6A2w8eO+UIQTXSTSTPzcbnOx+GCu9MKB0CF65PQ6Zo4K8pQmqI4PG2 gPbTwODHuRwlqYG6yg/veumM9JA60pljeeaKNSvPyIbbhLJuAgZTB7/+9dssFu4ZboBs oNew== X-Forwarded-Encrypted: i=1; AJvYcCWWTxAtABBcXpPNEhT2aNppXlUIbVzmhmXI2fhMkGm1F07GU0l0INWTouV1bLoPf0CvEfIOTF1CBz54bCU=@vger.kernel.org X-Gm-Message-State: AOJu0YyGj1cR7n/3p5dCwmKLv2au5wAs+RxIOwQDzb6isIgdXPCm9p9e TMRP+i+LFyPz16IcxIaVEEev7c4+XYZzjgzoy4oEwyWvTP97LlcdyCRV X-Gm-Gg: AZuq6aIv73gMpJ0GtoCsEGvzRabexamGLtfA1b56EuT+wd3+pK9gqM9Nz3NUSAyqh0S 7yPmjHcbx+4+xqVl94ljtSQMWWVdH3DMrnNAVVcvfuQOG2WhSatiDEx3Hbos7cH2urH19EraPXw iedLSxCn8l/mj1MANLEr4qX49/Wtb3d7Upi0CgmSmjlhib8x33InWlTwWT1K04A7GUzi21xTpYr kCr2XJJj/e2o/HNevv5meGeWm9gnJYCbS18wLDmeMXcXl6Yf0IDvIQMvVnLA7hLZ25HAGFXsFV7 /vUX95CddOlGvBWB7oENshwTrow3FAv6deTLgddrpqbzfTQILNAVBx3bZv3PEhcgB/2G+GDUXnQ toYoAHFLMHsMrawkvwveW3fNKh1BN54+9wr8tqFJdvmNUo71Bd/+3rWAEPvvGi6+BEyClSuWNd1 CX8KA7arfrfuI0u6aU0A== X-Received: by 2002:a05:6000:250a:b0:435:b089:4f46 with SMTP id ffacd0b85a97d-4362938c2f5mr3766118f8f.50.1770376624798; Fri, 06 Feb 2026 03:17:04 -0800 (PST) Received: from biju.lan ([2a00:23c4:a758:8a01:1e64:f8d5:9d7a:19d4]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4362972fa4csm4746380f8f.26.2026.02.06.03.17.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Feb 2026 03:17:04 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Thomas Gleixner Cc: Biju Das , linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v3 7/9] irqchip/renesas-rzg2l: Add RZ/G3L support Date: Fri, 6 Feb 2026 11:16:50 +0000 Message-ID: <20260206111658.231934-8-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260206111658.231934-1-biju.das.jz@bp.renesas.com> References: <20260206111658.231934-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The IRQC block on the RZ/G3L SoC is almost identical to the one found on the RZ/G2L SoC, with the following differences: - The number of GPIO interrupts for TINT selection is 113 instead of 123. - The pin index and TINT selection index are not in the 1:1 map. - The number of External IRQ is 16 instead of 8, out of this 8 IRQs are shared with TINT. Add support for the RZ/G3L driver by filling the rzg2l_hw_info table and adding LUT for mapping between pin index and TINT selection index. Signed-off-by: Biju Das --- v2->v3: * No change v1->v2: * No change --- drivers/irqchip/irq-renesas-rzg2l.c | 47 +++++++++++++++++++++++++++-- 1 file changed, 44 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-rene= sas-rzg2l.c index 0de7db45d4c8..06c439c98ff5 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -67,14 +67,16 @@ struct rzg2l_irqc_reg_cache { =20 /** * struct rzg2l_hw_info - Interrupt Control Unit controller hardware info = structure. + * @tssel_lut: TINT lookup table * @irq_count: Number of IRQC interrupts * @tint_start: Start of TINT interrupts * @num_irq: Total Number of interrupts */ struct rzg2l_hw_info { - u8 irq_count; - u8 tint_start; - u8 num_irq; + const u8 *tssel_lut; + u8 irq_count; + u8 tint_start; + u8 num_irq; }; =20 /** @@ -343,6 +345,9 @@ static u32 rzg2l_disable_tint_and_set_tint_source(struc= t irq_data *d, struct rzg u32 tint =3D (u32)(uintptr_t)irq_data_get_irq_chip_data(d); u32 tien =3D reg & (TIEN << TSSEL_SHIFT(tssr_offset)); =20 + if (priv->info->tssel_lut) + tint =3D priv->info->tssel_lut[tint]; + /* Clear the relevant byte in reg */ reg &=3D ~(TSSEL_MASK << TSSEL_SHIFT(tssr_offset)); /* Set TINT and leave TIEN clear */ @@ -607,6 +612,36 @@ static int rzg2l_irqc_common_probe(struct platform_dev= ice *pdev, struct device_n return 0; } =20 +/* Mapping based on port index on Table 4.2-1 and GPIOINT on Table 4.6-7 */ +static const u8 rzg3l_tssel_lut[] =3D { + 83, 84, /* P20-P21 */ + 7, 8, 9, 10, 11, 12, 13, /* P30-P36 */ + 85, 86, 87, 88, 89, 90, 91, /* P50-P56 */ + 92, 93, 94, 95, 96, 97, 98, /* P60-P66 */ + 99, 100, 101, 102, 103, 104, 105, 106, /* P70-P77 */ + 107, 108, 109, 110, 111, 112, /* P80-P85 */ + 45, 46, 47, 48, 49, 50, 51, 52, /* PA0-PA7 */ + 53, 54, 55, 56, 57, 58, 59, 60, /* PB0-PB7 */ + 61, 62, 63, /* PC0-PC2 */ + 64, 65, 66, 67, 68, 69, 70, 71, /* PD0-PD7 */ + 72, 73, 74, 75, 76, 77, 78, 79, /* PE0-PE7 */ + 80, 81, 82, /* PF0-PF2 */ + 27, 28, 29, 30, 31, 32, 33, 34, /* PG0-PG7 */ + 35, 36, 37, 38, 39, 40, /* PH0-PH5 */ + 2, 3, 4, 5, 6, /* PJ0-PJ4 */ + 41, 42, 43, 44, /* PK0-PK3 */ + 14, 15, 16, 17, 26, /* PL0-PL4 */ + 18, 19, 20, 21, 22, 23, 24, 25, /* PM0-PM7 */ + 0, 1 /* PS0-PS1 */ +}; + +static const struct rzg2l_hw_info rzg3l_hw_params =3D { + .tssel_lut =3D rzg3l_tssel_lut, + .irq_count =3D 16, + .tint_start =3D IRQC_IRQ_START + 16, + .num_irq =3D IRQC_IRQ_START + 16 + IRQC_TINT_COUNT, +}; + static const struct rzg2l_hw_info rzg2l_hw_params =3D { .irq_count =3D 8, .tint_start =3D IRQC_IRQ_START + 8, @@ -618,6 +653,11 @@ static int rzg2l_irqc_probe(struct platform_device *pd= ev, struct device_node *pa return rzg2l_irqc_common_probe(pdev, parent, &rzg2l_irqc_chip, &rzg2l_hw_= params); } =20 +static int rzg3l_irqc_probe(struct platform_device *pdev, struct device_no= de *parent) +{ + return rzg2l_irqc_common_probe(pdev, parent, &rzg2l_irqc_chip, &rzg3l_hw_= params); +} + static int rzfive_irqc_probe(struct platform_device *pdev, struct device_n= ode *parent) { return rzg2l_irqc_common_probe(pdev, parent, &rzfive_irqc_chip, &rzg2l_hw= _params); @@ -625,6 +665,7 @@ static int rzfive_irqc_probe(struct platform_device *pd= ev, struct device_node *p =20 IRQCHIP_PLATFORM_DRIVER_BEGIN(rzg2l_irqc) IRQCHIP_MATCH("renesas,rzg2l-irqc", rzg2l_irqc_probe) +IRQCHIP_MATCH("renesas,r9a08g046-irqc", rzg3l_irqc_probe) IRQCHIP_MATCH("renesas,r9a07g043f-irqc", rzfive_irqc_probe) IRQCHIP_PLATFORM_DRIVER_END(rzg2l_irqc) MODULE_AUTHOR("Lad Prabhakar "); --=20 2.43.0 From nobody Mon Feb 9 04:07:41 2026 Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F23FD39E6EF for ; Fri, 6 Feb 2026 11:17:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770376627; cv=none; b=NVU7zuipX2eWU/iA8kdheDir7uBaesLoSTpM5DlWYA6WYf+YdItBo/7F18+CGICMK4rPZescS7WzPSSEZSoGfu1IOdAFDhRP7e6IUTAJAl/BbYpc0Aapk+bMkdbwd6+tlOnwfBpsA90vcsYMJ6BP0xaACKFPXLzNSjzFN/+t6n8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770376627; c=relaxed/simple; bh=6EPlJdo2gZRs8EUreDsfLms5hWGVCHL4BYg3hBgBLvI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=N9ZQF9gPkH50JE55EMOkGBLi1ED1MZd9MYSnllfQTURWRrY6Zyc7cSw9GO+heWhEYbVew+TIGuUwo3TRpXkgrPpRJyiGFSMM07GsVreOXcJB95QXYVXTZrG/fomzhzVDia992nmM0O46nKwIFcNz2I9tuOlBi6K1gMepthH8Uj0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=BHVKtopZ; arc=none smtp.client-ip=209.85.221.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="BHVKtopZ" Received: by mail-wr1-f48.google.com with SMTP id ffacd0b85a97d-436263e31abso1282035f8f.1 for ; Fri, 06 Feb 2026 03:17:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1770376625; x=1770981425; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Aj0KFAWYI0f2ECDUwq96InOmBNkVC0SFMlpUZPJRFIU=; b=BHVKtopZSXcM/3EPyARktKYRCOaiJ7zhaWQ5Q0W9t8ifLyZIeaRY/j9TMIGrozfygD LQhlYclO5K3AEMr2mjYnDpaNClOuDYM+2I4LBIU0c2MIdxS6MJAvejuXnkzPHmDxiSin pYhCXxt/TFVvIeYmWF/YhnW5mMlD/NnpNG//Lf824zoEr2ngrwXYy/E9w/OjgIK0zn9v S7jpwxpqbWkCkG2xvniapQIQVZDI6u1aVaypt5lHeVO9xgt+q/T4vhKg2zb+xE5BvNuL 12if6PbHd3R2GwEY75tUU+0u+zuiWheBKOwgTUEBpN4G3Ca5UIfCS3nCmmugDn9PUCnk 8FPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770376625; x=1770981425; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=Aj0KFAWYI0f2ECDUwq96InOmBNkVC0SFMlpUZPJRFIU=; b=fiv9SDqHFNPBKuLkIo8j6aLXA4NeF4WmbOMhBkpMnccCICup4lvEHTeDlaVcxcJIER umLNaUFNf8Ghl2v/HkmbCKXKAfkcyk6EITEB7BTmLEfPVoG5zj7+HR/03EvrPdUp54Dp 29eWPXxTVYnBdeZBKt6NiNwTKsmlaxKDkhDh+gAuJVF3+c+/fS8sdN98SuLSaoZWq5cm 82R5l393Gkz6sQJsCmB4biqYUMRZ5hISTlKhrT0B7G+orE/WgAIb3AwjnO9x75QAgFzh Dzk6DcsfgUkM6dBgfceTAMWNn/FGl52wiheMfE2WHhzdq4yO+0qZ+tEl7PBn/ZuNMgZ1 rSng== X-Forwarded-Encrypted: i=1; AJvYcCXhCqkBH1jJaJpv/TTTtfBGC0KTK5oQmmnGODLL9/f8NUyP9JzqYgIYq0Mi1qaLyZTYOODfJEhCEXmtWq4=@vger.kernel.org X-Gm-Message-State: AOJu0YwsStfSi5e15JLSYhpOlM25tSQ9eBYX4IqN1XNDIrSaEoxb3no+ MmQK8DwNoIFObwXcPeOJBLoI2y92zoOOsXqTyAZY5JvmQHkwk9sUl6hp X-Gm-Gg: AZuq6aK1V9DrThyRx0DpllDMiRtOsNFJkc7s1B/e2v4O4LgJvBuAnZRf9+VpxAsMeMh VL3+n1Y1XYBgDeMwQc5itNLlBsW5VIoPmXwMogpFUEev+a4/I9LbjgtShajP4avxErSnppQjnEX aBb2wEtsaSm0QhsqFSC9/5JU6bXCXgiq9tmW4qKO7zL+G8AO6ybEE6mtcqLYbIKI15ggf85arb7 hUv3dZMRdSAS0YwS6/FnmG0UeJbBeHNnjlUXK8Nr3kBkz7axNzkuQt1+1PeddrCXrR1l9+8Hn4Y vwG2pBl822Cus7vPURRlfwuLrKncGrv75YjEvROGNuamhP5SXXpqF0E26JmYIv1BQb1TXVxh4ev AL5fwD2CuuSy0MnN905VHNLI+v3TK4ZlgMIfNaIL3GcIijgsI8CDrEbY5NjqFOcxpQXtSF6IeUf 38DrnmJhhsxh5s6pSadQ== X-Received: by 2002:a05:6000:2285:b0:427:526:16aa with SMTP id ffacd0b85a97d-436293b6ae1mr3468731f8f.58.1770376625282; Fri, 06 Feb 2026 03:17:05 -0800 (PST) Received: from biju.lan ([2a00:23c4:a758:8a01:1e64:f8d5:9d7a:19d4]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4362972fa4csm4746380f8f.26.2026.02.06.03.17.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Feb 2026 03:17:05 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Thomas Gleixner Cc: Biju Das , linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v3 8/9] irqchip/renesas-rzg2l: Add shared irq support Date: Fri, 6 Feb 2026 11:16:51 +0000 Message-ID: <20260206111658.231934-9-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260206111658.231934-1-biju.das.jz@bp.renesas.com> References: <20260206111658.231934-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The total number of External IRQs in RZ/G2L and RZ/G3L SoC are different. The RZ/G3L has 16 external IRQs out of which it shares 8 IRQs with TINT, where as RZ/G2L has only 8 external IRQ. Add shared_irq variable in struct rzg2l_hw_info to handle this differences by adding the callback irq_{request,release}_resources(). Signed-off-by: Biju Das --- v2->v3: * No change v1->v2: * No change --- drivers/irqchip/irq-renesas-rzg2l.c | 94 +++++++++++++++++++++++++++++ 1 file changed, 94 insertions(+) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-rene= sas-rzg2l.c index 06c439c98ff5..59108e1d53ec 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -29,6 +29,8 @@ #define TITSR(n) (0x24 + (n) * 4) #define TITSR0_MAX_INT 16 #define TITSEL_WIDTH 0x2 +#define INTTSEL 0x2c +#define TINTSEL(n) BIT(n) #define TSSR(n) (0x30 + ((n) * 4)) #define TIEN BIT(7) #define TSSEL_SHIFT(n) (8 * (n)) @@ -58,10 +60,12 @@ /** * struct rzg2l_irqc_reg_cache - registers cache (necessary for suspend/re= sume) * @iitsr: IITSR register + * @inttsel: INTTSEL register * @titsr: TITSR registers */ struct rzg2l_irqc_reg_cache { u32 iitsr; + u32 inttsel; u32 titsr[2]; }; =20 @@ -71,12 +75,14 @@ struct rzg2l_irqc_reg_cache { * @irq_count: Number of IRQC interrupts * @tint_start: Start of TINT interrupts * @num_irq: Total Number of interrupts + * @shared_irq_cnt: Number of shared interrupts */ struct rzg2l_hw_info { const u8 *tssel_lut; u8 irq_count; u8 tint_start; u8 num_irq; + u8 shared_irq_cnt; }; =20 /** @@ -295,6 +301,87 @@ static void rzg2l_irqc_irq_enable(struct irq_data *d) irq_chip_enable_parent(d); } =20 +static bool rzg2l_irqc_is_shared_irqc(const struct rzg2l_hw_info *info, un= signed int hw_irq) +{ + return ((hw_irq >=3D (info->tint_start - info->shared_irq_cnt)) && + hw_irq < info->tint_start); +} + +static bool rzg2l_irqc_is_shared_tint(const struct rzg2l_hw_info *info, un= signed int hw_irq) +{ + return ((hw_irq >=3D (info->num_irq - info->shared_irq_cnt)) && + hw_irq < info->num_irq); +} + +static int rzg2l_irqc_irq_request_resources(struct irq_data *d) +{ + unsigned int hw_irq =3D irqd_to_hwirq(d); + struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); + const struct rzg2l_hw_info *info =3D priv->info; + u32 offset, tssr_offset; + u8 tssr_index, tssel_shift; + u32 reg, inttsel_reg; + u8 value; + + if (!info->shared_irq_cnt) + return 0; + + if (rzg2l_irqc_is_shared_irqc(info, hw_irq)) { + offset =3D hw_irq + IRQC_TINT_COUNT - info->tint_start; + tssr_offset =3D TSSR_OFFSET(offset); + tssr_index =3D TSSR_INDEX(offset); + tssel_shift =3D TSSEL_SHIFT(tssr_offset); + + reg =3D readl_relaxed(priv->base + TSSR(tssr_index)); + value =3D (reg & (TIEN << tssel_shift)) >> tssel_shift; + if (value) + goto err_conflict; + + raw_spin_lock(&priv->lock); + inttsel_reg =3D readl_relaxed(priv->base + INTTSEL); + inttsel_reg |=3D TINTSEL(offset); + writel_relaxed(inttsel_reg, priv->base + INTTSEL); + raw_spin_unlock(&priv->lock); + } else if (rzg2l_irqc_is_shared_tint(info, hw_irq)) { + offset =3D hw_irq - info->tint_start; + tssr_offset =3D TSSR_OFFSET(offset); + tssr_index =3D TSSR_INDEX(offset); + + inttsel_reg =3D readl_relaxed(priv->base + INTTSEL); + value =3D (inttsel_reg & TINTSEL(offset)) >> offset; + if (value) + goto err_conflict; + } + + return 0; + +err_conflict: + pr_err("%s: Shared SPI conflict!\n", __func__); + return -EBUSY; +} + +static void rzg2l_irqc_irq_release_resources(struct irq_data *d) +{ + unsigned int hw_irq =3D irqd_to_hwirq(d); + struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); + const struct rzg2l_hw_info *info =3D priv->info; + u32 offset; + u8 inttsel_reg; + + if (!priv->info->shared_irq_cnt) + return; + + if (rzg2l_irqc_is_shared_irqc(info, hw_irq)) { + offset =3D hw_irq + IRQC_TINT_COUNT - info->tint_start; + + raw_spin_lock(&priv->lock); + inttsel_reg =3D readl_relaxed(priv->base + INTTSEL); + inttsel_reg &=3D ~TINTSEL(offset); + writel_relaxed(inttsel_reg, priv->base + INTTSEL); + raw_spin_unlock(&priv->lock); + } +} + static int rzg2l_irq_set_type(struct irq_data *d, unsigned int type) { struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); @@ -422,6 +509,8 @@ static int rzg2l_irqc_irq_suspend(void *data) void __iomem *base =3D rzg2l_irqc_data->base; =20 cache->iitsr =3D readl_relaxed(base + IITSR); + if (rzg2l_irqc_data->info->shared_irq_cnt) + cache->inttsel =3D readl_relaxed(base + INTTSEL); for (u8 i =3D 0; i < 2; i++) cache->titsr[i] =3D readl_relaxed(base + TITSR(i)); =20 @@ -440,6 +529,8 @@ static void rzg2l_irqc_irq_resume(void *data) */ for (u8 i =3D 0; i < 2; i++) writel_relaxed(cache->titsr[i], base + TITSR(i)); + if (rzg2l_irqc_data->info->shared_irq_cnt) + writel_relaxed(cache->inttsel, base + INTTSEL); writel_relaxed(cache->iitsr, base + IITSR); } =20 @@ -459,6 +550,8 @@ static const struct irq_chip rzg2l_irqc_chip =3D { .irq_unmask =3D irq_chip_unmask_parent, .irq_disable =3D rzg2l_irqc_irq_disable, .irq_enable =3D rzg2l_irqc_irq_enable, + .irq_request_resources =3D rzg2l_irqc_irq_request_resources, + .irq_release_resources =3D rzg2l_irqc_irq_release_resources, .irq_get_irqchip_state =3D irq_chip_get_parent_state, .irq_set_irqchip_state =3D irq_chip_set_parent_state, .irq_retrigger =3D irq_chip_retrigger_hierarchy, @@ -640,6 +733,7 @@ static const struct rzg2l_hw_info rzg3l_hw_params =3D { .irq_count =3D 16, .tint_start =3D IRQC_IRQ_START + 16, .num_irq =3D IRQC_IRQ_START + 16 + IRQC_TINT_COUNT, + .shared_irq_cnt =3D 8, }; =20 static const struct rzg2l_hw_info rzg2l_hw_params =3D { --=20 2.43.0 From nobody Mon Feb 9 04:07:41 2026 Received: from mail-wr1-f53.google.com (mail-wr1-f53.google.com [209.85.221.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A86043A0B1E for ; Fri, 6 Feb 2026 11:17:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770376628; cv=none; b=CsHclLOB1FNmeEMEjZ0P3K1QbDZsWHzUDbA5tRGSoIE3O9uUyU3f/fJEGbv6TM2qm3almH/xbxQGYrJoZZAfn4Vj0RUBmkh/kJ9xT1BQZ/LDaIlOqwcu7WgKnogr7+fGpKNF81Lte1EFK6g/5TwhjUWlV8TzNR9BKHjPBpR3rvc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770376628; c=relaxed/simple; bh=tBM2nmg/2U5P0LgRdBpw2K7UPVYyHeWowsAhG6bCy9U=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=iKHDYACBS3kRE/R+rpQaDwdVnzC6T1j8t7cze5GvQhFdR/tViovUESkFhv9nw9UHyyQPz/ssDjYH7ngYuZ61FZlc0BrcxXMmZqk/efvOBfjLdR5269L3UItOGak6PeUg/W2PpTHVgsnGf+3Pulw7iM71iF1Hky9solpIOBrnB+4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=CKOE6Hlv; arc=none smtp.client-ip=209.85.221.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="CKOE6Hlv" Received: by mail-wr1-f53.google.com with SMTP id ffacd0b85a97d-43284ed32a0so1272563f8f.3 for ; Fri, 06 Feb 2026 03:17:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1770376626; x=1770981426; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=64n8Vlh4nTpDgDDej9deHW1DSroc4CwLe6rBZznILz4=; b=CKOE6HlvHX5qmdHWA+6UneMe0vP4DmxMD1Fx9KMmbgCvBwuqZqb+AU0Z9Nki0QD7ho Sx0ACAuAMOMGwM/PFyYpQJtIxoJmpEsGjqD3H1J8EDW+whLEODtz+zkXF0UUDGWQoLim mwKdT1k/PziJ6FCGoOthGIZeeHIfeFY+xXP2FJrtlrucqWJAps98oxzNTPaGx14Y7A6x ocrWmgljukPI5pgaguMXLA3xsVSNBSAjKJhx/9BUT8PvU6tyIdMepL+Sv1V89/petHq/ dRvug4GWLjgIcc0fy1FtiayfolkOwy4eZtGM+GX5XEgAR0jDxx8IZpjN8L+lWi+0efRg zWUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770376626; x=1770981426; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=64n8Vlh4nTpDgDDej9deHW1DSroc4CwLe6rBZznILz4=; b=sy9CXD8dEQTKMQuRQvqpzunw7F3blsTkXJjyIeT9KgwjEekBQmdoxqKGSx+wVuA7af eT2SSrv3TwTy3Nvg9OFFXsd+Of+YvfHhQAA0Yl+zo0Q3RhhJgwYWXMK33M4KxFQLWPNb CpvaGO1PmzAInzYrpWK2K45r132AkbDrrUaZX1wWwjMSRmVR+FF7qqxZfWNZOWFUr51y AKLyP5WFODQzwhyWWF9nEGedxI7361QsTlDMzgUiNXlDA4Eyf4ncMg65QWCoFLouLF49 McS/4B4vumNLDDOTq4/J0ML6U3UY8kLUWFQwmRcX51JExZ8VoPz/APy/bU6QsVdFWmFq /a8w== X-Forwarded-Encrypted: i=1; AJvYcCWbhk73+HmMy9sgtc5r3kkN6REGukDMqk48I0YJ6GS1Efoy9lI67PFN1aKUwJk7zPUjlvuHAToFGHOV/Zo=@vger.kernel.org X-Gm-Message-State: AOJu0YyLHiGG2d5M5VlciO4xJ5cM8DJDifi5RMLnMPygCRaQU+RRfGIS 3/he3B+i1SvOYlo9MdG0Kctzcb6vy0g3XmYH4BFNVldOFEjZTAqA53BY X-Gm-Gg: AZuq6aIWwRvjuyaIiSy846ARabbxu8OSi5o1s0A99uyMT5Yj0SepGQlrdUisQsNztR4 zadjXL3cLAFzEQzjrREddVDLWRoUp8LHux4bIHH2yiBgAi5+mG0VCM7R7SZKtqfgyPYDSdV9eN2 8zQzDeAW3j4eTE39Vn3UX6Xrrr1xzdLKOGO/mVtyN9M0gQO6BviRhQVI02+d02hR75Ld7gwkAWl WlPjpIVqRfpwcAVpVuIUCOvspj4Wwy5D9TNA2JQNtdJE0PtBZ4UVM+0UZwGqUi18+4bvE+DpnCF PT7h8vvKbPlCET4sVL0jSD0lgmcMGpc8SvDN5N9SAOjHmF/9plK8kIjKKgWfuDTb4k8ML+kWAR/ wjD/igTDngfBS0nTGCzWkltjZKXV932zWDPqEJoMLJ66MOGGGbIyZOck9i7JiaWWkE4yBE9u48X uRlwKBfXiydIKMpv3K9g== X-Received: by 2002:a05:6000:220c:b0:436:7d3:b953 with SMTP id ffacd0b85a97d-4362933caf0mr4285699f8f.5.1770376625895; Fri, 06 Feb 2026 03:17:05 -0800 (PST) Received: from biju.lan ([2a00:23c4:a758:8a01:1e64:f8d5:9d7a:19d4]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4362972fa4csm4746380f8f.26.2026.02.06.03.17.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Feb 2026 03:17:05 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v3 9/9] arm64: dts: renesas: r9a08g046: Add ICU node Date: Fri, 6 Feb 2026 11:16:52 +0000 Message-ID: <20260206111658.231934-10-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260206111658.231934-1-biju.das.jz@bp.renesas.com> References: <20260206111658.231934-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add interrupt control node to RZ/G3L ("R9A08G046") SoC DTSI and add icu as interrupt-parent of pincontrol. Signed-off-by: Biju Das --- This patch depend upon [1] [1] https://lore.kernel.org/linux-renesas-soc/20260203131048.421708-9-biju.= das.jz@bp.renesas.com/T/#u v2->v3: * No change v1->v2: * No change --- arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 91 ++++++++++++++++++++++ 1 file changed, 91 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/d= ts/renesas/r9a08g046.dtsi index a92a4e07cc10..65dfa145ef59 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi @@ -188,6 +188,7 @@ pinctrl: pinctrl@11030000 { gpio-ranges =3D <&pinctrl 0 0 232>; interrupt-controller; #interrupt-cells =3D <2>; + interrupt-parent =3D <&icu>; clocks =3D <&cpg CPG_MOD R9A08G046_GPIO_HCLK>; power-domains =3D <&cpg>; resets =3D <&cpg R9A08G046_GPIO_RSTN>, @@ -196,6 +197,96 @@ pinctrl: pinctrl@11030000 { reset-names =3D "rstn", "port", "spare"; }; =20 + icu: interrupt-controller@11050000 { + compatible =3D "renesas,r9a08g046-irqc"; + #interrupt-cells =3D <2>; + #address-cells =3D <0>; + interrupt-controller; + reg =3D <0 0x11050000 0 0x10000>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "nmi", + "irq0", "irq1", "irq2", "irq3", + "irq4", "irq5", "irq6", "irq7", + "irq8", "irq9", "irq10", "irq11", + "irq12", "irq13", "irq14", "irq15", + "tint0", "tint1", "tint2", "tint3", + "tint4", "tint5", "tint6", "tint7", + "tint8", "tint9", "tint10", "tint11", + "tint12", "tint13", "tint14", "tint15", + "tint16", "tint17", "tint18", "tint19", + "tint20", "tint21", "tint22", "tint23", + "tint24", "tint25", "tint26", "tint27", + "tint28", "tint29", "tint30", "tint31", + "bus-err", "ec7tie1-0", "ec7tie2-0", "ec7tiovf-0", + "ovfunf0", "ovfunf1", "ovfunf2", "ovfunf3", + "ovfunf4", "ovfunf5", "ovfunf6", "ovfunf7"; + clocks =3D <&cpg CPG_MOD R9A08G046_IA55_CLK>, + <&cpg CPG_MOD R9A08G046_IA55_PCLK>; + clock-names =3D "clk", "pclk"; + power-domains =3D <&cpg>; + resets =3D <&cpg R9A08G046_IA55_RESETN>; + }; + dmac: dma-controller@11820000 { compatible =3D "renesas,r9a08g046-dmac", "renesas,rz-dmac"; reg =3D <0 0x11820000 0 0x10000>, --=20 2.43.0