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Thu, 05 Feb 2026 23:55:21 -0800 (PST) From: lukagejak5@gmail.com X-Google-Original-From: luka.gejak@linux.dev To: Greg Kroah-Hartman Cc: Dan Carpenter , linux-staging@lists.linux.dev, linux-kernel@vger.kernel.org, Luka Gejak Subject: [PATCH v2 18/26] staging: rtl8723bs: hal: fix line lengths in rtl8723b_phycfg.c Date: Fri, 6 Feb 2026 08:54:31 +0100 Message-ID: <20260206075439.103287-19-luka.gejak@linux.dev> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260206075439.103287-1-luka.gejak@linux.dev> References: <20260206075439.103287-1-luka.gejak@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Luka Gejak Break long lines exceeding 100 characters to comply with kernel coding style. Signed-off-by: Luka Gejak --- .../staging/rtl8723bs/hal/rtl8723b_phycfg.c | 54 +++++++++++++------ 1 file changed, 37 insertions(+), 17 deletions(-) diff --git a/drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c b/drivers/stag= ing/rtl8723bs/hal/rtl8723b_phycfg.c index 6d5e531505f9..4f171c065155 100644 --- a/drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c +++ b/drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c @@ -109,18 +109,26 @@ static u32 phy_RFSerialRead_8723B( NewOffset =3D Offset; =20 if (eRFPath =3D=3D RF_PATH_A) { - tmplong2 =3D PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhy= Set, bMaskDWord); + u32 regA =3D rFPGA0_XA_HSSIParameter2 | MaskforPhySet; + + tmplong2 =3D PHY_QueryBBReg(Adapter, regA, bMaskDWord); tmplong2 =3D (tmplong2 & (~bLSSIReadAddress)) | (NewOffset<<23) | bLSSIR= eadEdge; /* T65 RF */ - PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord= , tmplong2&(~bLSSIReadEdge)); + PHY_SetBBReg(Adapter, regA, bMaskDWord, tmplong2 & (~bLSSIReadEdge)); } else { - tmplong2 =3D PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter2|MaskforPhy= Set, bMaskDWord); + u32 regB =3D rFPGA0_XB_HSSIParameter2 | MaskforPhySet; + + tmplong2 =3D PHY_QueryBBReg(Adapter, regB, bMaskDWord); tmplong2 =3D (tmplong2 & (~bLSSIReadAddress)) | (NewOffset<<23) | bLSSIR= eadEdge; /* T65 RF */ - PHY_SetBBReg(Adapter, rFPGA0_XB_HSSIParameter2|MaskforPhySet, bMaskDWord= , tmplong2&(~bLSSIReadEdge)); + PHY_SetBBReg(Adapter, regB, bMaskDWord, tmplong2 & (~bLSSIReadEdge)); } =20 - tmplong2 =3D PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhyS= et, bMaskDWord); - PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord,= tmplong2 & (~bLSSIReadEdge)); - PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord,= tmplong2 | bLSSIReadEdge); + { + u32 reg =3D rFPGA0_XA_HSSIParameter2 | MaskforPhySet; + + tmplong2 =3D PHY_QueryBBReg(Adapter, reg, bMaskDWord); + PHY_SetBBReg(Adapter, reg, bMaskDWord, tmplong2 & (~bLSSIReadEdge)); + PHY_SetBBReg(Adapter, reg, bMaskDWord, tmplong2 | bLSSIReadEdge); + } =20 udelay(10); =20 @@ -307,22 +315,29 @@ static void phy_InitBBRFRegisterDefinition(struct ada= pter *Adapter) struct hal_com_data *pHalData =3D GET_HAL_DATA(Adapter); =20 /* RF Interface Sowrtware Control */ - pHalData->PHYRegDef[RF_PATH_A].rfintfs =3D rFPGA0_XAB_RFInterfaceSW; /* = 16 LSBs if read 32-bit from 0x870 */ - pHalData->PHYRegDef[RF_PATH_B].rfintfs =3D rFPGA0_XAB_RFInterfaceSW; /* = 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */ + /* 16 LSBs if read 32-bit from 0x870 */ + pHalData->PHYRegDef[RF_PATH_A].rfintfs =3D rFPGA0_XAB_RFInterfaceSW; + /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */ + pHalData->PHYRegDef[RF_PATH_B].rfintfs =3D rFPGA0_XAB_RFInterfaceSW; =20 /* RF Interface Output (and Enable) */ - pHalData->PHYRegDef[RF_PATH_A].rfintfo =3D rFPGA0_XA_RFInterfaceOE; /* 1= 6 LSBs if read 32-bit from 0x860 */ - pHalData->PHYRegDef[RF_PATH_B].rfintfo =3D rFPGA0_XB_RFInterfaceOE; /* 1= 6 LSBs if read 32-bit from 0x864 */ + /* 16 LSBs if read 32-bit from 0x860 */ + pHalData->PHYRegDef[RF_PATH_A].rfintfo =3D rFPGA0_XA_RFInterfaceOE; + /* 16 LSBs if read 32-bit from 0x864 */ + pHalData->PHYRegDef[RF_PATH_B].rfintfo =3D rFPGA0_XB_RFInterfaceOE; =20 /* RF Interface (Output and) Enable */ - pHalData->PHYRegDef[RF_PATH_A].rfintfe =3D rFPGA0_XA_RFInterfaceOE; /* 1= 6 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */ - pHalData->PHYRegDef[RF_PATH_B].rfintfe =3D rFPGA0_XB_RFInterfaceOE; /* 1= 6 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */ + /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */ + pHalData->PHYRegDef[RF_PATH_A].rfintfe =3D rFPGA0_XA_RFInterfaceOE; + /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */ + pHalData->PHYRegDef[RF_PATH_B].rfintfe =3D rFPGA0_XB_RFInterfaceOE; =20 pHalData->PHYRegDef[RF_PATH_A].rf3wireOffset =3D rFPGA0_XA_LSSIParameter;= /* LSSI Parameter */ pHalData->PHYRegDef[RF_PATH_B].rf3wireOffset =3D rFPGA0_XB_LSSIParameter; =20 - pHalData->PHYRegDef[RF_PATH_A].rfHSSIPara2 =3D rFPGA0_XA_HSSIParameter2; = /* wire control parameter2 */ - pHalData->PHYRegDef[RF_PATH_B].rfHSSIPara2 =3D rFPGA0_XB_HSSIParameter2; = /* wire control parameter2 */ + /* wire control parameter2 */ + pHalData->PHYRegDef[RF_PATH_A].rfHSSIPara2 =3D rFPGA0_XA_HSSIParameter2; + pHalData->PHYRegDef[RF_PATH_B].rfHSSIPara2 =3D rFPGA0_XB_HSSIParameter2; =20 /* Transceiver Readback LSSI/HSPI mode */ pHalData->PHYRegDef[RF_PATH_A].rfLSSIReadBack =3D rFPGA0_XA_LSSIReadBack; @@ -643,8 +658,12 @@ static void phy_PostSetBwMode8723B(struct adapter *Ada= pter) PHY_SetBBReg(Adapter, rCCK0_System, bCCKSideBand, (pHalData->nCur40MhzPr= imeSC>>1)); =20 PHY_SetBBReg(Adapter, rOFDM1_LSTF, 0xC00, pHalData->nCur40MhzPrimeSC); + { + u32 val; =20 - PHY_SetBBReg(Adapter, 0x818, (BIT26|BIT27), (pHalData->nCur40MhzPrimeSC = =3D=3D HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1); + val =3D (pHalData->nCur40MhzPrimeSC =3D=3D HAL_PRIME_CHNL_OFFSET_LOWER)= ? 2 : 1; + PHY_SetBBReg(Adapter, 0x818, (BIT26 | BIT27), val); + } break; default: break; @@ -769,5 +788,6 @@ void PHY_SetSwChnlBWMode8723B( u8 Offset80 ) { - PHY_HandleSwChnlAndSetBW8723B(Adapter, true, true, channel, Bandwidth, Of= fset40, Offset80, channel); + PHY_HandleSwChnlAndSetBW8723B(Adapter, true, true, channel, + Bandwidth, Offset40, Offset80, channel); } --=20 2.52.0