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charset="utf-8" Add external memory (EMEM) read/write operations to the GPU's FSP falcon engine. These operations use Falcon PIO (Programmed I/O) to communicate with the FSP through indirect memory access. Cc: Gary Guo Cc: Timur Tabi Signed-off-by: John Hubbard --- drivers/gpu/nova-core/falcon/fsp.rs | 62 ++++++++++++++++++++++++++++- drivers/gpu/nova-core/regs.rs | 10 +++++ 2 files changed, 71 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nova-core/falcon/fsp.rs b/drivers/gpu/nova-core/fa= lcon/fsp.rs index cc3fc3cf2f6a..5152c2f1ed26 100644 --- a/drivers/gpu/nova-core/falcon/fsp.rs +++ b/drivers/gpu/nova-core/falcon/fsp.rs @@ -5,15 +5,27 @@ //! The FSP falcon handles secure boot and Chain of Trust operations //! on Hopper and Blackwell architectures, replacing SEC2's role. =20 +use kernel::prelude::*; + use crate::{ + driver::Bar0, falcon::{ + Falcon, FalconEngine, PFalcon2Base, PFalconBase, // }, - regs::macros::RegisterBase, + regs::{ + self, + macros::RegisterBase, // + }, }; =20 +/// EMEM control register bit 24: write mode. +const EMEM_CTL_WRITE: u32 =3D 1 << 24; +/// EMEM control register bit 25: read mode. +const EMEM_CTL_READ: u32 =3D 1 << 25; + /// Type specifying the `Fsp` falcon engine. Cannot be instantiated. pub(crate) struct Fsp(()); =20 @@ -29,3 +41,51 @@ impl RegisterBase for Fsp { impl FalconEngine for Fsp { const ID: Self =3D Fsp(()); } + +impl Falcon { + /// Writes `data` to FSP external memory at byte `offset` using Falcon= PIO. + /// + /// Returns `EINVAL` if offset or data length is not 4-byte aligned. + #[expect(unused)] + pub(crate) fn write_emem(&self, bar: &Bar0, offset: u32, data: &[u8]) = -> Result { + // TODO: replace with `is_multiple_of` once the MSRV is >=3D 1.82. + if offset % 4 !=3D 0 || data.len() % 4 !=3D 0 { + return Err(EINVAL); + } + + regs::NV_PFALCON_FALCON_EMEM_CTL::default() + .set_value(EMEM_CTL_WRITE | offset) + .write(bar, &Fsp::ID); + + for chunk in data.chunks_exact(4) { + let word =3D u32::from_le_bytes([chunk[0], chunk[1], chunk[2],= chunk[3]]); + regs::NV_PFALCON_FALCON_EMEM_DATA::default() + .set_data(word) + .write(bar, &Fsp::ID); + } + + Ok(()) + } + + /// Reads FSP external memory at byte `offset` into `data` using Falco= n PIO. + /// + /// Returns `EINVAL` if offset or data length is not 4-byte aligned. + #[expect(unused)] + pub(crate) fn read_emem(&self, bar: &Bar0, offset: u32, data: &mut [u8= ]) -> Result { + // TODO: replace with `is_multiple_of` once the MSRV is >=3D 1.82. + if offset % 4 !=3D 0 || data.len() % 4 !=3D 0 { + return Err(EINVAL); + } + + regs::NV_PFALCON_FALCON_EMEM_CTL::default() + .set_value(EMEM_CTL_READ | offset) + .write(bar, &Fsp::ID); + + for chunk in data.chunks_exact_mut(4) { + let word =3D regs::NV_PFALCON_FALCON_EMEM_DATA::read(bar, &Fsp= ::ID).data(); + chunk.copy_from_slice(&word.to_le_bytes()); + } + + Ok(()) + } +} diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index ea0d32f5396c..30a5a49edeab 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -431,6 +431,16 @@ pub(crate) fn reset_engine(bar: &Bar0= ) { 8:8 br_fetch as bool; }); =20 +// GP102 EMEM PIO registers (used by FSP for Hopper/Blackwell) +// These registers provide falcon external memory communication interface +register!(NV_PFALCON_FALCON_EMEM_CTL @ PFalconBase[0x00000ac0] { + 31:0 value as u32; // EMEM control register +}); + +register!(NV_PFALCON_FALCON_EMEM_DATA @ PFalconBase[0x00000ac4] { + 31:0 data as u32; // EMEM data register +}); + // The modules below provide registers that are not identical on all suppo= rted chips. They should // only be used in HAL modules. =20 --=20 2.53.0