From nobody Sun Feb 8 00:11:39 2026 Received: from out28-98.mail.aliyun.com (out28-98.mail.aliyun.com [115.124.28.98]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 19FB661FFE; Fri, 6 Feb 2026 02:23:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.28.98 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770344616; cv=none; b=iEUfYL4Se/5Fsc87v4UcOT2EON+OJlJZAqDYui0waruU9tky8vXlgSP3RrdVfxMfnaBK/5GxY/uYErKEDVu3fZ8Z0d/pkdC9cCEMzQKznBeZ31NXelVtcL3Xh60xPjN4JdUVxl/tfwPM6QY71gYA2y8PJomk6K++lMkQkUMDf2U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770344616; c=relaxed/simple; bh=29152ZbryzR1SShOgoJmPtUPIzEgN4v4kci6h8dgf3w=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=YUHBu9wMgtABLaHbxerrv4QF8wKq8+ta/TYwzQQ6xZWxQ+jUJb32/7rq9eEbnKtw1S6/pAP66ZWhia5JJea+Uocv+fmiNsNQlehsUjSX0FUcrDt1i3AIsVCrYTzTgbutKyqbZEknRV8ng0RCEZmRqRvLxQBVcGWg2tJhtmfIVKM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=nebula-matrix.com; spf=pass smtp.mailfrom=nebula-matrix.com; arc=none smtp.client-ip=115.124.28.98 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=nebula-matrix.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nebula-matrix.com Received: from localhost.localdomain(mailfrom:illusion.wang@nebula-matrix.com fp:SMTPD_---.gQHg4cX_1770344290 cluster:ay29) by smtp.aliyun-inc.com; Fri, 06 Feb 2026 10:18:11 +0800 From: "illusion.wang" To: dimon.zhao@nebula-matrix.com, illusion.wang@nebula-matrix.com, alvin.wang@nebula-matrix.com, sam.chen@nebula-matrix.com, netdev@vger.kernel.org Cc: andrew+netdev@lunn.ch, corbet@lwn.net, kuba@kernel.org, linux-doc@vger.kernel.org, lorenzo@kernel.org, pabeni@redhat.com, horms@kernel.org, vadim.fedorenko@linux.dev, lukas.bulwahn@redhat.com, edumazet@google.com, linux-kernel@vger.kernel.org (open list) Subject: [PATCH v4 net-next 01/11] net/nebula-matrix: add minimum nbl build framework Date: Fri, 6 Feb 2026 10:15:53 +0800 Message-ID: <20260206021608.85381-2-illusion.wang@nebula-matrix.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260206021608.85381-1-illusion.wang@nebula-matrix.com> References: <20260206021608.85381-1-illusion.wang@nebula-matrix.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" 1.Add nbl min build infrastructure for nbl driver. 2.Implemented the framework of pci device initialization. Signed-off-by: illusion.wang --- .../device_drivers/ethernet/index.rst | 1 + .../ethernet/nebula-matrix/m18100.rst | 47 ++++++++ MAINTAINERS | 10 ++ drivers/net/ethernet/Kconfig | 1 + drivers/net/ethernet/Makefile | 1 + drivers/net/ethernet/nebula-matrix/Kconfig | 36 ++++++ drivers/net/ethernet/nebula-matrix/Makefile | 6 + .../net/ethernet/nebula-matrix/nbl/Makefile | 11 ++ .../net/ethernet/nebula-matrix/nbl/nbl_core.h | 27 +++++ .../nbl/nbl_include/nbl_include.h | 23 ++++ .../net/ethernet/nebula-matrix/nbl/nbl_main.c | 109 ++++++++++++++++++ 11 files changed, 272 insertions(+) create mode 100644 Documentation/networking/device_drivers/ethernet/nebula= -matrix/m18100.rst create mode 100644 drivers/net/ethernet/nebula-matrix/Kconfig create mode 100644 drivers/net/ethernet/nebula-matrix/Makefile create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/Makefile create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_core.h create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_= include.h create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_main.c diff --git a/Documentation/networking/device_drivers/ethernet/index.rst b/D= ocumentation/networking/device_drivers/ethernet/index.rst index 5e8fc3d6d741..8b049cb0f3bd 100644 --- a/Documentation/networking/device_drivers/ethernet/index.rst +++ b/Documentation/networking/device_drivers/ethernet/index.rst @@ -48,6 +48,7 @@ Contents: meta/fbnic microsoft/netvsc mucse/rnpgbe + nebula-matrix/nbl netronome/nfp pensando/ionic pensando/ionic_rdma diff --git a/Documentation/networking/device_drivers/ethernet/nebula-matrix= /m18100.rst b/Documentation/networking/device_drivers/ethernet/nebula-matri= x/m18100.rst new file mode 100644 index 000000000000..c763042ce3ee --- /dev/null +++ b/Documentation/networking/device_drivers/ethernet/nebula-matrix/m18100= .rst @@ -0,0 +1,47 @@ +.. SPDX-License-Identifier: GPL-2.0 + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Linux Base Driver for Nebula-matrix M18100-NIC family +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Overview: +=3D=3D=3D=3D=3D=3D=3D=3D=3D +M18100-NIC is a series of network interface card for the Data Center Area. + +The driver supports link-speed 100GbE/25GE/10GE. + +M18100-NIC devices support MSI-X interrupt vector for each Tx/Rx queue and +interrupt moderation. + +M18100-NIC devices support also various offload features such as checksum = offload, +Receive-Side Scaling(RSS). + +Supported PCI vendor ID/device IDs: +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +1f0f:3403 - M18110 Family PF +1f0f:3404 - M18110 Lx Family PF +1f0f:3405 - M18110 Family BASE-T PF +1f0f:3406 - M18110 Lx Family BASE-T PF +1f0f:3407 - M18110 Family OCP PF +1f0f:3408 - M18110 Lx Family OCP PF +1f0f:3409 - M18110 Family BASE-T OCP PF +1f0f:340a - M18110 Lx Family BASE-T OCP PF +1f0f:340b - M18100 Family PF +1f0f:340c - M18100 Lx Family PF +1f0f:340d - M18100 Family BASE-T PF +1f0f:340e - M18100 Lx Family BASE-T PF +1f0f:340f - M18100 Family OCP PF +1f0f:3410 - M18100 Lx Family OCP PF +1f0f:3411 - M18100 Family BASE-T OCP PF +1f0f:3412 - M18100 Lx Family BASE-T OCP PF + +Support +=3D=3D=3D=3D=3D=3D=3D + +For more information about M18100-NIC, please visit the following URL: +https://www.nebula-matrix.com/ + +If an issue is identified with the released source code on the supported k= ernel +with a supported adapter, email the specific information related to the is= sue to +open@nebula-matrix.com. diff --git a/MAINTAINERS b/MAINTAINERS index 98b07da905b0..2c85f70023a9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -18015,6 +18015,16 @@ F: Documentation/devicetree/bindings/hwmon/nuvoton= ,nct7363.yaml F: Documentation/hwmon/nct7363.rst F: drivers/hwmon/nct7363.c =20 +NEBULA-MATRIX ETHERNET DRIVER (nebula-matrix) +M: llusion.Wang +M: Dimon.Zhao +M: Alvin.Wang +M: Sam Chen +L: netdev@vger.kernel.org +S: Maintained +F: Documentation/networking/device_drivers/ethernet/nebula-matrix/* +F: drivers/net/ethernet/nebula-matrix/ + NETCONSOLE M: Breno Leitao S: Maintained diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig index aa7103e7f47f..3aa005adb90e 100644 --- a/drivers/net/ethernet/Kconfig +++ b/drivers/net/ethernet/Kconfig @@ -131,6 +131,7 @@ config FEALNX =20 source "drivers/net/ethernet/ni/Kconfig" source "drivers/net/ethernet/natsemi/Kconfig" +source "drivers/net/ethernet/nebula-matrix/Kconfig" source "drivers/net/ethernet/netronome/Kconfig" source "drivers/net/ethernet/8390/Kconfig" source "drivers/net/ethernet/nvidia/Kconfig" diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile index 6615a67a63d5..024a8e91abed 100644 --- a/drivers/net/ethernet/Makefile +++ b/drivers/net/ethernet/Makefile @@ -68,6 +68,7 @@ obj-$(CONFIG_NET_VENDOR_MUCSE) +=3D mucse/ obj-$(CONFIG_NET_VENDOR_MYRI) +=3D myricom/ obj-$(CONFIG_FEALNX) +=3D fealnx.o obj-$(CONFIG_NET_VENDOR_NATSEMI) +=3D natsemi/ +obj-$(CONFIG_NET_VENDOR_NEBULA_MATRIX) +=3D nebula-matrix/ obj-$(CONFIG_NET_VENDOR_NETRONOME) +=3D netronome/ obj-$(CONFIG_NET_VENDOR_NI) +=3D ni/ obj-$(CONFIG_NET_VENDOR_NVIDIA) +=3D nvidia/ diff --git a/drivers/net/ethernet/nebula-matrix/Kconfig b/drivers/net/ether= net/nebula-matrix/Kconfig new file mode 100644 index 000000000000..9c65803f5447 --- /dev/null +++ b/drivers/net/ethernet/nebula-matrix/Kconfig @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Nebula-matrix network device configuration +# + +config NET_VENDOR_NEBULA_MATRIX + bool "Nebula-matrix devices" + default y + help + If you have a network (Ethernet) card belonging to this class, say Y. + Note that the answer to this question doesn't directly affect the + kernel: saying N will just cause the configurator to skip all + the questions about Nebula-matrix cards. If you say Y, you will be asked + for your specific card in the following questions. + +if NET_VENDOR_NEBULA_MATRIX + +config NBL_CORE + tristate "Nebula-matrix Ethernet Controller m18100 Family support" + depends on 64BIT && PCI + default m + select PAGE_POOL + help + This driver supports Nebula-matrix Ethernet Controller m18100 Family of + devices. For more information about this product, go to the product + description with smart NIC: + + + + More specific information on configuring the driver is in + . + + To compile this driver as a module, choose M here. The module + will be called nbl_core. + +endif # NET_VENDOR_NEBULA_MATRIX diff --git a/drivers/net/ethernet/nebula-matrix/Makefile b/drivers/net/ethe= rnet/nebula-matrix/Makefile new file mode 100644 index 000000000000..dc6bf7dcd6bf --- /dev/null +++ b/drivers/net/ethernet/nebula-matrix/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Makefile for the Nebula-matrix network device drivers. +# + +obj-$(CONFIG_NBL_CORE) +=3D nbl/ diff --git a/drivers/net/ethernet/nebula-matrix/nbl/Makefile b/drivers/net/= ethernet/nebula-matrix/nbl/Makefile new file mode 100644 index 000000000000..df16a3436a5c --- /dev/null +++ b/drivers/net/ethernet/nebula-matrix/nbl/Makefile @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0 +# Copyright (c) 2025 Nebula Matrix Limited. +# Author: + +obj-$(CONFIG_NBL_CORE) :=3D nbl_core.o + +nbl_core-objs +=3D nbl_main.o + +# Provide include files +ccflags-y +=3D -I$(srctree)/drivers/net/ethernet/nebula-matrix/nbl/nbl_inc= lude/ +ccflags-y +=3D -I$(srctree)/drivers/net/ethernet/nebula-matrix/nbl/ diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_core.h b/drivers/ne= t/ethernet/nebula-matrix/nbl/nbl_core.h new file mode 100644 index 000000000000..51aa4d87146f --- /dev/null +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_core.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0*/ +/* + * Copyright (c) 2025 Nebula Matrix Limited. + * Author: + */ + +#ifndef _NBL_CORE_H_ +#define _NBL_CORE_H_ + +#include +#include "nbl_include.h" +#define NBL_CAP_TEST_BIT(val, loc) (((val) >> (loc)) & 0x1) + +#define NBL_CAP_IS_CTRL(val) NBL_CAP_TEST_BIT(val, NBL_CAP_HAS_CTRL_BIT) +#define NBL_CAP_IS_NET(val) NBL_CAP_TEST_BIT(val, NBL_CAP_HAS_NET_BIT) +#define NBL_CAP_IS_NIC(val) NBL_CAP_TEST_BIT(val, NBL_CAP_IS_NIC_BIT) +#define NBL_CAP_IS_OCP(val) NBL_CAP_TEST_BIT(val, NBL_CAP_IS_OCP_BIT) +#define NBL_CAP_IS_LEONIS(val) NBL_CAP_TEST_BIT(val, NBL_CAP_IS_LEONIS_BIT) + +enum { + NBL_CAP_HAS_CTRL_BIT =3D 0, + NBL_CAP_HAS_NET_BIT, + NBL_CAP_IS_NIC_BIT, + NBL_CAP_IS_LEONIS_BIT, + NBL_CAP_IS_OCP_BIT, +}; +#endif diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_include= .h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_include.h new file mode 100644 index 000000000000..f12bf019dfee --- /dev/null +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_include.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0*/ +/* + * Copyright (c) 2025 Nebula Matrix Limited. + * Author: + */ + +#ifndef _NBL_INCLUDE_H_ +#define _NBL_INCLUDE_H_ + +#include + +/* ------ Basic definitions ------- */ +#define NBL_DRIVER_NAME "nbl_core" + +struct nbl_func_caps { + u32 has_ctrl:1; + u32 has_net:1; + u32 is_nic:1; + u32 is_ocp:1; + u32 rsv:28; +}; + +#endif diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_main.c b/drivers/ne= t/ethernet/nebula-matrix/nbl/nbl_main.c new file mode 100644 index 000000000000..63bba8211654 --- /dev/null +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_main.c @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 Nebula Matrix Limited. + * Author: + */ + +#include +#include "nbl_core.h" + +static int nbl_probe(struct pci_dev *pdev, + const struct pci_device_id __always_unused *id) +{ + return 0; +} + +static void nbl_remove(struct pci_dev *pdev) +{ +} + +#define NBL_VENDOR_ID (0x1F0F) + +/* + * Leonis DeviceID + * 0x3403-0x340d for snic v3r1 product + */ +#define NBL_DEVICE_ID_M18110 (0x3403) +#define NBL_DEVICE_ID_M18110_LX (0x3404) +#define NBL_DEVICE_ID_M18110_BASE_T (0x3405) +#define NBL_DEVICE_ID_M18110_LX_BASE_T (0x3406) +#define NBL_DEVICE_ID_M18110_OCP (0x3407) +#define NBL_DEVICE_ID_M18110_LX_OCP (0x3408) +#define NBL_DEVICE_ID_M18110_BASE_T_OCP (0x3409) +#define NBL_DEVICE_ID_M18110_LX_BASE_T_OCP (0x340a) +#define NBL_DEVICE_ID_M18000 (0x340b) +#define NBL_DEVICE_ID_M18000_LX (0x340c) +#define NBL_DEVICE_ID_M18000_BASE_T (0x340d) +#define NBL_DEVICE_ID_M18000_LX_BASE_T (0x340e) +#define NBL_DEVICE_ID_M18000_OCP (0x340f) +#define NBL_DEVICE_ID_M18000_LX_OCP (0x3410) +#define NBL_DEVICE_ID_M18000_BASE_T_OCP (0x3411) +#define NBL_DEVICE_ID_M18000_LX_BASE_T_OCP (0x3412) + +static const struct pci_device_id nbl_id_table[] =3D { + { PCI_DEVICE(NBL_VENDOR_ID, NBL_DEVICE_ID_M18110), + .driver_data =3D BIT(NBL_CAP_HAS_NET_BIT) | BIT(NBL_CAP_IS_NIC_BIT) | + BIT(NBL_CAP_IS_LEONIS_BIT) }, + { PCI_DEVICE(NBL_VENDOR_ID, NBL_DEVICE_ID_M18110_LX), + .driver_data =3D BIT(NBL_CAP_HAS_NET_BIT) | BIT(NBL_CAP_IS_NIC_BIT) | + BIT(NBL_CAP_IS_LEONIS_BIT) }, + { PCI_DEVICE(NBL_VENDOR_ID, NBL_DEVICE_ID_M18110_BASE_T), + .driver_data =3D BIT(NBL_CAP_HAS_NET_BIT) | BIT(NBL_CAP_IS_NIC_BIT) | + BIT(NBL_CAP_IS_LEONIS_BIT) }, + { PCI_DEVICE(NBL_VENDOR_ID, NBL_DEVICE_ID_M18110_LX_BASE_T), + .driver_data =3D BIT(NBL_CAP_HAS_NET_BIT) | BIT(NBL_CAP_IS_NIC_BIT) | + BIT(NBL_CAP_IS_LEONIS_BIT) }, + { PCI_DEVICE(NBL_VENDOR_ID, NBL_DEVICE_ID_M18110_OCP), + .driver_data =3D BIT(NBL_CAP_HAS_NET_BIT) | BIT(NBL_CAP_IS_NIC_BIT) | + BIT(NBL_CAP_IS_LEONIS_BIT) | BIT(NBL_CAP_IS_OCP_BIT) }, + { PCI_DEVICE(NBL_VENDOR_ID, NBL_DEVICE_ID_M18110_LX_OCP), + .driver_data =3D BIT(NBL_CAP_HAS_NET_BIT) | BIT(NBL_CAP_IS_NIC_BIT) | + BIT(NBL_CAP_IS_LEONIS_BIT) | BIT(NBL_CAP_IS_OCP_BIT) }, + { PCI_DEVICE(NBL_VENDOR_ID, NBL_DEVICE_ID_M18110_BASE_T_OCP), + .driver_data =3D BIT(NBL_CAP_HAS_NET_BIT) | BIT(NBL_CAP_IS_NIC_BIT) | + BIT(NBL_CAP_IS_LEONIS_BIT) | BIT(NBL_CAP_IS_OCP_BIT) }, + { PCI_DEVICE(NBL_VENDOR_ID, NBL_DEVICE_ID_M18110_LX_BASE_T_OCP), + .driver_data =3D BIT(NBL_CAP_HAS_NET_BIT) | BIT(NBL_CAP_IS_NIC_BIT) | + BIT(NBL_CAP_IS_LEONIS_BIT) | BIT(NBL_CAP_IS_OCP_BIT) }, + { PCI_DEVICE(NBL_VENDOR_ID, NBL_DEVICE_ID_M18000), + .driver_data =3D BIT(NBL_CAP_HAS_NET_BIT) | BIT(NBL_CAP_IS_NIC_BIT) | + BIT(NBL_CAP_IS_LEONIS_BIT) }, + { PCI_DEVICE(NBL_VENDOR_ID, NBL_DEVICE_ID_M18000_LX), + .driver_data =3D BIT(NBL_CAP_HAS_NET_BIT) | BIT(NBL_CAP_IS_NIC_BIT) | + BIT(NBL_CAP_IS_LEONIS_BIT) }, + { PCI_DEVICE(NBL_VENDOR_ID, NBL_DEVICE_ID_M18000_BASE_T), + .driver_data =3D BIT(NBL_CAP_HAS_NET_BIT) | BIT(NBL_CAP_IS_NIC_BIT) | + BIT(NBL_CAP_IS_LEONIS_BIT) }, + { PCI_DEVICE(NBL_VENDOR_ID, NBL_DEVICE_ID_M18000_LX_BASE_T), + .driver_data =3D BIT(NBL_CAP_HAS_NET_BIT) | BIT(NBL_CAP_IS_NIC_BIT) | + BIT(NBL_CAP_IS_LEONIS_BIT) }, + { PCI_DEVICE(NBL_VENDOR_ID, NBL_DEVICE_ID_M18000_OCP), + .driver_data =3D BIT(NBL_CAP_HAS_NET_BIT) | BIT(NBL_CAP_IS_NIC_BIT) | + BIT(NBL_CAP_IS_LEONIS_BIT) | BIT(NBL_CAP_IS_OCP_BIT) }, + { PCI_DEVICE(NBL_VENDOR_ID, NBL_DEVICE_ID_M18000_LX_OCP), + .driver_data =3D BIT(NBL_CAP_HAS_NET_BIT) | BIT(NBL_CAP_IS_NIC_BIT) | + BIT(NBL_CAP_IS_LEONIS_BIT) | BIT(NBL_CAP_IS_OCP_BIT) }, + { PCI_DEVICE(NBL_VENDOR_ID, NBL_DEVICE_ID_M18000_BASE_T_OCP), + .driver_data =3D BIT(NBL_CAP_HAS_NET_BIT) | BIT(NBL_CAP_IS_NIC_BIT) | + BIT(NBL_CAP_IS_LEONIS_BIT) | BIT(NBL_CAP_IS_OCP_BIT) }, + { PCI_DEVICE(NBL_VENDOR_ID, NBL_DEVICE_ID_M18000_LX_BASE_T_OCP), + .driver_data =3D BIT(NBL_CAP_HAS_NET_BIT) | BIT(NBL_CAP_IS_NIC_BIT) | + BIT(NBL_CAP_IS_LEONIS_BIT) | BIT(NBL_CAP_IS_OCP_BIT) }, + /* required as sentinel */ + { + 0, + } +}; +MODULE_DEVICE_TABLE(pci, nbl_id_table); + +static struct pci_driver nbl_driver =3D { + .name =3D NBL_DRIVER_NAME, + .id_table =3D nbl_id_table, + .probe =3D nbl_probe, + .remove =3D nbl_remove, +}; + +module_pci_driver(nbl_driver); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Nebula Matrix Network Driver"); --=20 2.47.3 From nobody Sun Feb 8 00:11:39 2026 Received: from out28-194.mail.aliyun.com (out28-194.mail.aliyun.com [115.124.28.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 46313273F9; Fri, 6 Feb 2026 02:18:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.28.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770344304; cv=none; b=Ltes+mSJsk1E8q1AkUR2BCFU3dz3Qa2X4pSUJh0p6kWs9JL+r3EnzFhenaHxFhnFkc8his1Er0T2ndoOSciqobG3B1Y0eTTvr9M8+pg76p76BRJdiL0LeXzobA57hlPXLbQJqe54skkcj9gzvZsIlt2wzgFq49nRxdZ+RZ2hqbc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770344304; c=relaxed/simple; bh=jhPC50AYBOQnjsEvHOmuahsX1l6D2diE4+xV5CoZjfg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=AvXEEiDDQAscs6OPoH+PBgf3pSAXvI20ntBuZiVm1Y1KMi8RcSn+0Pa2bVMcKDlnyXPiyL7cGYXZ6Mi9649Az138pLr6mUilmgOPKA6A2kIDDiDzRkcYY/i+Q0VJ3UdcrFneEZsFUPUsppM8K7BK1+e+hr3v8+IsIEg2hk+AJIE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=nebula-matrix.com; spf=pass smtp.mailfrom=nebula-matrix.com; arc=none smtp.client-ip=115.124.28.194 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=nebula-matrix.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nebula-matrix.com Received: from localhost.localdomain(mailfrom:illusion.wang@nebula-matrix.com fp:SMTPD_---.gQHg4eN_1770344291 cluster:ay29) by smtp.aliyun-inc.com; Fri, 06 Feb 2026 10:18:12 +0800 From: "illusion.wang" To: dimon.zhao@nebula-matrix.com, illusion.wang@nebula-matrix.com, alvin.wang@nebula-matrix.com, sam.chen@nebula-matrix.com, netdev@vger.kernel.org Cc: andrew+netdev@lunn.ch, corbet@lwn.net, kuba@kernel.org, linux-doc@vger.kernel.org, lorenzo@kernel.org, pabeni@redhat.com, horms@kernel.org, vadim.fedorenko@linux.dev, lukas.bulwahn@redhat.com, edumazet@google.com, linux-kernel@vger.kernel.org (open list) Subject: [PATCH v4 net-next 02/11] net/nebula-matrix: add our driver architecture Date: Fri, 6 Feb 2026 10:15:54 +0800 Message-ID: <20260206021608.85381-3-illusion.wang@nebula-matrix.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260206021608.85381-1-illusion.wang@nebula-matrix.com> References: <20260206021608.85381-1-illusion.wang@nebula-matrix.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable our driver architecture: Hardware (HW), Channel, Resource, Dispatch, and Device Layer Struct Initialization/Deinitialization, and Operation Set Registration/ Unregistration Our driver architecture is relatively complex because the code is highly reusable and designed to support multiple features. Additionally, the codebase supports multiple chip variants, each with distinct hardware-software interactions.=C2=A0 To ensure compatibility, our architecture is divided into the following layers: 1. Dev Layer (Device Layer) The top-level business logic layer where all operations are device-centric. Every operation is performed relative to the device context. The intergration of base functions encompasses: management(ctrl only for leonis pf0), network(net_dev,this time not contained),common. 2. Dispatch Layer The distribution from services to specific data operations is mainly divided into two types: direct pass-through and handling by the management PF. It shields the upper layer from the differences in specific underlying locations. It describes the processing locations and paths of the services. 3. Resource Layer Handles tasks dispatched from Dispatch Layer. These tasks fall into two categories: 3.1 Hardware control =C2=A0 The Resource Layer further invokes the HW Layer when hardware access is needed, as only the HW Layer has OS-level privileges. 3.2 Software resource management Operations like packet statistics collection that don't require hardware access. 4. HW Layer (Hardware Layer) Serves the Resource Layer by interacting with different hardware chipsets.Writes to hardware registers to drive the hardware based on Resource Layer directives. 5. Channel Layer Handle communication between PF0(has ctrl func) and other PF,and provide basic interaction channels. 6. Common Layer Provides fundamental services Signed-off-by: illusion.wang --- .../net/ethernet/nebula-matrix/nbl/Makefile | 8 +- .../nbl/nbl_channel/nbl_channel.c | 82 ++++++++ .../nbl/nbl_channel/nbl_channel.h | 37 ++++ .../net/ethernet/nebula-matrix/nbl/nbl_core.h | 59 +++++- .../nebula-matrix/nbl/nbl_core/nbl_dev.c | 55 ++++++ .../nebula-matrix/nbl/nbl_core/nbl_dev.h | 18 ++ .../nebula-matrix/nbl/nbl_core/nbl_dispatch.c | 75 ++++++++ .../nebula-matrix/nbl/nbl_core/nbl_dispatch.h | 22 +++ .../nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.c | 143 ++++++++++++++ .../nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.h | 13 ++ .../nbl_hw_leonis/nbl_resource_leonis.c | 90 +++++++++ .../nbl_hw_leonis/nbl_resource_leonis.h | 12 ++ .../nebula-matrix/nbl/nbl_hw/nbl_hw_reg.h | 131 +++++++++++++ .../nebula-matrix/nbl/nbl_hw/nbl_resource.h | 30 +++ .../nbl/nbl_include/nbl_def_channel.h | 26 +++ .../nbl/nbl_include/nbl_def_common.h | 33 ++++ .../nbl/nbl_include/nbl_def_dev.h | 12 ++ .../nbl/nbl_include/nbl_def_dispatch.h | 28 +++ .../nbl/nbl_include/nbl_def_hw.h | 20 ++ .../nbl/nbl_include/nbl_def_resource.h | 21 ++ .../nbl/nbl_include/nbl_include.h | 13 +- .../nbl/nbl_include/nbl_product_base.h | 20 ++ .../net/ethernet/nebula-matrix/nbl/nbl_main.c | 180 ++++++++++++++++++ 23 files changed, 1125 insertions(+), 3 deletions(-) create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_channel/nbl_= channel.c create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_channel/nbl_= channel.h create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dev= .c create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dev= .h create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dis= patch.c create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dis= patch.h create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_le= onis/nbl_hw_leonis.c create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_le= onis/nbl_hw_leonis.h create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_le= onis/nbl_resource_leonis.c create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_le= onis/nbl_resource_leonis.h create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_re= g.h create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_resou= rce.h create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_= def_channel.h create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_= def_common.h create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_= def_dev.h create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_= def_dispatch.h create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_= def_hw.h create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_= def_resource.h create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_= product_base.h diff --git a/drivers/net/ethernet/nebula-matrix/nbl/Makefile b/drivers/net/= ethernet/nebula-matrix/nbl/Makefile index df16a3436a5c..6d04e23c0cae 100644 --- a/drivers/net/ethernet/nebula-matrix/nbl/Makefile +++ b/drivers/net/ethernet/nebula-matrix/nbl/Makefile @@ -4,8 +4,14 @@ =20 obj-$(CONFIG_NBL_CORE) :=3D nbl_core.o =20 -nbl_core-objs +=3D nbl_main.o +nbl_core-objs +=3D nbl_channel/nbl_channel.o \ + nbl_hw/nbl_hw_leonis/nbl_hw_leonis.o \ + nbl_hw/nbl_hw_leonis/nbl_resource_leonis.o \ + nbl_core/nbl_dispatch.o \ + nbl_core/nbl_dev.o \ + nbl_main.o =20 # Provide include files ccflags-y +=3D -I$(srctree)/drivers/net/ethernet/nebula-matrix/nbl/nbl_inc= lude/ +ccflags-y +=3D -I$(srctree)/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw ccflags-y +=3D -I$(srctree)/drivers/net/ethernet/nebula-matrix/nbl/ diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_channel/nbl_channel= .c b/drivers/net/ethernet/nebula-matrix/nbl/nbl_channel/nbl_channel.c new file mode 100644 index 000000000000..9fc67700c581 --- /dev/null +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_channel/nbl_channel.c @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 Nebula Matrix Limited. + * Author: + */ +#include +#include "nbl_channel.h" + +static struct nbl_channel_ops chan_ops =3D { +}; + +static int +nbl_chan_setup_chan_mgt(struct nbl_adapter *adapter, + struct nbl_init_param *param, + struct nbl_channel_mgt_leonis **chan_mgt_leonis) +{ + struct nbl_hw_ops_tbl *hw_ops_tbl =3D adapter->intf.hw_ops_tbl; + struct nbl_common_info *common =3D &adapter->common; + struct device *dev =3D &adapter->pdev->dev; + struct nbl_chan_info *mailbox; + + *chan_mgt_leonis =3D devm_kzalloc(dev, + sizeof(struct nbl_channel_mgt_leonis), + GFP_KERNEL); + if (!*chan_mgt_leonis) + goto alloc_channel_mgt_leonis_fail; + + (&(*chan_mgt_leonis)->chan_mgt)->common =3D common; + (*chan_mgt_leonis)->chan_mgt.hw_ops_tbl =3D hw_ops_tbl; + + mailbox =3D devm_kzalloc(dev, sizeof(struct nbl_chan_info), GFP_KERNEL); + if (!mailbox) + goto alloc_mailbox_fail; + mailbox->chan_type =3D NBL_CHAN_TYPE_MAILBOX; + (&(*chan_mgt_leonis)->chan_mgt)->chan_info[NBL_CHAN_TYPE_MAILBOX] =3D + mailbox; + + return 0; +alloc_mailbox_fail: +alloc_channel_mgt_leonis_fail: + return -ENOMEM; +} + +static int nbl_chan_setup_ops(struct device *dev, + struct nbl_channel_ops_tbl **chan_ops_tbl, + struct nbl_channel_mgt_leonis *chan_mgt) +{ + *chan_ops_tbl =3D devm_kzalloc(dev, sizeof(struct nbl_channel_ops_tbl), + GFP_KERNEL); + if (!*chan_ops_tbl) + return -ENOMEM; + + (*chan_ops_tbl)->ops =3D &chan_ops; + (*chan_ops_tbl)->priv =3D &chan_mgt->chan_mgt; + return 0; +} + +int nbl_chan_init_common(struct nbl_adapter *adap, struct nbl_init_param *= param) +{ + struct nbl_channel_ops_tbl **chan_ops_tbl =3D &adap->intf.channel_ops_tbl; + struct nbl_channel_mgt_leonis **chan_mgt_leonis =3D + (struct nbl_channel_mgt_leonis **)&NBL_ADAP_TO_CHAN_MGT(adap); + struct device *dev =3D &adap->pdev->dev; + int ret; + + ret =3D nbl_chan_setup_chan_mgt(adap, param, chan_mgt_leonis); + if (ret) + goto setup_mgt_fail; + ret =3D nbl_chan_setup_ops(dev, chan_ops_tbl, *chan_mgt_leonis); + if (ret) + goto setup_ops_fail; + + return 0; + +setup_ops_fail: +setup_mgt_fail: + return ret; +} + +void nbl_chan_remove_common(struct nbl_adapter *adap) +{ +} diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_channel/nbl_channel= .h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_channel/nbl_channel.h new file mode 100644 index 000000000000..717ea402b8e9 --- /dev/null +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_channel/nbl_channel.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0*/ +/* + * Copyright (c) 2025 Nebula Matrix Limited. + * Author: + */ + +#ifndef _NBL_CHANNEL_H_ +#define _NBL_CHANNEL_H_ + +#include "nbl_core.h" + +#define NBL_CHAN_MGT_TO_MBX(chan_mgt) \ + ((chan_mgt)->chan_info[NBL_CHAN_TYPE_MAILBOX]) +#define NBL_CHAN_MGT_TO_CHAN_INFO(chan_mgt, chan_type) \ + ((chan_mgt)->chan_info[chan_type]) + +struct nbl_chan_info { + u8 chan_type; + +}; + +struct nbl_channel_mgt { + struct nbl_common_info *common; + struct nbl_hw_ops_tbl *hw_ops_tbl; + struct nbl_chan_info *chan_info[NBL_CHAN_TYPE_MAX]; + struct nbl_hash_tbl_mgt *handle_hash_tbl; +}; + +/* Mgt structure for each product. + * Every indivisual mgt must have the common mgt as its first member, and + * contains its unique data structure in the reset of it. + */ +struct nbl_channel_mgt_leonis { + struct nbl_channel_mgt chan_mgt; +}; + +#endif diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_core.h b/drivers/ne= t/ethernet/nebula-matrix/nbl/nbl_core.h index 51aa4d87146f..97ad853ce81d 100644 --- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_core.h +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_core.h @@ -8,7 +8,19 @@ #define _NBL_CORE_H_ =20 #include -#include "nbl_include.h" +#include "nbl_product_base.h" +#include "nbl_def_channel.h" +#include "nbl_def_hw.h" +#include "nbl_def_resource.h" +#include "nbl_def_dispatch.h" +#include "nbl_def_common.h" + +#define NBL_ADAP_TO_HW_MGT(adapter) ((adapter)->core.hw_mgt) +#define NBL_ADAP_TO_RES_MGT(adapter) ((adapter)->core.res_mgt) +#define NBL_ADAP_TO_DISP_MGT(adapter) ((adapter)->core.disp_mgt) +#define NBL_ADAP_TO_DEV_MGT(adapter) ((adapter)->core.dev_mgt) +#define NBL_ADAP_TO_CHAN_MGT(adapter) ((adapter)->core.chan_mgt) + #define NBL_CAP_TEST_BIT(val, loc) (((val) >> (loc)) & 0x1) =20 #define NBL_CAP_IS_CTRL(val) NBL_CAP_TEST_BIT(val, NBL_CAP_HAS_CTRL_BIT) @@ -24,4 +36,49 @@ enum { NBL_CAP_IS_LEONIS_BIT, NBL_CAP_IS_OCP_BIT, }; + +struct nbl_interface { + struct nbl_hw_ops_tbl *hw_ops_tbl; + struct nbl_resource_ops_tbl *resource_ops_tbl; + struct nbl_dispatch_ops_tbl *dispatch_ops_tbl; + struct nbl_service_ops_tbl *service_ops_tbl; + struct nbl_channel_ops_tbl *channel_ops_tbl; +}; + +struct nbl_core { + struct nbl_hw_mgt *hw_mgt; + struct nbl_resource_mgt *res_mgt; + struct nbl_dispatch_mgt *disp_mgt; + struct nbl_dev_mgt *dev_mgt; + struct nbl_channel_mgt *chan_mgt; +}; + +struct nbl_adapter { + struct pci_dev *pdev; + struct nbl_core core; + struct nbl_interface intf; + struct nbl_common_info common; + struct nbl_product_base_ops *product_base_ops; + struct nbl_init_param init_param; +}; + +struct nbl_adapter *nbl_core_init(struct pci_dev *pdev, + struct nbl_init_param *param); +void nbl_core_remove(struct nbl_adapter *adapter); +int nbl_core_start(struct nbl_adapter *adapter, struct nbl_init_param *par= am); +void nbl_core_stop(struct nbl_adapter *adapter); + +int nbl_hw_init_leonis(struct nbl_adapter *adapter, + struct nbl_init_param *param); +void nbl_hw_remove_leonis(struct nbl_adapter *adapter); +int nbl_res_init_leonis(struct nbl_adapter *adapter, + struct nbl_init_param *param); +int nbl_chan_init_common(struct nbl_adapter *adapter, + struct nbl_init_param *param); +void nbl_chan_remove_common(struct nbl_adapter *adapter); +int nbl_disp_init(struct nbl_adapter *adapter, struct nbl_init_param *para= m); +int nbl_dev_init(struct nbl_adapter *adapter, struct nbl_init_param *param= ); +void nbl_dev_remove(struct nbl_adapter *adapter); +int nbl_dev_start(struct nbl_adapter *adapter, struct nbl_init_param *para= m); +void nbl_dev_stop(struct nbl_adapter *adapter); #endif diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dev.c b/dr= ivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dev.c new file mode 100644 index 000000000000..fd7c97f3b0fe --- /dev/null +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dev.c @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 Nebula Matrix Limited. + * Author: + */ + +#include "nbl_dev.h" + +static int nbl_dev_setup_dev_mgt(struct nbl_common_info *common, + struct nbl_dev_mgt **dev_mgt) +{ + *dev_mgt =3D devm_kzalloc(common->dev, sizeof(struct nbl_dev_mgt), + GFP_KERNEL); + if (!*dev_mgt) + return -ENOMEM; + + (*dev_mgt)->common =3D common; + return 0; +} + +int nbl_dev_init(struct nbl_adapter *adapter, struct nbl_init_param *param) +{ + struct nbl_common_info *common =3D &adapter->common; + struct nbl_dispatch_ops_tbl *disp_ops_tbl =3D + adapter->intf.dispatch_ops_tbl; + struct nbl_channel_ops_tbl *chan_ops_tbl =3D + adapter->intf.channel_ops_tbl; + struct nbl_dev_mgt **dev_mgt =3D + (struct nbl_dev_mgt **)&NBL_ADAP_TO_DEV_MGT(adapter); + int ret; + + ret =3D nbl_dev_setup_dev_mgt(common, dev_mgt); + if (ret) + goto setup_mgt_fail; + + (*dev_mgt)->disp_ops_tbl =3D disp_ops_tbl; + (*dev_mgt)->chan_ops_tbl =3D chan_ops_tbl; + return 0; +setup_mgt_fail: + return ret; +} + +void nbl_dev_remove(struct nbl_adapter *adapter) +{ +} + +/* ---------- Dev start process ---------- */ +int nbl_dev_start(struct nbl_adapter *adapter, struct nbl_init_param *para= m) +{ + return 0; +} + +void nbl_dev_stop(struct nbl_adapter *adapter) +{ +} diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dev.h b/dr= ivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dev.h new file mode 100644 index 000000000000..d41ba06d00fb --- /dev/null +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dev.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0*/ +/* + * Copyright (c) 2025 Nebula Matrix Limited. + * Author: + */ + +#ifndef _NBL_DEV_H_ +#define _NBL_DEV_H_ + +#include "nbl_core.h" + +struct nbl_dev_mgt { + struct nbl_common_info *common; + struct nbl_dispatch_ops_tbl *disp_ops_tbl; + struct nbl_channel_ops_tbl *chan_ops_tbl; +}; + +#endif diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dispatch.c= b/drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dispatch.c new file mode 100644 index 000000000000..e326c59b9999 --- /dev/null +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dispatch.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 Nebula Matrix Limited. + * Author: + */ + +#include "nbl_dispatch.h" + +static int nbl_disp_setup_disp_mgt(struct nbl_common_info *common, + struct nbl_dispatch_mgt **disp_mgt) +{ + struct device *dev =3D common->dev; + + *disp_mgt =3D + devm_kzalloc(dev, sizeof(struct nbl_dispatch_mgt), GFP_KERNEL); + if (!*disp_mgt) + return -ENOMEM; + + (*disp_mgt)->common =3D common; + return 0; +} + +static int nbl_disp_setup_ops(struct device *dev, + struct nbl_dispatch_ops_tbl **disp_ops_tbl, + struct nbl_dispatch_mgt *disp_mgt) +{ + struct nbl_dispatch_ops *disp_ops; + + *disp_ops_tbl =3D devm_kzalloc(dev, sizeof(struct nbl_dispatch_ops_tbl), + GFP_KERNEL); + if (!*disp_ops_tbl) + return -ENOMEM; + + disp_ops =3D + devm_kzalloc(dev, sizeof(struct nbl_dispatch_ops), GFP_KERNEL); + if (!disp_ops) + return -ENOMEM; + + (*disp_ops_tbl)->ops =3D disp_ops; + (*disp_ops_tbl)->priv =3D disp_mgt; + + return 0; +} + +int nbl_disp_init(struct nbl_adapter *adapter, struct nbl_init_param *para= m) +{ + struct nbl_common_info *common =3D &adapter->common; + struct nbl_dispatch_ops_tbl **disp_ops_tbl =3D + &adapter->intf.dispatch_ops_tbl; + struct nbl_resource_ops_tbl *res_ops_tbl =3D + adapter->intf.resource_ops_tbl; + struct nbl_channel_ops_tbl *chan_ops_tbl =3D + adapter->intf.channel_ops_tbl; + struct device *dev =3D &adapter->pdev->dev; + struct nbl_dispatch_mgt **disp_mgt =3D + (struct nbl_dispatch_mgt **)&NBL_ADAP_TO_DISP_MGT(adapter); + int ret; + + ret =3D nbl_disp_setup_disp_mgt(common, disp_mgt); + if (ret) + goto setup_mgt_fail; + + ret =3D nbl_disp_setup_ops(dev, disp_ops_tbl, *disp_mgt); + if (ret) + goto setup_ops_fail; + + (*disp_mgt)->res_ops_tbl =3D res_ops_tbl; + (*disp_mgt)->chan_ops_tbl =3D chan_ops_tbl; + (*disp_mgt)->disp_ops_tbl =3D *disp_ops_tbl; + return 0; +setup_ops_fail: +setup_mgt_fail: + return ret; +} + diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dispatch.h= b/drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dispatch.h new file mode 100644 index 000000000000..265bad944404 --- /dev/null +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dispatch.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0*/ +/* + * Copyright (c) 2025 Nebula Matrix Limited. + * Author: + */ + +#ifndef _NBL_DISPATCH_H_ +#define _NBL_DISPATCH_H_ + +#include "nbl_core.h" + +struct nbl_dispatch_mgt { + struct nbl_common_info *common; + struct nbl_resource_ops_tbl *res_ops_tbl; + struct nbl_channel_ops_tbl *chan_ops_tbl; + struct nbl_dispatch_ops_tbl *disp_ops_tbl; + DECLARE_BITMAP(ctrl_lvl, NBL_DISP_CTRL_LVL_MAX); + /* use for the caller not in interrupt */ + struct mutex ops_mutex_lock; +}; + +#endif diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nb= l_hw_leonis.c b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis= /nbl_hw_leonis.c new file mode 100644 index 000000000000..1ff5710cd955 --- /dev/null +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_le= onis.c @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 Nebula Matrix Limited. + * Author: + */ + +#include "nbl_hw_leonis.h" + +static struct nbl_hw_ops hw_ops =3D { +}; + +/* Structure starts here, adding an op should not modify anything below */ +static int nbl_hw_setup_hw_mgt(struct nbl_common_info *common, + struct nbl_hw_mgt_leonis **hw_mgt_leonis) +{ + struct device *dev =3D common->dev; + + *hw_mgt_leonis =3D + devm_kzalloc(dev, sizeof(struct nbl_hw_mgt_leonis), GFP_KERNEL); + if (!*hw_mgt_leonis) + return -ENOMEM; + + (&(*hw_mgt_leonis)->hw_mgt)->common =3D common; + + return 0; +} + +static int nbl_hw_setup_ops(struct nbl_common_info *common, + struct nbl_hw_ops_tbl **hw_ops_tbl, + struct nbl_hw_mgt_leonis *hw_mgt_leonis) +{ + struct device *dev; + + dev =3D common->dev; + *hw_ops_tbl =3D + devm_kzalloc(dev, sizeof(struct nbl_hw_ops_tbl), GFP_KERNEL); + if (!*hw_ops_tbl) + return -ENOMEM; + + (*hw_ops_tbl)->ops =3D &hw_ops; + (*hw_ops_tbl)->priv =3D &hw_mgt_leonis->hw_mgt; + + return 0; +} + +int nbl_hw_init_leonis(struct nbl_adapter *adapter, + struct nbl_init_param *param) +{ + struct nbl_hw_ops_tbl **hw_ops_tbl =3D &adapter->intf.hw_ops_tbl; + struct nbl_common_info *common =3D &adapter->common; + struct nbl_hw_mgt_leonis **hw_mgt_leonis; + struct pci_dev *pdev =3D common->pdev; + struct nbl_hw_mgt *hw_mgt; + int bar_mask; + int ret =3D 0; + + hw_mgt_leonis =3D + (struct nbl_hw_mgt_leonis **)&NBL_ADAP_TO_HW_MGT(adapter); + + ret =3D nbl_hw_setup_hw_mgt(common, hw_mgt_leonis); + if (ret) + goto setup_mgt_fail; + + hw_mgt =3D &(*hw_mgt_leonis)->hw_mgt; + bar_mask =3D BIT(NBL_MEMORY_BAR) | BIT(NBL_MAILBOX_BAR); + ret =3D pci_request_selected_regions(pdev, bar_mask, NBL_DRIVER_NAME); + if (ret) { + dev_err(&pdev->dev, + "Request memory bar and mailbox bar failed, err =3D %d\n", + ret); + goto request_bar_region_fail; + } + + if (param->caps.has_ctrl) { + hw_mgt->hw_addr =3D + ioremap(pci_resource_start(pdev, NBL_MEMORY_BAR), + pci_resource_len(pdev, NBL_MEMORY_BAR) - + NBL_RDMA_NOTIFY_OFF); + if (!hw_mgt->hw_addr) { + dev_err(&pdev->dev, "Memory bar ioremap failed\n"); + ret =3D -EIO; + goto ioremap_err; + } + hw_mgt->hw_size =3D pci_resource_len(pdev, NBL_MEMORY_BAR) - + NBL_RDMA_NOTIFY_OFF; + } else { + hw_mgt->hw_addr =3D + ioremap(pci_resource_start(pdev, NBL_MEMORY_BAR), + NBL_RDMA_NOTIFY_OFF); + if (!hw_mgt->hw_addr) { + dev_err(&pdev->dev, "Memory bar ioremap failed\n"); + ret =3D -EIO; + goto ioremap_err; + } + hw_mgt->hw_size =3D NBL_RDMA_NOTIFY_OFF; + } + + hw_mgt->notify_offset =3D 0; + hw_mgt->mailbox_bar_hw_addr =3D pci_ioremap_bar(pdev, NBL_MAILBOX_BAR); + if (!hw_mgt->mailbox_bar_hw_addr) { + dev_err(&pdev->dev, "Mailbox bar ioremap failed\n"); + ret =3D -EIO; + goto mailbox_ioremap_err; + } + + spin_lock_init(&hw_mgt->reg_lock); + + ret =3D nbl_hw_setup_ops(common, hw_ops_tbl, *hw_mgt_leonis); + if (ret) + goto setup_ops_fail; + + (*hw_mgt_leonis)->ro_enable =3D pcie_relaxed_ordering_enabled(pdev); + return 0; + +setup_ops_fail: + iounmap(hw_mgt->mailbox_bar_hw_addr); +mailbox_ioremap_err: + iounmap(hw_mgt->hw_addr); +ioremap_err: + pci_release_selected_regions(pdev, bar_mask); +request_bar_region_fail: +setup_mgt_fail: + return ret; +} + +void nbl_hw_remove_leonis(struct nbl_adapter *adapter) +{ + int bar_mask =3D BIT(NBL_MEMORY_BAR) | BIT(NBL_MAILBOX_BAR); + struct nbl_common_info *common =3D &adapter->common; + struct nbl_hw_mgt_leonis **hw_mgt_leonis; + struct pci_dev *pdev =3D common->pdev; + u8 __iomem *mailbox_bar_hw_addr; + u8 __iomem *hw_addr; + + hw_mgt_leonis =3D + (struct nbl_hw_mgt_leonis **)&NBL_ADAP_TO_HW_MGT(adapter); + hw_addr =3D (*hw_mgt_leonis)->hw_mgt.hw_addr; + mailbox_bar_hw_addr =3D (*hw_mgt_leonis)->hw_mgt.mailbox_bar_hw_addr; + + iounmap(mailbox_bar_hw_addr); + iounmap(hw_addr); + pci_release_selected_regions(pdev, bar_mask); +} diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nb= l_hw_leonis.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis= /nbl_hw_leonis.h new file mode 100644 index 000000000000..240d356f18b0 --- /dev/null +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_le= onis.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0*/ +/* + * Copyright (c) 2025 Nebula Matrix Limited. + * Author: + */ + +#ifndef _NBL_HW_LEONIS_H_ +#define _NBL_HW_LEONIS_H_ + +#include "nbl_include.h" +#include "nbl_hw_reg.h" + +#endif diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nb= l_resource_leonis.c b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_= leonis/nbl_resource_leonis.c new file mode 100644 index 000000000000..bd395e607f5f --- /dev/null +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_resou= rce_leonis.c @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 Nebula Matrix Limited. + * Author: + */ + +#include "nbl_resource_leonis.h" + +static struct nbl_resource_ops res_ops =3D { +}; + +static int +nbl_res_setup_res_mgt(struct nbl_common_info *common, + struct nbl_resource_mgt_leonis **res_mgt_leonis) +{ + struct nbl_resource_info *resource_info; + struct device *dev =3D common->dev; + + *res_mgt_leonis =3D devm_kzalloc(dev, + sizeof(struct nbl_resource_mgt_leonis), + GFP_KERNEL); + if (!*res_mgt_leonis) + return -ENOMEM; + (&(*res_mgt_leonis)->res_mgt)->common =3D common; + + resource_info =3D + devm_kzalloc(dev, sizeof(struct nbl_resource_info), GFP_KERNEL); + if (!resource_info) + return -ENOMEM; + (&(*res_mgt_leonis)->res_mgt)->resource_info =3D resource_info; + + return 0; +} + +static int nbl_res_setup_ops(struct device *dev, + struct nbl_resource_ops_tbl **res_ops_tbl, + struct nbl_resource_mgt_leonis *res_mgt_leonis) +{ + *res_ops_tbl =3D devm_kzalloc(dev, sizeof(struct nbl_resource_ops_tbl), + GFP_KERNEL); + if (!*res_ops_tbl) + return -ENOMEM; + + (*res_ops_tbl)->ops =3D &res_ops; + (*res_ops_tbl)->priv =3D &res_mgt_leonis->res_mgt; + + return 0; +} + +static int nbl_res_start(struct nbl_resource_mgt_leonis *res_mgt_leonis, + struct nbl_func_caps caps) +{ + return 0; +} + +int nbl_res_init_leonis(struct nbl_adapter *adap, struct nbl_init_param *p= aram) +{ + struct nbl_channel_ops_tbl *chan_ops_tbl =3D adap->intf.channel_ops_tbl; + struct nbl_hw_ops_tbl *hw_ops_tbl =3D adap->intf.hw_ops_tbl; + struct nbl_common_info *common =3D &adap->common; + struct nbl_resource_ops_tbl **res_ops_tbl =3D + &adap->intf.resource_ops_tbl; + struct nbl_resource_mgt_leonis **mgt =3D + (struct nbl_resource_mgt_leonis **)&NBL_ADAP_TO_RES_MGT(adap); + struct device *dev =3D &adap->pdev->dev; + int ret =3D 0; + + ret =3D nbl_res_setup_res_mgt(common, mgt); + if (ret) + goto setup_mgt_fail; + + (&(*mgt)->res_mgt)->chan_ops_tbl =3D chan_ops_tbl; + (&(*mgt)->res_mgt)->hw_ops_tbl =3D hw_ops_tbl; + + ret =3D nbl_res_start(*mgt, param->caps); + if (ret) + goto start_fail; + + ret =3D nbl_res_setup_ops(dev, res_ops_tbl, *mgt); + if (ret) + goto setup_ops_fail; + + return 0; + +setup_ops_fail: +start_fail: +setup_mgt_fail: + return ret; +} + diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nb= l_resource_leonis.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_= leonis/nbl_resource_leonis.h new file mode 100644 index 000000000000..80925ff9e680 --- /dev/null +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_resou= rce_leonis.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0*/ +/* + * Copyright (c) 2025 Nebula Matrix Limited. + * Author: + */ + +#ifndef _NBL_RESOURCE_LEONIS_H_ +#define _NBL_RESOURCE_LEONIS_H_ + +#include "nbl_resource.h" + +#endif diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_reg.h b/d= rivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_reg.h new file mode 100644 index 000000000000..7367575ef10a --- /dev/null +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_reg.h @@ -0,0 +1,131 @@ +/* SPDX-License-Identifier: GPL-2.0*/ +/* + * Copyright (c) 2025 Nebula Matrix Limited. + * Author: + */ + +#ifndef _NBL_HW_REG_H_ +#define _NBL_HW_REG_H_ + +#include "nbl_core.h" + +#define NBL_MEMORY_BAR (0) +#define NBL_MAILBOX_BAR (2) +#define NBL_RDMA_NOTIFY_OFF (8192) +#define NBL_HW_DUMMY_REG (0x1300904) + +struct nbl_hw_mgt { + struct nbl_common_info *common; + u8 __iomem *hw_addr; + u8 __iomem *mailbox_bar_hw_addr; + u64 notify_offset; + u32 version; + u32 hw_size; + spinlock_t reg_lock; /* Protect reg access */ +}; + +static inline u32 rd32(u8 __iomem *addr, u64 reg) +{ + return readl(addr + (reg)); +} + +static inline void wr32_barrier(u8 __iomem *addr, u64 reg, u32 value) +{ + writel((value), (addr + (reg))); +} + +static inline void nbl_hw_rd_regs(struct nbl_hw_mgt *hw_mgt, u64 reg, u8 *= data, + u32 len) +{ + u32 size =3D len / 4; + u32 i =3D 0; + + if (len % 4) + return; + + spin_lock(&hw_mgt->reg_lock); + + for (i =3D 0; i < size; i++) + *(u32 *)(data + i * sizeof(u32)) =3D + rd32(hw_mgt->hw_addr, reg + i * sizeof(u32)); + spin_unlock(&hw_mgt->reg_lock); +} + +static inline void nbl_hw_wr_regs(struct nbl_hw_mgt *hw_mgt, u64 reg, + const u8 *data, u32 len) +{ + u32 size =3D len / 4; + u32 i =3D 0; + + if (len % 4) + return; + spin_lock(&hw_mgt->reg_lock); + for (i =3D 0; i < size; i++) + /* Used for emu, make sure that we won't write too frequently */ + wr32_barrier(hw_mgt->hw_addr, reg + i * sizeof(u32), + *(u32 *)(data + i * sizeof(u32))); + spin_unlock(&hw_mgt->reg_lock); +} + +static inline void nbl_hw_wr32(struct nbl_hw_mgt *hw_mgt, u64 reg, u32 val= ue) +{ + /* Used for emu, make sure that we won't write too frequently */ + wr32_barrier(hw_mgt->hw_addr, reg, value); +} + +static inline u32 nbl_hw_rd32(struct nbl_hw_mgt *hw_mgt, u64 reg) +{ + return rd32(hw_mgt->hw_addr, reg); +} + +static inline void nbl_mbx_wr32(struct nbl_hw_mgt *hw_mgt, u64 reg, u32 va= lue) +{ + writel((value), ((hw_mgt)->mailbox_bar_hw_addr + (reg))); +} + +static inline void nbl_flush_writes(struct nbl_hw_mgt *hw_mgt) +{ + nbl_hw_rd32(hw_mgt, NBL_HW_DUMMY_REG); +} + +static inline u32 nbl_mbx_rd32(struct nbl_hw_mgt *hw_mgt, u64 reg) +{ + return readl((hw_mgt)->mailbox_bar_hw_addr + (reg)); +} + +static inline void nbl_hw_read_mbx_regs(struct nbl_hw_mgt *hw_mgt, u64 reg, + u8 *data, u32 len) +{ + u32 i =3D 0; + + if (len % 4) + return; + + for (i =3D 0; i < len / 4; i++) + *(u32 *)(data + i * sizeof(u32)) =3D + nbl_mbx_rd32(hw_mgt, reg + i * sizeof(u32)); +} + +static inline void nbl_hw_write_mbx_regs(struct nbl_hw_mgt *hw_mgt, u64 re= g, + const u8 *data, u32 len) +{ + u32 i =3D 0; + + if (len % 4) + return; + + for (i =3D 0; i < len / 4; i++) + /* Used for emu, make sure that we won't write too frequently */ + nbl_mbx_wr32(hw_mgt, reg + i * sizeof(u32), + *(u32 *)(data + i * sizeof(u32))); +} + +/* Mgt structure for each product. + * Every indivisual mgt must have the common mgt as its first member, + * and contains its unique data structure in the reset of it. + */ +struct nbl_hw_mgt_leonis { + struct nbl_hw_mgt hw_mgt; + bool ro_enable; +}; +#endif diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_resource.h b= /drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_resource.h new file mode 100644 index 000000000000..8429eb263862 --- /dev/null +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_resource.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0*/ +/* + * Copyright (c) 2025 Nebula Matrix Limited. + * Author: + */ + +#ifndef _NBL_RESOURCE_H_ +#define _NBL_RESOURCE_H_ + +#include "nbl_core.h" + +struct nbl_resource_info { +}; + +struct nbl_resource_mgt { + struct nbl_common_info *common; + struct nbl_resource_info *resource_info; + struct nbl_channel_ops_tbl *chan_ops_tbl; + struct nbl_hw_ops_tbl *hw_ops_tbl; + struct nbl_interrupt_mgt *intr_mgt; +}; + +/* Mgt structure for each product. + * Every indivisual mgt must have the common mgt as its first member, and + * contains its unique data structure in the reset of it. + */ +struct nbl_resource_mgt_leonis { + struct nbl_resource_mgt res_mgt; +}; +#endif diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_cha= nnel.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_channel= .h new file mode 100644 index 000000000000..d87c9c5416d2 --- /dev/null +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_channel.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0*/ +/* + * Copyright (c) 2025 Nebula Matrix Limited. + * Author: + */ + +#ifndef _NBL_DEF_CHANNEL_H_ +#define _NBL_DEF_CHANNEL_H_ + +#include +#include "nbl_include.h" + +enum nbl_channel_type { + NBL_CHAN_TYPE_MAILBOX, + NBL_CHAN_TYPE_MAX +}; + +struct nbl_channel_ops { +}; + +struct nbl_channel_ops_tbl { + struct nbl_channel_ops *ops; + struct nbl_channel_mgt *priv; +}; + +#endif diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_com= mon.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_common.h new file mode 100644 index 000000000000..b98bbc726308 --- /dev/null +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_common.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0*/ +/* + * Copyright (c) 2025 Nebula Matrix Limited. + * Author: + */ + +#ifndef _NBL_DEF_COMMON_H_ +#define _NBL_DEF_COMMON_H_ + +#include "nbl_include.h" + +struct nbl_common_info { + struct pci_dev *pdev; + struct device *dev; + u32 msg_enable; + u16 vsi_id; + u8 eth_id; + u8 logic_eth_id; + u8 eth_mode; + + u8 function; + u8 devid; + u8 bus; + u8 hw_bus; + u16 mgt_pf; + + bool pci_using_dac; + u8 is_ocp; + enum nbl_product_type product_type; + u8 is_ctrl; +}; + +#endif diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_dev= .h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_dev.h new file mode 100644 index 000000000000..b69bc3320c50 --- /dev/null +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_dev.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0*/ +/* + * Copyright (c) 2025 Nebula Matrix Limited. + * Author: + */ + +#ifndef _NBL_DEF_DEV_H_ +#define _NBL_DEF_DEV_H_ + +#include "nbl_include.h" + +#endif diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_dis= patch.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_dispat= ch.h new file mode 100644 index 000000000000..9ece74c48898 --- /dev/null +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_dispatch.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0*/ +/* + * Copyright (c) 2025 Nebula Matrix Limited. + * Author: + */ + +#ifndef _NBL_DEF_DISPATCH_H_ +#define _NBL_DEF_DISPATCH_H_ + +#include "nbl_include.h" +struct nbl_dispatch_mgt; +enum { + NBL_DISP_CTRL_LVL_NEVER =3D 0, + NBL_DISP_CTRL_LVL_MGT, + NBL_DISP_CTRL_LVL_NET, + NBL_DISP_CTRL_LVL_ALWAYS, + NBL_DISP_CTRL_LVL_MAX, +}; + +struct nbl_dispatch_ops { +}; + +struct nbl_dispatch_ops_tbl { + struct nbl_dispatch_ops *ops; + struct nbl_dispatch_mgt *priv; +}; + +#endif diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_hw.= h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_hw.h new file mode 100644 index 000000000000..80ebddec55f8 --- /dev/null +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_hw.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0*/ +/* + * Copyright (c) 2025 Nebula Matrix Limited. + * Author: + */ + +#ifndef _NBL_DEF_HW_H_ +#define _NBL_DEF_HW_H_ + +#include "nbl_include.h" +struct nbl_hw_mgt; +struct nbl_hw_ops { +}; + +struct nbl_hw_ops_tbl { + struct nbl_hw_ops *ops; + struct nbl_hw_mgt *priv; +}; + +#endif diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_res= ource.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_resour= ce.h new file mode 100644 index 000000000000..74a6a7ee9af9 --- /dev/null +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_resource.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0*/ +/* + * Copyright (c) 2025 Nebula Matrix Limited. + * Author: + */ + +#ifndef _NBL_DEF_RESOURCE_H_ +#define _NBL_DEF_RESOURCE_H_ + +#include "nbl_include.h" +struct nbl_resource_mgt; + +struct nbl_resource_ops { +}; + +struct nbl_resource_ops_tbl { + struct nbl_resource_ops *ops; + struct nbl_resource_mgt *priv; +}; + +#endif diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_include= .h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_include.h index f12bf019dfee..f58b4dbb0aab 100644 --- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_include.h +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_include.h @@ -8,10 +8,15 @@ #define _NBL_INCLUDE_H_ =20 #include - +#include /* ------ Basic definitions ------- */ #define NBL_DRIVER_NAME "nbl_core" =20 +enum nbl_product_type { + NBL_LEONIS_TYPE, + NBL_PRODUCT_MAX, +}; + struct nbl_func_caps { u32 has_ctrl:1; u32 has_net:1; @@ -20,4 +25,10 @@ struct nbl_func_caps { u32 rsv:28; }; =20 +struct nbl_init_param { + struct nbl_func_caps caps; + enum nbl_product_type product_type; + bool pci_using_dac; +}; + #endif diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_product= _base.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_product_ba= se.h new file mode 100644 index 000000000000..ad072fa18262 --- /dev/null +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_product_base.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0*/ +/* + * Copyright (c) 2025 Nebula Matrix Limited. + * Author: + */ + +#ifndef _NBL_DEF_PRODUCT_BASE_H_ +#define _NBL_DEF_PRODUCT_BASE_H_ + +#include "nbl_include.h" +struct nbl_adapter; +struct nbl_product_base_ops { + int (*hw_init)(struct nbl_adapter *p, struct nbl_init_param *param); + void (*hw_remove)(struct nbl_adapter *p); + int (*res_init)(struct nbl_adapter *p, struct nbl_init_param *param); + int (*chan_init)(struct nbl_adapter *p, struct nbl_init_param *param); + void (*chan_remove)(struct nbl_adapter *p); +}; + +#endif diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_main.c b/drivers/ne= t/ethernet/nebula-matrix/nbl/nbl_main.c index 63bba8211654..a16a685e4f29 100644 --- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_main.c +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_main.c @@ -7,14 +7,194 @@ #include #include "nbl_core.h" =20 +static struct nbl_product_base_ops nbl_product_base_ops[NBL_PRODUCT_MAX] = =3D { + { + .hw_init =3D nbl_hw_init_leonis, + .hw_remove =3D nbl_hw_remove_leonis, + .res_init =3D nbl_res_init_leonis, + .chan_init =3D nbl_chan_init_common, + .chan_remove =3D nbl_chan_remove_common, + }, +}; + +int nbl_core_start(struct nbl_adapter *adapter, struct nbl_init_param *par= am) +{ + int ret =3D 0; + + ret =3D nbl_dev_start(adapter, param); + return ret; +} + +void nbl_core_stop(struct nbl_adapter *adapter) +{ + nbl_dev_stop(adapter); +} + +static void +nbl_core_setup_product_ops(struct nbl_adapter *adapter, + struct nbl_init_param *param, + struct nbl_product_base_ops **product_base_ops) +{ + adapter->product_base_ops =3D &nbl_product_base_ops[param->product_type]; + *product_base_ops =3D adapter->product_base_ops; +} + +struct nbl_adapter *nbl_core_init(struct pci_dev *pdev, + struct nbl_init_param *param) +{ + struct nbl_product_base_ops *product_base_ops; + struct nbl_common_info *common; + struct nbl_adapter *adapter; + int ret =3D 0; + + adapter =3D devm_kzalloc(&pdev->dev, sizeof(struct nbl_adapter), + GFP_KERNEL); + if (!adapter) + return NULL; + + adapter->pdev =3D pdev; + common =3D &adapter->common; + + common->pdev =3D pdev; + common->dev =3D &pdev->dev; + common->is_ocp =3D param->caps.is_ocp; + common->is_ctrl =3D param->caps.has_ctrl; + common->pci_using_dac =3D param->pci_using_dac; + common->function =3D PCI_FUNC(pdev->devfn); + common->devid =3D PCI_SLOT(pdev->devfn); + common->bus =3D pdev->bus->number; + common->product_type =3D param->product_type; + + memcpy(&adapter->init_param, param, sizeof(adapter->init_param)); + + nbl_core_setup_product_ops(adapter, param, &product_base_ops); + + /* + *every product's hw/chan/res layer has a great difference, + *so call their own init ops + */ + ret =3D product_base_ops->hw_init(adapter, param); + if (ret) + goto hw_init_fail; + + ret =3D product_base_ops->chan_init(adapter, param); + if (ret) + goto chan_init_fail; + + ret =3D product_base_ops->res_init(adapter, param); + if (ret) + goto res_init_fail; + + ret =3D nbl_disp_init(adapter, param); + if (ret) + goto disp_init_fail; + + ret =3D nbl_dev_init(adapter, param); + if (ret) + goto dev_init_fail; + return adapter; + +dev_init_fail: +disp_init_fail: +res_init_fail: + product_base_ops->chan_remove(adapter); +chan_init_fail: + product_base_ops->hw_remove(adapter); +hw_init_fail: + return NULL; +} + +void nbl_core_remove(struct nbl_adapter *adapter) +{ + struct nbl_product_base_ops *product_base_ops; + + product_base_ops =3D adapter->product_base_ops; + product_base_ops->chan_remove(adapter); + product_base_ops->hw_remove(adapter); +} + +static void nbl_get_func_param(struct pci_dev *pdev, kernel_ulong_t driver= _data, + struct nbl_init_param *param) +{ + param->caps.has_ctrl =3D NBL_CAP_IS_CTRL(driver_data); + param->caps.has_net =3D NBL_CAP_IS_NET(driver_data); + param->caps.is_nic =3D NBL_CAP_IS_NIC(driver_data); + param->caps.is_ocp =3D NBL_CAP_IS_OCP(driver_data); + + if (NBL_CAP_IS_LEONIS(driver_data)) + param->product_type =3D NBL_LEONIS_TYPE; + + /* + * Leonis only PF0 has ctrl capability, but PF0's pcie device_id + * is same with other PF.So hanle it special. + */ + if (param->product_type =3D=3D NBL_LEONIS_TYPE && + (PCI_FUNC(pdev->devfn) =3D=3D 0)) + param->caps.has_ctrl =3D 1; +} + static int nbl_probe(struct pci_dev *pdev, const struct pci_device_id __always_unused *id) { + struct nbl_init_param param =3D { { 0 } }; + struct nbl_adapter *adapter =3D NULL; + struct device *dev =3D &pdev->dev; + int err; + + if (pci_enable_device(pdev)) { + dev_err(&pdev->dev, "Failed to enable PCI device\n"); + return -ENODEV; + } + + param.pci_using_dac =3D true; + nbl_get_func_param(pdev, id->driver_data, ¶m); + + err =3D dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); + if (err) { + dev_dbg(dev, "Configure DMA 64 bit mask failed, err =3D %d\n", + err); + param.pci_using_dac =3D false; + err =3D dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); + if (err) { + dev_err(dev, + "Configure DMA 32 bit mask failed, err =3D %d\n", + err); + goto configure_dma_err; + } + } + pci_set_master(pdev); + pci_save_state(pdev); + adapter =3D nbl_core_init(pdev, ¶m); + if (!adapter) { + dev_err(dev, "Nbl adapter init fail\n"); + err =3D -ENOMEM; + goto adapter_init_err; + } + pci_set_drvdata(pdev, adapter); + err =3D nbl_core_start(adapter, ¶m); + if (err) + goto core_start_err; return 0; +core_start_err: + nbl_core_remove(adapter); +adapter_init_err: + pci_clear_master(pdev); +configure_dma_err: + pci_disable_device(pdev); + return err; } =20 static void nbl_remove(struct pci_dev *pdev) { + struct nbl_adapter *adapter =3D pci_get_drvdata(pdev); + + pci_disable_sriov(pdev); + + nbl_core_stop(adapter); + nbl_core_remove(adapter); + + pci_clear_master(pdev); + pci_disable_device(pdev); } =20 #define NBL_VENDOR_ID (0x1F0F) --=20 2.47.3 From nobody Sun Feb 8 00:11:39 2026 Received: from out28-99.mail.aliyun.com (out28-99.mail.aliyun.com [115.124.28.99]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C704313D638; Fri, 6 Feb 2026 02:18:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.28.99 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770344305; cv=none; b=JfeDIc1WTPb6DSwlAamGqITwiHZS1FGTF/czLpM0XcWUgkGmvFkaSjJXkd4XYbgMdwi+MjkR4/j3SBkb20Nv3IsaVmEyUmPjndGOhQAK/ermVcHZQgj888zyrx25IAzuaZDx4GK+a06hVd5tKWR6+XCIyHM+4uY2Ar0C3+4p/hI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770344305; c=relaxed/simple; bh=tKCG8sP90cCqsJbny488wEwBl1xxgTdFR/ic01HbbQM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=pHmVRkL3AjBBfYzEzeNz1ANW27GDVBJ/qgtiDZEnvnYt+5+s3Po49/xYdWtE5hX66sbpJkcHmG5JQUWf6RpkAgM7/McRfjzV9rv65b8bINUOM/igFEz0U/ERG2XPs2AVO9S3QEVj+axpH936WqV6hKk/DQRELf/htCDoITf3IJs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=nebula-matrix.com; spf=pass smtp.mailfrom=nebula-matrix.com; arc=none smtp.client-ip=115.124.28.99 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=nebula-matrix.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nebula-matrix.com Received: from localhost.localdomain(mailfrom:illusion.wang@nebula-matrix.com fp:SMTPD_---.gQHg4g6_1770344292 cluster:ay29) by smtp.aliyun-inc.com; Fri, 06 Feb 2026 10:18:13 +0800 From: "illusion.wang" To: dimon.zhao@nebula-matrix.com, illusion.wang@nebula-matrix.com, alvin.wang@nebula-matrix.com, sam.chen@nebula-matrix.com, netdev@vger.kernel.org Cc: andrew+netdev@lunn.ch, corbet@lwn.net, kuba@kernel.org, linux-doc@vger.kernel.org, lorenzo@kernel.org, pabeni@redhat.com, horms@kernel.org, vadim.fedorenko@linux.dev, lukas.bulwahn@redhat.com, edumazet@google.com, linux-kernel@vger.kernel.org (open list) Subject: [PATCH v4 net-next 03/11] net/nebula-matrix: add chip related definitions Date: Fri, 6 Feb 2026 10:15:55 +0800 Message-ID: <20260206021608.85381-4-illusion.wang@nebula-matrix.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260206021608.85381-1-illusion.wang@nebula-matrix.com> References: <20260206021608.85381-1-illusion.wang@nebula-matrix.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" 1. nbl_hw.h/nbl_hw_leonis.h chip-related reg definitions 2. nbl_hw_leonis_regs.c P4 configuration that will be invoked during chip initialization Signed-off-by: illusion.wang --- .../net/ethernet/nebula-matrix/nbl/Makefile | 1 + .../nebula-matrix/nbl/nbl_hw/nbl_hw.h | 128 + .../nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.h | 1172 ++++++- .../nbl_hw/nbl_hw_leonis/nbl_hw_leonis_regs.c | 2902 +++++++++++++++++ .../nbl_hw/nbl_hw_leonis/nbl_hw_leonis_regs.h | 12 + 5 files changed, 4214 insertions(+), 1 deletion(-) create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw.h create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_le= onis/nbl_hw_leonis_regs.c create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_le= onis/nbl_hw_leonis_regs.h diff --git a/drivers/net/ethernet/nebula-matrix/nbl/Makefile b/drivers/net/= ethernet/nebula-matrix/nbl/Makefile index 6d04e23c0cae..c88c49dafa0d 100644 --- a/drivers/net/ethernet/nebula-matrix/nbl/Makefile +++ b/drivers/net/ethernet/nebula-matrix/nbl/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_NBL_CORE) :=3D nbl_core.o nbl_core-objs +=3D nbl_channel/nbl_channel.o \ nbl_hw/nbl_hw_leonis/nbl_hw_leonis.o \ nbl_hw/nbl_hw_leonis/nbl_resource_leonis.o \ + nbl_hw/nbl_hw_leonis/nbl_hw_leonis_regs.o \ nbl_core/nbl_dispatch.o \ nbl_core/nbl_dev.o \ nbl_main.o diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw.h b/drive= rs/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw.h new file mode 100644 index 000000000000..f657c1e6a5ad --- /dev/null +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw.h @@ -0,0 +1,128 @@ +/* SPDX-License-Identifier: GPL-2.0*/ +/* + * Copyright (c) 2025 Nebula Matrix Limited. + * Author: + */ + +#ifndef _NBL_HW_H_ +#define _NBL_HW_H_ + +#include "nbl_include.h" + +#define NBL_MAX_ETHERNET (4) + +#define NBL_QID_MAP_TABLE_ENTRIES (4096) +#define NBL_EPRO_PF_RSS_RET_TBL_DEPTH (4096) +#define NBL_EPRO_RSS_RET_TBL_DEPTH (8192 * 2) +#define NBL_EPRO_RSS_ENTRY_SIZE_UNIT (16) + +#define NBL_EPRO_PF_RSS_RET_TBL_COUNT (512) +#define NBL_EPRO_PF_RSS_ENTRY_SIZE (5) + +#define NBL_EPRO_RSS_ENTRY_MAX_COUNT (512) +#define NBL_EPRO_RSS_ENTRY_MAX_SIZE (4) + +#pragma pack(1) +union nbl_action_data { + union dport_act { + struct { + /* port_type =3D SET_DPORT_TYPE_ETH_LAG, set the eth and + * lag field. + */ + u16 dport_info:10; + u16 dport_type:2; + #define FWD_DPORT_TYPE_ETH (0) + #define FWD_DPORT_TYPE_LAG (1) + #define FWD_DPORT_TYPE_VSI (2) + u16 dport_id:4; + #define FWD_DPORT_ID_HOST_TLS (0) + #define FWD_DPORT_ID_ECPU_TLS (1) + #define FWD_DPORT_ID_HOST_RDMA (2) + #define FWD_DPORT_ID_ECPU_RDMA (3) + #define FWD_DPORT_ID_EMP (4) + #define FWD_DPORT_ID_BMC (5) + #define FWD_DPORT_ID_LOOP_BACK (7) + #define FWD_DPORT_ID_ETH0 (8) + #define FWD_DPORT_ID_ETH1 (9) + #define FWD_DPORT_ID_ETH2 (10) + #define FWD_DPORT_ID_ETH3 (11) + } fwd_dport; + + struct { + /* port_type =3D SET_DPORT_TYPE_ETH_LAG, + * set the eth and lag field. + */ + u16 eth_id:2; + u16 lag_id:2; + u16 eth_vld:1; + u16 lag_vld:1; + u16 rsv:4; + u16 port_type:2; + u16 next_stg_sel:2; + u16 upcall_flag:2; + } down; + + struct { + /* port_type =3D SET_DPORT_TYPE_VSI_HOST and + * SET_DPORT_TYPE_VSI_ECPU, + * set the port_id field as the vsi_id. + * port_type =3D SET_DPORT_TYPE_SP_PORT, set the port_id + * as the defined PORT_TYPE_SP_*. + */ + u16 port_id:10; + #define PORT_TYPE_SP_DROP (0x3FF) + #define PORT_TYPE_SP_GLB_LB (0x3FE) + #define PORT_TYPE_SP_BMC (0x3FD) + #define PORT_TYPE_SP_EMP (0x3FC) + u16 port_type:2; + #define SET_DPORT_TYPE_VSI_HOST (0) + #define SET_DPORT_TYPE_VSI_ECPU (1) + #define SET_DPORT_TYPE_ETH_LAG (2) + #define SET_DPORT_TYPE_SP_PORT (3) + u16 next_stg_sel:2; + #define NEXT_STG_SEL_NONE (0) + #define NEXT_STG_SEL_ACL_S0 (1) + #define NEXT_STG_SEL_EPRO (2) + #define NEXT_STG_SEL_BYPASS (3) + u16 upcall_flag:2; + #define AUX_KEEP_FWD_TYPE (0) + #define AUX_FWD_TYPE_NML_FWD (1) + #define AUX_FWD_TYPE_UPCALL (2) + } up; + } dport; + + struct dqueue_act { + u16 que_id:11; + u16 rsv:5; + } dqueue; + + struct mcc_id_act { + u16 mcc_id:13; + u16 pri:1; + #define NBL_MCC_PRI_HIGH (0) + #define NBL_MCC_PRI_LOW (1) + u16 rsv:2; + } mcc_idx; + + struct set_aux_act { + u16 nstg_val:4; + u16 nstg_vld:1; + u16 ftype_val:3; + u16 ftype_vld:1; + u16 pkt_cos_val:3; + u16 pcos_vld:1; + u16 rsv:1; + #define NBL_SET_AUX_CLR_FLG (0) + #define NBL_SET_AUX_SET_FLG (1) + #define NBL_SET_AUX_SET_AUX (2) + u16 sub_id:2; + } set_aux; + + u16 data; +}; + +#pragma pack() + +#define NBL_SPORT_ETH_OFFSET 8 + +#endif diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nb= l_hw_leonis.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis= /nbl_hw_leonis.h index 240d356f18b0..9000650256ca 100644 --- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_le= onis.h +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_le= onis.h @@ -7,7 +7,1177 @@ #ifndef _NBL_HW_LEONIS_H_ #define _NBL_HW_LEONIS_H_ =20 -#include "nbl_include.h" +#include "nbl_hw.h" #include "nbl_hw_reg.h" =20 +#define NBL_DRAIN_WAIT_TIMES (30000) +#define NBL_DRIVER_STATUS_REG (0x1300444) +#define NBL_DRIVER_STATUS_BIT (16) + +#pragma pack(1) + +/* ---------- REG BASE ADDR ---------- */ +#define NBL_LB_PCIEX16_TOP_BASE (0x01500000) +/* PPE modules base addr */ +#define NBL_PPE_FEM_BASE (0x00a04000) +#define NBL_PPE_IPRO_BASE (0x00b04000) +#define NBL_PPE_PP0_BASE (0x00b14000) +#define NBL_PPE_PP1_BASE (0x00b24000) +#define NBL_PPE_PP2_BASE (0x00b34000) +#define NBL_PPE_MCC_BASE (0x00b44000) +#define NBL_PPE_ACL_BASE (0x00b64000) +#define NBL_PPE_CAP_BASE (0x00e64000) +#define NBL_PPE_EPRO_BASE (0x00e74000) +#define NBL_PPE_DPRBAC_BASE (0x00904000) +#define NBL_PPE_UPRBAC_BASE (0x0000C000) +/* Interface modules base addr */ +#define NBL_INTF_HOST_PCOMPLETER_BASE (0x00f08000) +#define NBL_INTF_HOST_PADPT_BASE (0x00f4c000) +#define NBL_INTF_HOST_CTRLQ_BASE (0x00f8c000) +#define NBL_INTF_HOST_VDPA_NET_BASE (0x00f98000) +#define NBL_INTF_HOST_CMDQ_BASE (0x00fa0000) +#define NBL_INTF_HOST_MAILBOX_BASE (0x00fb0000) +#define NBL_INTF_HOST_PCIE_BASE (0X01504000) +#define NBL_INTF_HOST_PCAP_BASE (0X015a4000) +/* DP modules base addr */ +#define NBL_DP_URMUX_BASE (0x00008000) +#define NBL_DP_UPRBAC_BASE (0x0000C000) +#define NBL_DP_UPA_BASE (0x0008C000) +#define NBL_DP_USTORE_BASE (0x00104000) +#define NBL_DP_UPMEM_BASE (0x00108000) +#define NBL_DP_UBM_BASE (0x0010c000) +#define NBL_DP_UQM_BASE (0x00114000) +#define NBL_DP_USTAT_BASE (0x0011c000) +#define NBL_DP_UPED_BASE (0x0015c000) +#define NBL_DP_UCAR_BASE (0x00e84000) +#define NBL_DP_UL4S_BASE (0x00204000) +#define NBL_DP_UVN_BASE (0x00244000) +#define NBL_DP_DSCH_BASE (0x00404000) +#define NBL_DP_SHAPING_BASE (0x00504000) +#define NBL_DP_DVN_BASE (0x00514000) +#define NBL_DP_DL4S_BASE (0x00614000) +#define NBL_DP_DRMUX_BASE (0x00654000) +#define NBL_DP_DSTORE_BASE (0x00704000) +#define NBL_DP_DPMEM_BASE (0x00708000) +#define NBL_DP_DBM_BASE (0x0070c000) +#define NBL_DP_DQM_BASE (0x00714000) +#define NBL_DP_DSTAT_BASE (0x0071c000) +#define NBL_DP_DPED_BASE (0x0075c000) +#define NBL_DP_DPA_BASE (0x0085c000) +#define NBL_DP_DPRBAC_BASE (0x00904000) +#define NBL_DP_DDMUX_BASE (0x00984000) +#define NBL_DP_LB_DDP_BUF_BASE (0x00000000) +#define NBL_DP_LB_DDP_OUT_BASE (0x00000000) +#define NBL_DP_LB_DDP_DIST_BASE (0x00000000) +#define NBL_DP_LB_DDP_IN_BASE (0x00000000) +#define NBL_DP_LB_UDP_BUF_BASE (0x00000000) +#define NBL_DP_LB_UDP_OUT_BASE (0x00000000) +#define NBL_DP_LB_UDP_DIST_BASE (0x00000000) +#define NBL_DP_LB_UDP_IN_BASE (0x00000000) +#define NBL_DP_DL4S_BASE (0x00614000) +#define NBL_DP_UL4S_BASE (0x00204000) + +/* -------- LB -------- */ +#define NBL_LB_PF_CONFIGSPACE_SELECT_OFFSET (0x81100000) +#define NBL_LB_PF_CONFIGSPACE_SELECT_STRIDE (0x00100000) +#define NBL_LB_PF_CONFIGSPACE_BASE_ADDR (NBL_LB_PCIEX16_TOP_BASE + 0x00024= 000) +#define NBL_LB_PCIEX16_TOP_AHB (NBL_LB_PCIEX16_TOP_BASE + 0x00000020) + +#define NBL_SRIOV_CAPS_OFFSET (0x140) + +/* -------- MAILBOX BAR2 ----- */ +#define NBL_MAILBOX_NOTIFY_ADDR (0x00000000) +#define NBL_MAILBOX_BAR_REG (0x00000000) +#define NBL_MAILBOX_QINFO_CFG_RX_TABLE_ADDR (0x10) +#define NBL_MAILBOX_QINFO_CFG_TX_TABLE_ADDR (0x20) +#define NBL_MAILBOX_QINFO_CFG_DBG_TABLE_ADDR (0x30) + +/* -------- MAILBOX -------- */ + +/* mailbox BAR qinfo_cfg_dbg_table */ +struct nbl_mailbox_qinfo_cfg_dbg_tbl { + u16 rx_drop; + u16 rx_get; + u16 tx_drop; + u16 tx_out; + u16 rx_hd_ptr; + u16 tx_hd_ptr; + u16 rx_tail_ptr; + u16 tx_tail_ptr; +}; + +/* mailbox BAR qinfo_cfg_table */ +struct nbl_mailbox_qinfo_cfg_table { + u32 queue_base_addr_l; + u32 queue_base_addr_h; + u32 queue_size_bwind:4; + u32 rsv1:28; + u32 queue_rst:1; + u32 queue_en:1; + u32 dif_err:1; + u32 ptr_err:1; + u32 rsv2:28; +}; + +/* -------- MAILBOX BAR0 ----- */ +/* mailbox qinfo_map_table */ +#define NBL_MAILBOX_QINFO_MAP_REG_ARR(func_id) \ + (NBL_INTF_HOST_MAILBOX_BASE + 0x00001000 + \ + (func_id) * sizeof(struct nbl_mailbox_qinfo_map_table)) + +/* MAILBOX qinfo_map_table */ +struct nbl_mailbox_qinfo_map_table { + u32 function:3; + u32 devid:5; + u32 bus:8; + u32 msix_idx:13; + u32 msix_idx_valid:1; + u32 rsv:2; +}; + +/* -------- HOST_PCIE -------- */ +#define NBL_PCIE_HOST_K_PF_MASK_REG (NBL_INTF_HOST_PCIE_BASE + 0x00001004) +#define NBL_PCIE_HOST_K_PF_FID(pf_id) \ + (NBL_INTF_HOST_PCIE_BASE + 0x0000106C + 4 * (pf_id)) +#define NBL_PCIE_HOST_TL_CFG_BUSDEV (NBL_INTF_HOST_PCIE_BASE + 0x11040) + +/* -------- HOST_PADPT -------- */ +#define NBL_HOST_PADPT_HOST_CFG_FC_PD_DN (NBL_INTF_HOST_PADPT_BASE + 0x000= 00160) +#define NBL_HOST_PADPT_HOST_CFG_FC_PH_DN (NBL_INTF_HOST_PADPT_BASE + 0x000= 00164) +#define NBL_HOST_PADPT_HOST_CFG_FC_NPH_DN \ + (NBL_INTF_HOST_PADPT_BASE + 0x0000016C) +#define NBL_HOST_PADPT_HOST_CFG_FC_CPLH_UP \ + (NBL_INTF_HOST_PADPT_BASE + 0x00000170) +/* host_padpt host_msix_info */ +#define NBL_PADPT_ABNORMAL_MSIX_VEC (NBL_INTF_HOST_PADPT_BASE + 0x00000200) +#define NBL_PADPT_ABNORMAL_TIMEOUT (NBL_INTF_HOST_PADPT_BASE + 0x00000204) +#define NBL_PADPT_HOST_MSIX_INFO_REG_ARR(vector_id) \ + (NBL_INTF_HOST_PADPT_BASE + 0x00010000 + \ + (vector_id) * sizeof(struct nbl_host_msix_info)) +/* host_padpt host_vnet_qinfo */ +#define NBL_PADPT_HOST_VNET_QINFO_REG_ARR(queue_id) \ + (NBL_INTF_HOST_PADPT_BASE + 0x00008000 + \ + (queue_id) * sizeof(struct nbl_host_vnet_qinfo)) + +struct nbl_host_msix_info { + u32 intrl_pnum:16; + u32 intrl_rate:16; + u32 function:3; + u32 devid:5; + u32 bus:8; + u32 valid:1; + u32 msix_mask_en:1; + u32 rsv:14; +}; + +/* host_padpt host_vnet_qinfo */ +struct nbl_host_vnet_qinfo { + u32 function_id:3; + u32 device_id:5; + u32 bus_id:8; + u32 msix_idx:13; + u32 msix_idx_valid:1; + u32 log_en:1; + u32 valid:1; + u32 tph_en:1; + u32 ido_en:1; + u32 rlo_en:1; + u32 rsv0:29; +}; + +struct nbl_msix_notify { + u32 glb_msix_idx:13; + u32 rsv1:3; + u32 mask:1; + u32 rsv2:15; +}; + +/* -------- HOST_PCOMPLETER -------- */ +/* pcompleter_host pcompleter_host_virtio_qid_map_table */ +#define NBL_PCOMPLETER_QID_MAP_REG_ARR(select, i) \ + (NBL_INTF_HOST_PCOMPLETER_BASE + 0x00010000 + \ + (select) * NBL_QID_MAP_TABLE_ENTRIES * \ + sizeof(struct nbl_virtio_qid_map_table) + \ + (i) * sizeof(struct nbl_virtio_qid_map_table)) +#define NBL_PCOMPLETER_FUNCTION_MSIX_MAP_REG_ARR(i) \ + (NBL_INTF_HOST_PCOMPLETER_BASE + 0x00004000 + \ + (i) * sizeof(struct nbl_function_msix_map)) +#define NBL_PCOMPLETER_HOST_MSIX_FID_TABLE(i) \ + (NBL_INTF_HOST_PCOMPLETER_BASE + 0x0003a000 + \ + (i) * sizeof(struct nbl_pcompleter_host_msix_fid_table)) +#define NBL_PCOMPLETER_INT_STATUS (NBL_INTF_HOST_PCOMPLETER_BASE + 0x00000= 000) +#define NBL_PCOMPLETER_TLP_OUT_DROP_CNT \ + (NBL_INTF_HOST_PCOMPLETER_BASE + 0x00002430) + +/* pcompleter_host pcompleter_host_virtio_table_ready */ +#define NBL_PCOMPLETER_QUEUE_TABLE_READY_REG \ + (NBL_INTF_HOST_PCOMPLETER_BASE + 0x0000110C) +/* pcompleter_host pcompleter_host_virtio_table_select */ +#define NBL_PCOMPLETER_QUEUE_TABLE_SELECT_REG \ + (NBL_INTF_HOST_PCOMPLETER_BASE + 0x00001110) + +#define NBL_PCOMPLETER_MSIX_NOTIRY_OFFSET (0x1020) + +#define NBL_REG_WRITE_MAX_TRY_TIMES 2 + +/* pcompleter_host virtio_qid_map_table */ +struct nbl_virtio_qid_map_table { + u32 local_qid:9; + u32 notify_addr_l:23; + u32 notify_addr_h; + u32 global_qid:12; + u32 ctrlq_flag:1; + u32 rsv1:19; + u32 rsv2; +}; + +struct nbl_pcompleter_host_msix_fid_table { + u32 fid:10; + u32 vld:1; + u32 rsv:21; +}; + +struct nbl_function_msix_map { + u64 msix_map_base_addr; + u32 function:3; + u32 devid:5; + u32 bus:8; + u32 valid:1; + u32 rsv0:15; + u32 rsv1; +}; + +struct nbl_queue_table_select { + u32 select:1; + u32 rsv:31; +}; + +struct nbl_queue_table_ready { + u32 ready:1; + u32 rsv:31; +}; + +/* IPRO ipro_queue_tbl */ +struct nbl_ipro_queue_tbl { + u32 vsi_id:10; + u32 vsi_en:1; + u32 rsv:21; +}; + +/* ---------- DPED ---------- */ +#define NBL_DPED_VLAN_OFFSET (NBL_DP_DPED_BASE + 0x000003F4) +#define NBL_DPED_DSCP_OFFSET_0 (NBL_DP_DPED_BASE + 0x000003F8) +#define NBL_DPED_DSCP_OFFSET_1 (NBL_DP_DPED_BASE + 0x000003FC) + +/* DPED dped_hw_edt_prof */ +#define NBL_DPED_HW_EDT_PROF_TABLE(i) \ + (NBL_DP_DPED_BASE + 0x00001000 + \ + (i) * sizeof(struct ped_hw_edit_profile)) +/* DPED dped_l4_ck_cmd_40 */ + +/* DPED hw_edt_prof/ UPED hw_edt_prof */ +struct ped_hw_edit_profile { + u32 l4_len:2; +#define NBL_PED_L4_LEN_MDY_CMD_0 (0) +#define NBL_PED_L4_LEN_MDY_CMD_1 (1) +#define NBL_PED_L4_LEN_MDY_DISABLE (2) + u32 l3_len:2; +#define NBL_PED_L3_LEN_MDY_CMD_0 (0) +#define NBL_PED_L3_LEN_MDY_CMD_1 (1) +#define NBL_PED_L3_LEN_MDY_DISABLE (2) + u32 l4_ck:3; +#define NBL_PED_L4_CKSUM_CMD_0 (0) +#define NBL_PED_L4_CKSUM_CMD_1 (1) +#define NBL_PED_L4_CKSUM_CMD_2 (2) +#define NBL_PED_L4_CKSUM_CMD_3 (3) +#define NBL_PED_L4_CKSUM_CMD_4 (4) +#define NBL_PED_L4_CKSUM_CMD_5 (5) +#define NBL_PED_L4_CKSUM_CMD_6 (6) +#define NBL_PED_L4_CKSUM_DISABLE (7) + u32 l3_ck:1; +#define NBL_PED_L3_CKSUM_ENABLE (1) +#define NBL_PED_L3_CKSUM_DISABLE (0) + u32 l4_ck_zero_free:1; +#define NBL_PED_L4_CKSUM_ZERO_FREE_ENABLE (1) +#define NBL_PED_L4_CKSUM_ZERO_FREE_DISABLE (0) + u32 rsv:23; +}; + +/* ---------- UPED ---------- */ +/* UPED uped_hw_edt_prof */ +#define NBL_UPED_HW_EDT_PROF_TABLE(i) \ + (NBL_DP_UPED_BASE + 0x00001000 + \ + (i) * sizeof(struct ped_hw_edit_profile)) + +/* --------- SHAPING --------- */ +#define NBL_SHAPING_NET_TIMMING_ADD_ADDR (NBL_DP_SHAPING_BASE + 0x00000300) +#define NBL_SHAPING_NET(i) \ + (NBL_DP_SHAPING_BASE + 0x00001800 + \ + (i) * sizeof(struct nbl_shaping_net)) + +/* cir 1, bandwidth 1kB/s in protol environment */ +/* cir 1, bandwidth 1Mb/s */ +#define NBL_LR_LEONIS_SYS_CLK 15000.0 /* 0105tag Khz */ +#define NBL_LR_LEONIS_NET_SHAPING_CYCLE_MAX 25 +#define NBL_LR_LEONIS_NET_SHAPING_DPETH 600 +#define NBL_LR_LEONIS_NET_BUCKET_DEPTH 9600 + +#define NBL_SHAPING_DPORT_25G_RATE 0x61A8 +#define NBL_SHAPING_DPORT_HALF_25G_RATE 0x30D4 + +#define NBL_SHAPING_DPORT_100G_RATE 0x1A400 +#define NBL_SHAPING_DPORT_HALF_100G_RATE 0xD200 + +#define NBL_UCAR_MAX_BUCKET_DEPTH 524287 + +#define NBL_DSTORE_DROP_XOFF_TH 0xC8 +#define NBL_DSTORE_DROP_XON_TH 0x64 + +#define NBL_DSTORE_DROP_XOFF_TH_100G 0x1F4 +#define NBL_DSTORE_DROP_XON_TH_100G 0x12C + +#define NBL_DSTORE_DROP_XOFF_TH_BOND_MAIN 0x180 +#define NBL_DSTORE_DROP_XON_TH_BOND_MAIN 0x180 + +#define NBL_DSTORE_DROP_XOFF_TH_BOND_OTHER 0x64 +#define NBL_DSTORE_DROP_XON_TH_BOND_OTHER 0x64 + +#define NBL_DSTORE_DROP_XOFF_TH_100G_BOND_MAIN 0x2D5 +#define NBL_DSTORE_DROP_XON_TH_100G_BOND_MAIN 0x2BC + +#define NBL_DSTORE_DROP_XOFF_TH_100G_BOND_OTHER 0x145 +#define NBL_DSTORE_DROP_XON_TH_100G_BOND_OTHER 0x12C + +#define NBL_DSTORE_DISC_BP_TH (NBL_DP_DSTORE_BASE + 0x00000630) + +struct dstore_disc_bp_th { + u32 xoff_th:10; + u32 rsv1:6; + u32 xon_th:10; + u32 rsv:5; + u32 en:1; +}; + +/* DSCH dsch_vn_sha2net_map_tbl */ +struct dsch_vn_sha2net_map_tbl { + u32 vld:1; + u32 reserve:31; +}; + +/* DSCH dsch_vn_net2sha_map_tbl */ +struct dsch_vn_net2sha_map_tbl { + u32 vld:1; + u32 reserve:31; +}; + +struct dsch_psha_en { + u32 en:4; + u32 rsv:28; +}; + +/* SHAPING shaping_net */ +struct nbl_shaping_net { + u32 valid:1; + u32 depth:19; + u32 cir:19; + u32 pir:19; + u32 cbs:21; + u32 pbs:21; + u32 rsv:28; +}; + +struct nbl_shaping_dport { + u32 valid:1; + u32 depth:19; + u32 cir:19; + u32 pir:19; + u32 cbs:21; + u32 pbs:21; + u32 rsv:28; +}; + +struct nbl_shaping_dvn_dport { + u32 valid:1; + u32 depth:19; + u32 cir:19; + u32 pir:19; + u32 cbs:21; + u32 pbs:21; + u32 rsv:28; +}; + +/* ---------- DSCH ---------- */ +/* DSCH vn_host_qid_max */ +#define NBL_DSCH_NOTIFY_BITMAP_ARR(i) \ + (NBL_DP_DSCH_BASE + 0x00003000 + (i) * BYTES_PER_DWORD) +#define NBL_DSCH_FLY_BITMAP_ARR(i) \ + (NBL_DP_DSCH_BASE + 0x00004000 + (i) * BYTES_PER_DWORD) +#define NBL_DSCH_PORT_MAP_REG_ARR(i) \ + (NBL_DP_DSCH_BASE + 0x00005000 + (i) * sizeof(struct nbl_port_map)) +/* DSCH dsch_vn_q2tc_cfg_tbl */ +#define NBL_DSCH_VN_Q2TC_CFG_TABLE_REG_ARR(i) \ + (NBL_DP_DSCH_BASE + 0x00010000 + \ + (i) * sizeof(struct dsch_vn_q2tc_cfg_tbl)) +/* DSCH dsch_vn_n2g_cfg_tbl */ +#define NBL_DSCH_VN_N2G_CFG_TABLE_REG_ARR(i) \ + (NBL_DP_DSCH_BASE + 0x00060000 + \ + (i) * sizeof(struct dsch_vn_n2g_cfg_tbl)) +/* DSCH dsch_vn_g2p_cfg_tbl */ +#define NBL_DSCH_VN_G2P_CFG_TABLE_REG_ARR(i) \ + (NBL_DP_DSCH_BASE + 0x00064000 + \ + (i) * sizeof(struct dsch_vn_g2p_cfg_tbl)) +/* DSCH dsch_vn_sha2net_map_tbl */ +#define NBL_DSCH_VN_SHA2NET_MAP_TABLE_REG_ARR(i) \ + (NBL_DP_DSCH_BASE + 0x00070000 + \ + (i) * sizeof(struct dsch_vn_sha2net_map_tbl)) +/* DSCH dsch_vn_net2sha_map_tbl */ +#define NBL_DSCH_VN_NET2SHA_MAP_TABLE_REG_ARR(i) \ + (NBL_DP_DSCH_BASE + 0x00074000 + \ + (i) * sizeof(struct dsch_vn_net2sha_map_tbl)) +/* DSCH dsch_vn_tc_q_list_tbl */ +#define NBL_DSCH_VN_TC_Q_LIST_TABLE_REG_ARR(i) \ + (NBL_DP_DSCH_BASE + 0x00040000 + \ + (i) * sizeof(struct dsch_vn_tc_q_list_tbl)) +/* DSCH dsch maxqid */ +#define NBL_DSCH_HOST_QID_MAX (NBL_DP_DSCH_BASE + 0x00000118) +#define NBL_DSCH_VN_QUANTA_ADDR (NBL_DP_DSCH_BASE + 0x00000134) +#define NBL_DSCH_INT_STATUS (NBL_DP_DSCH_BASE + 0x00000000) +#define NBL_DSCH_RDMA_OTHER_ABN (NBL_DP_DSCH_BASE + 0x00000080) +#define NBL_DSCH_RDMA_OTHER_ABN_BIT (0x4000) +#define NBL_DSCH_RDMA_DPQM_DB_LOST (2) + +#define NBL_MAX_QUEUE_ID (0x7ff) +#define NBL_HOST_QUANTA (0x8000) +#define NBL_ECPU_QUANTA (0x1000) + +/* DSCH dsch_vn_q2tc_cfg_tbl */ +struct dsch_vn_q2tc_cfg_tbl { + u32 tcid:13; + u32 rsv:18; + u32 vld:1; +}; + +/* DSCH dsch_vn_n2g_cfg_tbl */ +struct dsch_vn_n2g_cfg_tbl { + u32 grpid:8; + u32 rsv:23; + u32 vld:1; +}; + +/* DSCH dsch_vn_tc_qlist_tbl */ +struct dsch_vn_tc_q_list_tbl { + u32 nxt:11; + u32 reserve:18; + u32 regi:1; + u32 fly:1; + u32 vld:1; +}; + +/* DSCH dsch_vn_g2p_cfg_tbl */ +struct dsch_vn_g2p_cfg_tbl { + u32 port:3; + u32 rsv:28; + u32 vld:1; +}; + +struct dsch_vn_quanta { + u32 h_qua:16; + u32 e_qua:16; +}; + +/* ---------- DVN ---------- */ +/* DVN dvn_queue_table */ +#define NBL_DVN_QUEUE_TABLE_ARR(i) \ + (NBL_DP_DVN_BASE + 0x00020000 + (i) * sizeof(struct dvn_queue_table)) +#define NBL_DVN_QUEUE_CXT_TABLE_ARR(i) \ + (NBL_DP_DVN_BASE + 0x00030000 + (i) * sizeof(struct dvn_queue_context)) +/* DVN dvn_queue_reset */ +#define NBL_DVN_QUEUE_RESET_REG (NBL_DP_DVN_BASE + 0x00000400) +/* DVN dvn_queue_reset_done */ +#define NBL_DVN_QUEUE_RESET_DONE_REG (NBL_DP_DVN_BASE + 0x00000404) +#define NBL_DVN_ECPU_QUEUE_NUM (NBL_DP_DVN_BASE + 0x0000041C) +#define NBL_DVN_DESCREQ_NUM_CFG (NBL_DP_DVN_BASE + 0x00000430) +#define NBL_DVN_DESC_WR_MERGE_TIMEOUT (NBL_DP_DVN_BASE + 0x00000480) +#define NBL_DVN_DIF_REQ_RD_RO_FLAG (NBL_DP_DVN_BASE + 0x0000045C) +#define NBL_DVN_INT_STATUS (NBL_DP_DVN_BASE + 0x00000000) +#define NBL_DVN_DESC_DIF_ERR_CNT (NBL_DP_DVN_BASE + 0x0000003C) +#define NBL_DVN_DESC_DIF_ERR_INFO (NBL_DP_DVN_BASE + 0x00000038) +#define NBL_DVN_PKT_DIF_ERR_INFO (NBL_DP_DVN_BASE + 0x00000030) +#define NBL_DVN_PKT_DIF_ERR_CNT (NBL_DP_DVN_BASE + 0x00000034) +#define NBL_DVN_ERR_QUEUE_ID_GET (NBL_DP_DVN_BASE + 0x0000040C) +#define NBL_DVN_BACK_PRESSURE_MASK (NBL_DP_DVN_BASE + 0x00000464) +#define NBL_DVN_DESCRD_L2_UNAVAIL_CNT (NBL_DP_DVN_BASE + 0x00000A1C) +#define NBL_DVN_DESCRD_L2_NOAVAIL_CNT (NBL_DP_DVN_BASE + 0x00000A20) + +#define DEFAULT_DVN_DESCREQ_NUMCFG (0x00080014) +#define DEFAULT_DVN_100G_DESCREQ_NUMCFG (0x00080020) + +#define NBL_DVN_INT_PKT_DIF_ERR (4) +#define DEFAULT_DVN_DESC_WR_MERGE_TIMEOUT_MAX (0x3FF) + +#define NBL_DVN_INT_DESC_DIF_ERR (5) + +struct nbl_dvn_descreq_num_cfg { + u32 avring_cfg_num:1; /* spilit ring descreq_num 0:8,1:16 */ + u32 rsv0:3; + /* packet ring descreq_num 0:8,1:12,2:16;3:20,4:24,5:26;6:32,7:32 */ + u32 packed_l1_num:3; + u32 rsv1:25; +}; + +struct nbl_dvn_desc_wr_merge_timeout { + u32 cfg_cycle:10; + u32 rsv:22; +}; + +struct nbl_dvn_dif_req_rd_ro_flag { + u32 rd_desc_ro_en:1; + u32 rd_data_ro_en:1; + u32 rd_avring_ro_en:1; + u32 rsv:29; +}; + +/* DVN dvn_queue_table */ +struct dvn_queue_table { + u64 dvn_used_baddr; + u64 dvn_avail_baddr; + u64 dvn_queue_baddr; + u32 dvn_queue_size:4; + u32 dvn_queue_type:1; + u32 dvn_queue_en:1; + u32 dvn_extend_header_en:1; + u32 dvn_interleave_seg_disable:1; + u32 dvn_seg_disable:1; + u32 rsv0:23; + u32 rsv1:32; +}; + +/* DVN dvn_queue_context */ +struct dvn_queue_context { + u32 dvn_descrd_num:3; + u32 dvn_firstdescid:16; + u32 dvn_firstdesc:16; + u32 dvn_indirect_len:6; + u64 dvn_indirect_addr:64; + u32 dvn_indirect_next:5; + u32 dvn_l1_ring_read:16; + u32 dvn_avail_ring_read:16; + u32 dvn_ring_wrap_counter:1; + u32 dvn_lso_id:10; + u32 dvn_avail_ring_idx:16; + u32 dvn_used_ring_idx:16; + u32 dvn_indirect_left:1; + u32 dvn_desc_left:1; + u32 dvn_lso_flag:1; + u32 dvn_descrd_disable:1; + u32 dvn_queue_err:1; + u32 dvn_lso_drop:1; + u32 dvn_protected_bit:1; + u64 reserve; +}; + +/* DVN dvn_queue_reset */ +struct nbl_dvn_queue_reset { + u32 dvn_queue_index:11; + u32 vld:1; + u32 rsv:20; +}; + +/* DVN dvn_queue_reset_done */ +struct nbl_dvn_queue_reset_done { + u32 flag:1; + u32 rsv:31; +}; + +/* ---------- UVN ---------- */ +/* UVN uvn_queue_table */ +#define NBL_UVN_QUEUE_TABLE_ARR(i) \ + (NBL_DP_UVN_BASE + 0x00010000 + (i) * sizeof(struct uvn_queue_table)) +/* UVN uvn_queue_cxt */ +#define NBL_UVN_QUEUE_CXT_TABLE_ARR(i) \ + (NBL_DP_UVN_BASE + 0x00020000 + (i) * sizeof(struct uvn_queue_cxt)) +/* UVN uvn_desc_cxt */ +#define NBL_UVN_DESC_CXT_TABLE_ARR(i) \ + (NBL_DP_UVN_BASE + 0x00028000 + (i) * sizeof(struct uvn_desc_cxt)) +/* UVN uvn_queue_reset */ +#define NBL_UVN_QUEUE_RESET_REG (NBL_DP_UVN_BASE + 0x00000200) +/* UVN uvn_queue_reset_done */ +#define NBL_UVN_QUEUE_RESET_DONE_REG (NBL_DP_UVN_BASE + 0x00000408) +#define NBL_UVN_STATIS_PKT_DROP(i) \ + (NBL_DP_UVN_BASE + 0x00038000 + (i) * sizeof(u32)) +#define NBL_UVN_INT_STATUS (NBL_DP_UVN_BASE + 0x00000000) +#define NBL_UVN_QUEUE_ERR_INFO (NBL_DP_UVN_BASE + 0x00000034) +#define NBL_UVN_QUEUE_ERR_CNT (NBL_DP_UVN_BASE + 0x00000038) +#define NBL_UVN_DESC_RD_WAIT (NBL_DP_UVN_BASE + 0x0000020C) +#define NBL_UVN_QUEUE_ERR_MASK (NBL_DP_UVN_BASE + 0x00000224) +#define NBL_UVN_ECPU_QUEUE_NUM (NBL_DP_UVN_BASE + 0x0000023C) +#define NBL_UVN_DESC_WR_TIMEOUT (NBL_DP_UVN_BASE + 0x00000214) +#define NBL_UVN_DIF_DELAY_REQ (NBL_DP_UVN_BASE + 0x000010D0) +#define NBL_UVN_DIF_DELAY_TIME (NBL_DP_UVN_BASE + 0x000010D4) +#define NBL_UVN_DIF_DELAY_MAX (NBL_DP_UVN_BASE + 0x000010D8) +#define NBL_UVN_DESC_PRE_DESC_REQ_NULL (NBL_DP_UVN_BASE + 0x000012C8) +#define NBL_UVN_DESC_PRE_DESC_REQ_LACK (NBL_DP_UVN_BASE + 0x000012CC) +#define NBL_UVN_DESC_RD_ENTRY (NBL_DP_UVN_BASE + 0x000012D0) +#define NBL_UVN_DESC_RD_DROP_DESC_LACK (NBL_DP_UVN_BASE + 0x000012E0) +#define NBL_UVN_DIF_REQ_RO_FLAG (NBL_DP_UVN_BASE + 0x00000250) +#define NBL_UVN_DESC_PREFETCH_INIT (NBL_DP_UVN_BASE + 0x00000204) +#define NBL_UVN_DESC_WR_TIMEOUT_4US (0x960) +#define NBL_UVN_DESC_PREFETCH_NUM (4) + +#define NBL_UVN_INT_QUEUE_ERR (5) + +struct uvn_dif_req_ro_flag { + u32 avail_rd:1; + u32 desc_rd:1; + u32 pkt_wr:1; + u32 desc_wr:1; + u32 rsv:28; +}; + +/* UVN uvn_queue_table */ +struct uvn_queue_table { + u64 used_baddr; + u64 avail_baddr; + u64 queue_baddr; + u32 queue_size_mask_pow:4; + u32 queue_type:1; + u32 queue_enable:1; + u32 extend_header_en:1; + u32 guest_csum_en:1; + u32 half_offload_en:1; + u32 rsv0:23; + u32 rsv1:32; +}; + +/* uvn uvn_queue_cxt */ +struct uvn_queue_cxt { + u32 queue_head:16; + u32 wrap_count:1; + u32 queue_err:1; + u32 prefetch_null_cnt:2; + u32 ntf_finish:1; + u32 spnd_flag:1; + u32 reserve0:10; + u32 avail_idx:16; + u32 avail_idx_spnd_flag:1; + u32 reserve1:15; + u32 reserve2[2]; +}; + +/* uvn uvn_queue_reset */ +struct nbl_uvn_queue_reset { + u32 index:11; + u32 rsv0:5; + u32 vld:1; + u32 rsv1:15; +}; + +/* uvn uvn_queue_reset_done */ +struct nbl_uvn_queue_reset_done { + u32 flag:1; + u32 rsv:31; +}; + +/* uvn uvn_desc_cxt */ +struct uvn_desc_cxt { + u32 cache_head:9; + u32 reserve0:7; + u32 cache_tail:9; + u32 reserve1:7; + u32 cache_pref_num_prev:9; + u32 reserve2:7; + u32 cache_pref_num_post:9; + u32 reserve3:7; + u32 cache_head_byte:30; + u32 reserve4:2; + u32 cache_tail_byte:30; + u32 reserve5:2; +}; + +struct uvn_desc_wr_timeout { + u32 num:15; + u32 mask:1; + u32 rsv:16; +}; + +struct uvn_queue_err_mask { + u32 rsv0:1; + u32 buffer_len_err:1; + u32 next_err:1; + u32 indirect_err:1; + u32 split_err:1; + u32 dif_err:1; + u32 rsv1:26; +}; + +struct uvn_desc_prefetch_init { + u32 num:8; + u32 rsv1:8; + u32 sel:1; + u32 rsv:15; +}; + +/* -------- USTORE -------- */ +#define NBL_USTORE_PKT_LEN_ADDR (NBL_DP_USTORE_BASE + 0x00000108) +#define NBL_USTORE_PORT_FC_TH_REG_ARR(port_id) \ + (NBL_DP_USTORE_BASE + 0x00000134 + \ + (port_id) * sizeof(struct nbl_ustore_port_fc_th)) +#define NBL_USTORE_COS_FC_TH_REG_ARR(cos_id) \ + (NBL_DP_USTORE_BASE + 0x00000200 + \ + (cos_id) * sizeof(struct nbl_ustore_cos_fc_th)) +#define NBL_USTORE_PORT_DROP_TH_REG_ARR(port_id) \ + (NBL_DP_USTORE_BASE + 0x00000150 + \ + (port_id) * sizeof(struct nbl_ustore_port_drop_th)) +#define NBL_USTORE_BUF_TOTAL_DROP_PKT (NBL_DP_USTORE_BASE + 0x000010A8) +#define NBL_USTORE_BUF_TOTAL_TRUN_PKT (NBL_DP_USTORE_BASE + 0x000010AC) +#define NBL_USTORE_BUF_PORT_DROP_PKT(eth_id) \ + (NBL_DP_USTORE_BASE + 0x00002500 + (eth_id) * sizeof(u32)) +#define NBL_USTORE_BUF_PORT_TRUN_PKT(eth_id) \ + (NBL_DP_USTORE_BASE + 0x00002540 + (eth_id) * sizeof(u32)) + +#define NBL_USTORE_SIGNLE_ETH_DROP_TH 0xC80 +#define NBL_USTORE_DUAL_ETH_DROP_TH 0x640 +#define NBL_USTORE_QUAD_ETH_DROP_TH 0x320 + +/* USTORE pkt_len */ +struct ustore_pkt_len { + u32 min:7; + u32 rsv:8; + u32 min_chk_en:1; + u32 max:14; + u32 rsv2:1; + u32 max_chk_len:1; +}; + +/* USTORE port_fc_th */ +struct nbl_ustore_port_fc_th { + u32 xoff_th:12; + u32 rsv1:4; + u32 xon_th:12; + u32 rsv2:2; + u32 fc_set:1; + u32 fc_en:1; +}; + +/* USTORE cos_fc_th */ +struct nbl_ustore_cos_fc_th { + u32 xoff_th:12; + u32 rsv1:4; + u32 xon_th:12; + u32 rsv2:2; + u32 fc_set:1; + u32 fc_en:1; +}; + +#define NBL_MAX_USTORE_COS_FC_TH (4080) + +/* USTORE port_drop_th */ +struct nbl_ustore_port_drop_th { + u32 disc_th:12; + u32 rsv:19; + u32 en:1; +}; + +/* ---------- IPRO ---------- */ +/* ipro module related macros */ +#define NBL_IPRO_MODULE (0xB04000) +/* ipro queue tbl */ +#define NBL_IPRO_QUEUE_TBL(i) \ + (NBL_IPRO_MODULE + 0x00004000 + (i) * sizeof(struct nbl_ipro_queue_tbl)) +#define NBL_IPRO_UP_SPORT_TABLE(i) \ + (NBL_IPRO_MODULE + 0x00007000 + \ + (i) * sizeof(struct nbl_ipro_upsport_tbl)) +#define NBL_IPRO_DN_SRC_PORT_TABLE(i) \ + (NBL_PPE_IPRO_BASE + 0x00008000 + \ + (i) * sizeof(struct nbl_ipro_dn_src_port_tbl)) + +/* IPRO dn_src_port_tbl */ +struct nbl_ipro_dn_src_port_tbl { + u32 entry_vld:1; + u32 mirror_en:1; + u32 mirror_pr:2; + u32 mirror_id:4; + u32 vlan_layer_num_1:2; + u32 hw_flow:1; + u32 mtu_sel:4; + u32 addr_check_en:1; + u32 smac_low:16; + u32 smac_high; + u32 dqueue:11; + u32 dqueue_en:1; + u32 dqueue_pri:2; + u32 set_dport_pri:2; + union nbl_action_data set_dport; + u32 set_dport_en:1; + u32 proc_done:1; + u32 not_used_1:6; + u32 rsv:24; +}; + +/* IPRO up sport tab */ +struct nbl_ipro_upsport_tbl { + u32 entry_vld:1; + u32 vlan_layer_num_0:2; + u32 vlan_layer_num_1:2; + u32 lag_vld:1; + u32 lag_id:2; + u32 hw_flow:1; + u32 mirror_en:1; + u32 mirror_pr:2; + u32 mirror_id:4; + u32 dqueue_pri:2; + u32 set_dport_pri:2; + u32 dqueue:11; + u32 dqueue_en:1; + union nbl_action_data set_dport; + u32 set_dport_en:1; + u32 proc_done:1; + u32 car_en:1; + u32 car_pr:2; + u32 car_id:10; + u32 rsv:1; +}; + +/* ---------- EPRO ---------- */ +#define NBL_EPRO_INT_STATUS (NBL_PPE_EPRO_BASE + 0x00000000) +#define NBL_EPRO_INT_MASK (NBL_PPE_EPRO_BASE + 0x00000004) +#define NBL_EPRO_RSS_KEY_REG (NBL_PPE_EPRO_BASE + 0x00000400) + +/* epro epro_ept table */ +#define NBL_EPRO_EPT_TABLE(i) \ + (NBL_PPE_EPRO_BASE + 0x00001800 + (i) * sizeof(struct nbl_epro_ept_tbl)) +/* epro epro_vpt table */ +#define NBL_EPRO_VPT_TABLE(i) \ + (NBL_PPE_EPRO_BASE + 0x00004000 + (i) * sizeof(struct nbl_epro_vpt_tbl)) +/* epro epro_rss_pt table */ +#define NBL_EPRO_RSS_PT_TABLE(i) \ + (NBL_PPE_EPRO_BASE + 0x00002000 + \ + (i) * sizeof(struct nbl_epro_rss_pt_tbl)) +/* epro epro_rss_ret table */ +#define NBL_EPRO_RSS_RET_TABLE(i) \ + (NBL_PPE_EPRO_BASE + 0x00008000 + \ + (i) * sizeof(struct nbl_epro_rss_ret_tbl)) +/* epro epro_sch_cos_map table */ +#define NBL_EPRO_SCH_COS_MAP_TABLE(i, j) \ + (NBL_PPE_EPRO_BASE + 0x00000640 + ((i) * 0x20) + \ + (j) * sizeof(struct nbl_epro_cos_map)) +/* epro epro_port_pri_mdf_en */ +#define NBL_EPRO_PORT_PRI_MDF_EN (NBL_PPE_EPRO_BASE + 0x000006E0) +/* epro epro_act_sel_en */ +#define NBL_EPRO_ACT_SEL_EN_REG (NBL_PPE_EPRO_BASE + 0x00000214) +/* epro epro_kgen_ft table */ +#define NBL_EPRO_KGEN_FT_TABLE(i) \ + (NBL_PPE_EPRO_BASE + 0x00001980 + \ + (i) * sizeof(struct nbl_epro_kgen_ft_tbl)) + +struct nbl_epro_rss_key { + u64 key0; + u64 key1; + u64 key2; + u64 key3; + u64 key4; +}; + +/* EPRO epro_rss_ret table */ +struct nbl_epro_rss_ret_tbl { + u32 dqueue0:11; + u32 vld0:1; + u32 rsv0:4; + u32 dqueue1:11; + u32 vld1:1; + u32 rsv1:4; +}; + +/* EPRO epro_rss_pt table */ +struct nbl_epro_rss_pt_tbl { + u32 entry_size:3; +#define NBL_EPRO_RSS_ENTRY_SIZE_16 (0) +#define NBL_EPRO_RSS_ENTRY_SIZE_32 (1) +#define NBL_EPRO_RSS_ENTRY_SIZE_64 (2) +#define NBL_EPRO_RSS_ENTRY_SIZE_128 (3) +#define NBL_EPRO_RSS_ENTRY_SIZE_256 (4) + u32 offset1:14; + u32 offset1_vld:1; + u32 offset0:14; + u32 offset0_vld:1; + u32 vld:1; + u32 rsv:30; +}; + +/*EPRO sch cos map*/ +struct nbl_epro_cos_map { + u32 pkt_cos:3; + u32 dscp:6; + u32 rsv:23; +}; + +/* EPRO epro_port_pri_mdf_en */ +struct nbl_epro_port_pri_mdf_en_cfg { + u32 eth0:1; + u32 eth1:1; + u32 eth2:1; + u32 eth3:1; + u32 loop:1; + u32 rsv:27; +}; + +/* EPRO action filter table */ +struct nbl_epro_action_filter_tbl { + u64 filter_mask; +}; + +/* EPRO epr_ept table */ +struct nbl_epro_ept_tbl { + u32 cvlan:16; + u32 svlan:16; + u32 fwd:1; +#define NBL_EPRO_FWD_TYPE_DROP (0) +#define NBL_EPRO_FWD_TYPE_NORMAL (1) + u32 mirror_en:1; + u32 mirror_id:4; + u32 pop_i_vlan:1; + u32 pop_o_vlan:1; + u32 push_i_vlan:1; + u32 push_o_vlan:1; + u32 replace_i_vlan:1; + u32 replace_o_vlan:1; + u32 lag_alg_sel:2; +#define NBL_EPRO_LAG_ALG_L2_HASH (0) +#define NBL_EPRO_LAG_ALG_L23_HASH (1) +#define NBL_EPRO_LAG_ALG_LINUX_L34_HASH (2) +#define NBL_EPRO_LAG_ALG_DPDK_L34_HASH (3) + u32 lag_port_btm:4; + u32 lag_l2_protect_en:1; + u32 pfc_sch_cos_default:3; + u32 pfc_mode:1; + u32 vld:1; + u32 rsv:8; +}; + +/* EPRO epro_vpt table */ +struct nbl_epro_vpt_tbl { + u32 cvlan:16; + u32 svlan:16; + u32 fwd:1; +#define NBL_EPRO_FWD_TYPE_DROP (0) +#define NBL_EPRO_FWD_TYPE_NORMAL (1) + u32 mirror_en:1; + u32 mirror_id:4; + u32 car_en:1; + u32 car_id:10; + u32 pop_i_vlan:1; + u32 pop_o_vlan:1; + u32 push_i_vlan:1; + u32 push_o_vlan:1; + u32 replace_i_vlan:1; + u32 replace_o_vlan:1; + u32 rss_alg_sel:1; +#define NBL_EPRO_RSS_ALG_TOEPLITZ_HASH (0) +#define NBL_EPRO_RSS_ALG_CRC32 (1) + u32 rss_key_type_ipv4:1; +#define NBL_EPRO_RSS_KEY_TYPE_IPV4_L3 (0) +#define NBL_EPRO_RSS_KEY_TYPE_IPV4_L4 (1) + u32 rss_key_type_ipv6:1; +#define NBL_EPRO_RSS_KEY_TYPE_IPV6_L3 (0) +#define NBL_EPRO_RSS_KEY_TYPE_IPV6_L4 (1) + u32 vld:1; + u32 rsv:5; +}; + +/* UPA upa_pri_sel_conf */ +#define NBL_UPA_PRI_SEL_CONF_TABLE(id) \ + (NBL_DP_UPA_BASE + 0x00000230 + \ + ((id) * sizeof(struct nbl_upa_pri_sel_conf))) +#define NBL_UPA_PRI_CONF_TABLE(id) \ + (NBL_DP_UPA_BASE + 0x00002000 + \ + ((id) * sizeof(struct nbl_upa_pri_conf))) + +/* UPA pri_sel_conf */ +struct nbl_upa_pri_sel_conf { + u32 pri_sel:5; + u32 pri_default:3; + u32 pri_disen:1; + u32 rsv:23; +}; + +/* UPA pri_conf_table */ +struct nbl_upa_pri_conf { + u32 pri0:4; + u32 pri1:4; + u32 pri2:4; + u32 pri3:4; + u32 pri4:4; + u32 pri5:4; + u32 pri6:4; + u32 pri7:4; +}; + +#define NBL_DQM_RXMAC_TX_PORT_BP_EN (NBL_DP_DQM_BASE + 0x00000660) +#define NBL_DQM_RXMAC_TX_COS_BP_EN (NBL_DP_DQM_BASE + 0x00000664) +#define NBL_DQM_RXMAC_RX_PORT_BP_EN (NBL_DP_DQM_BASE + 0x00000670) +#define NBL_DQM_RX_PORT_BP_EN (NBL_DP_DQM_BASE + 0x00000610) +#define NBL_DQM_RX_COS_BP_EN (NBL_DP_DQM_BASE + 0x00000614) + +/* DQM rxmac_tx_port_bp_en */ +struct nbl_dqm_rxmac_tx_port_bp_en_cfg { + u32 eth0:1; + u32 eth1:1; + u32 eth2:1; + u32 eth3:1; + u32 rsv:28; +}; + +/* DQM rxmac_tx_cos_bp_en */ +struct nbl_dqm_rxmac_tx_cos_bp_en_cfg { + u32 eth0:8; + u32 eth1:8; + u32 eth2:8; + u32 eth3:8; +}; + +#define NBL_UQM_QUE_TYPE (NBL_DP_UQM_BASE + 0x0000013c) +#define NBL_UQM_RX_COS_BP_EN (NBL_DP_UQM_BASE + 0x00000614) +#define NBL_UQM_TX_COS_BP_EN (NBL_DP_UQM_BASE + 0x00000604) + +#define NBL_UQM_DROP_PKT_CNT (NBL_DP_UQM_BASE + 0x000009C0) +#define NBL_UQM_DROP_PKT_SLICE_CNT (NBL_DP_UQM_BASE + 0x000009C4) +#define NBL_UQM_DROP_PKT_LEN_ADD_CNT (NBL_DP_UQM_BASE + 0x000009C8) +#define NBL_UQM_DROP_HEAD_PNTR_ADD_CNT (NBL_DP_UQM_BASE + 0x000009CC) +#define NBL_UQM_DROP_WEIGHT_ADD_CNT (NBL_DP_UQM_BASE + 0x000009D0) +#define NBL_UQM_PORT_DROP_PKT_CNT (NBL_DP_UQM_BASE + 0x000009D4) +#define NBL_UQM_PORT_DROP_PKT_SLICE_CNT (NBL_DP_UQM_BASE + 0x000009F4) +#define NBL_UQM_PORT_DROP_PKT_LEN_ADD_CNT (NBL_DP_UQM_BASE + 0x00000A14) +#define NBL_UQM_PORT_DROP_HEAD_PNTR_ADD_CNT (NBL_DP_UQM_BASE + 0x00000A34) +#define NBL_UQM_PORT_DROP_WEIGHT_ADD_CNT (NBL_DP_UQM_BASE + 0x00000A54) +#define NBL_UQM_FWD_DROP_CNT (NBL_DP_UQM_BASE + 0x00000A80) +#define NBL_UQM_DPORT_DROP_CNT (NBL_DP_UQM_BASE + 0x00000B74) + +#define NBL_UQM_PORT_DROP_DEPTH 6 +#define NBL_UQM_DPORT_DROP_DEPTH 16 + +struct nbl_uqm_que_type { + u32 bp_drop:1; + u32 rsv:31; +}; + +/* UQM rx_cos_bp_en */ +struct nbl_uqm_rx_cos_bp_en_cfg { + u32 vld_l; + u32 vld_h:16; +}; + +/* UQM rx_port_bp_en */ +struct nbl_uqm_rx_port_bp_en_cfg { + u32 l4s_h:1; + u32 l4s_e:1; + u32 rdma_h:1; + u32 rdma_e:1; + u32 emp:1; + u32 loopback:1; + u32 rsv:26; +}; + +/* UQM tx_cos_bp_en */ +struct nbl_uqm_tx_cos_bp_en_cfg { + u32 vld_l; + u32 vld_h:8; +}; + +#pragma pack() + +#define NBL_BYTES_IN_REG (4) +#define NBL_SHAPING_DPORT_ADDR (0x504700) +#define NBL_SHAPING_DPORT_DWLEN (4) +#define NBL_SHAPING_DPORT_REG(r) \ + (NBL_SHAPING_DPORT_ADDR + (NBL_SHAPING_DPORT_DWLEN * 4) * (r)) +#define NBL_SHAPING_DVN_DPORT_ADDR (0x504750) +#define NBL_SHAPING_DVN_DPORT_DWLEN (4) +#define NBL_SHAPING_DVN_DPORT_REG(r) \ + (NBL_SHAPING_DVN_DPORT_ADDR + (NBL_SHAPING_DVN_DPORT_DWLEN * 4) * (r)) +#define NBL_DSCH_PSHA_EN_ADDR (0x404314) +#define NBL_SHAPING_NET_ADDR (0x505800) +#define NBL_SHAPING_NET_DWLEN (4) +#define NBL_SHAPING_NET_REG(r) \ + (NBL_SHAPING_NET_ADDR + (NBL_SHAPING_NET_DWLEN * 4) * (r)) + +#define NBL_DPED_L4_CK_CMD_40_ADDR (0x75c338) +#define NBL_DPED_L4_CK_CMD_40_DEPTH (1) +#define NBL_DPED_L4_CK_CMD_40_WIDTH (32) +#define NBL_DPED_L4_CK_CMD_40_DWLEN (1) +union dped_l4_ck_cmd_40_u { + struct dped_l4_ck_cmd_40 { + u32 value:8; /* [7:0] Default:0x0 RW */ + u32 len_in_oft:7; /* [14:8] Default:0x0 RW */ + u32 len_phid:2; /* [16:15] Default:0x0 RW */ + u32 len_vld:1; /* [17] Default:0x0 RW */ + u32 data_vld:1; /* [18] Default:0x0 RW */ + u32 in_oft:7; /* [25:19] Default:0x8 RW */ + u32 phid:2; /* [27:26] Default:0x3 RW */ + u32 flag:1; /* [28] Default:0x0 RW */ + u32 mode:1; /* [29] Default:0x1 RW */ + u32 rsv:1; /* [30] Default:0x0 RO */ + u32 en:1; /* [31] Default:0x0 RW */ + } __packed info; + u32 data[NBL_DPED_L4_CK_CMD_40_DWLEN]; +} __packed; + +#define NBL_DSTORE_D_DPORT_FC_TH_ADDR (0x704600) +#define NBL_DSTORE_D_DPORT_FC_TH_DEPTH (5) +#define NBL_DSTORE_D_DPORT_FC_TH_WIDTH (32) +#define NBL_DSTORE_D_DPORT_FC_TH_DWLEN (1) +union dstore_d_dport_fc_th_u { + struct dstore_d_dport_fc_th { + u32 xoff_th:11; /* [10:0] Default:200 RW */ + u32 rsv1:5; /* [15:11] Default:0x0 RO */ + u32 xon_th:11; /* [26:16] Default:100 RW */ + u32 rsv:3; /* [29:27] Default:0x0 RO */ + u32 fc_set:1; /* [30:30] Default:0x0 RW */ + u32 fc_en:1; /* [31:31] Default:0x0 RW */ + } __packed info; + u32 data[NBL_DSTORE_D_DPORT_FC_TH_DWLEN]; +} __packed; +#define NBL_DSTORE_D_DPORT_FC_TH_REG(r) (NBL_DSTORE_D_DPORT_FC_TH_ADDR + \ + (NBL_DSTORE_D_DPORT_FC_TH_DWLEN * 4) * (r)) +#define NBL_DSTORE_PORT_DROP_TH_ADDR (0x704150) +#define NBL_DSTORE_PORT_DROP_TH_DEPTH (6) +#define NBL_DSTORE_PORT_DROP_TH_WIDTH (32) +#define NBL_DSTORE_PORT_DROP_TH_DWLEN (1) +union dstore_port_drop_th_u { + struct dstore_port_drop_th { + u32 disc_th:10; /* [9:0] Default:800 RW */ + u32 rsv:21; /* [30:10] Default:0x0 RO */ + u32 en:1; /* [31] Default:0x1 RW */ + } __packed info; + u32 data[NBL_DSTORE_PORT_DROP_TH_DWLEN]; +} __packed; +#define NBL_DSTORE_PORT_DROP_TH_REG(r) (NBL_DSTORE_PORT_DROP_TH_ADDR + \ + (NBL_DSTORE_PORT_DROP_TH_DWLEN * 4) * (r)) + +#define NBL_FW_BOARD_CONFIG 0x200 +#define NBL_FW_BOARD_DW3_OFFSET (NBL_FW_BOARD_CONFIG + 12) +#define NBL_FW_BOARD_DW6_OFFSET (NBL_FW_BOARD_CONFIG + 24) +union nbl_fw_board_cfg_dw3 { + struct board_cfg_dw3 { + u32 port_type:1; + u32 port_num:7; + u32 port_speed:2; + u32 gpio_type:3; + u32 p4_version:1; /* 0: low version; 1: high version */ + u32 rsv:18; + } __packed info; + u32 data; +}; + +union nbl_fw_board_cfg_dw6 { + struct board_cfg_dw6 { + u8 lane_bitmap; + u8 eth_bitmap; + u16 rsv; + } __packed info; + u32 data; +}; + +#define NBL_LEONIS_QUIRKS_OFFSET (0x00000140) +#define NBL_LEONIS_ILLEGAL_REG_VALUE (0xDEADBEEF) + #endif diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nb= l_hw_leonis_regs.c b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_l= eonis/nbl_hw_leonis_regs.c new file mode 100644 index 000000000000..8515733949ca --- /dev/null +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_le= onis_regs.c @@ -0,0 +1,2902 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 Nebula Matrix Limited. + * Author: + */ + +#include "nbl_hw_reg.h" +#include "nbl_hw_leonis.h" +#include "nbl_hw_leonis_regs.h" + +#define NBL_SEC_BLOCK_SIZE (0x100) +#define NBL_SEC000_SIZE (1) +#define NBL_SEC000_ADDR (0x114150) +#define NBL_SEC001_SIZE (1) +#define NBL_SEC001_ADDR (0x15c190) +#define NBL_SEC002_SIZE (1) +#define NBL_SEC002_ADDR (0x10417c) +#define NBL_SEC003_SIZE (1) +#define NBL_SEC003_ADDR (0x714154) +#define NBL_SEC004_SIZE (1) +#define NBL_SEC004_ADDR (0x75c190) +#define NBL_SEC005_SIZE (1) +#define NBL_SEC005_ADDR (0x70417c) +#define NBL_SEC006_SIZE (512) +#define NBL_SEC006_ADDR (0x8f000) +#define NBL_SEC006_REGI(i) (0x8f000 + NBL_BYTES_IN_REG * (i)) +#define NBL_SEC007_SIZE (256) +#define NBL_SEC007_ADDR (0x8f800) +#define NBL_SEC007_REGI(i) (0x8f800 + NBL_BYTES_IN_REG * (i)) +#define NBL_SEC008_SIZE (1024) +#define NBL_SEC008_ADDR (0x90000) +#define NBL_SEC008_REGI(i) (0x90000 + NBL_BYTES_IN_REG * (i)) +#define NBL_SEC009_SIZE (2048) +#define NBL_SEC009_ADDR (0x94000) +#define NBL_SEC009_REGI(i) (0x94000 + NBL_BYTES_IN_REG * (i)) +#define NBL_SEC010_SIZE (256) +#define NBL_SEC010_ADDR (0x96000) +#define NBL_SEC010_REGI(i) (0x96000 + NBL_BYTES_IN_REG * (i)) +#define NBL_SEC011_SIZE (1024) +#define NBL_SEC011_ADDR (0x91000) +#define NBL_SEC011_REGI(i) (0x91000 + NBL_BYTES_IN_REG * (i)) +#define NBL_SEC012_SIZE (128) +#define NBL_SEC012_ADDR (0x92000) +#define NBL_SEC012_REGI(i) (0x92000 + NBL_BYTES_IN_REG * (i)) +#define NBL_SEC013_SIZE (64) +#define NBL_SEC013_ADDR (0x92200) +#define NBL_SEC013_REGI(i) (0x92200 + NBL_BYTES_IN_REG * (i)) +#define NBL_SEC014_SIZE (64) +#define NBL_SEC014_ADDR (0x92300) +#define NBL_SEC014_REGI(i) (0x92300 + NBL_BYTES_IN_REG * (i)) +#define NBL_SEC015_SIZE (1) +#define NBL_SEC015_ADDR (0x8c214) +#define NBL_SEC016_SIZE (1) +#define NBL_SEC016_ADDR (0x8c220) +#define NBL_SEC017_SIZE (1) +#define NBL_SEC017_ADDR (0x8c224) +#define NBL_SEC018_SIZE (1) +#define NBL_SEC018_ADDR (0x8c228) +#define NBL_SEC019_SIZE (1) +#define NBL_SEC019_ADDR (0x8c22c) +#define NBL_SEC020_SIZE (1) +#define NBL_SEC020_ADDR (0x8c1f0) +#define NBL_SEC021_SIZE (1) +#define NBL_SEC021_ADDR (0x8c1f8) +#define NBL_SEC022_SIZE (256) +#define NBL_SEC022_ADDR (0x85f000) +#define NBL_SEC022_REGI(i) (0x85f000 + NBL_BYTES_IN_REG * (i)) +#define NBL_SEC023_SIZE (128) +#define NBL_SEC023_ADDR (0x85f800) +#define NBL_SEC023_REGI(i) (0x85f800 + NBL_BYTES_IN_REG * (i)) +#define NBL_SEC024_SIZE (512) +#define NBL_SEC024_ADDR (0x860000) +#define NBL_SEC024_REGI(i) (0x860000 + NBL_BYTES_IN_REG * (i)) +#define NBL_SEC025_SIZE (1024) +#define NBL_SEC025_ADDR (0x864000) +#define NBL_SEC025_REGI(i) (0x864000 + NBL_BYTES_IN_REG * (i)) +#define NBL_SEC026_SIZE (256) +#define NBL_SEC026_ADDR (0x866000) +#define NBL_SEC026_REGI(i) (0x866000 + NBL_BYTES_IN_REG * (i)) +#define NBL_SEC027_SIZE (512) +#define NBL_SEC027_ADDR (0x861000) +#define NBL_SEC027_REGI(i) (0x861000 + NBL_BYTES_IN_REG * (i)) +#define NBL_SEC028_SIZE (64) +#define NBL_SEC028_ADDR (0x862000) +#define NBL_SEC028_REGI(i) (0x862000 + NBL_BYTES_IN_REG * (i)) +#define NBL_SEC029_SIZE (32) +#define NBL_SEC029_ADDR (0x862200) +#define NBL_SEC029_REGI(i) (0x862200 + NBL_BYTES_IN_REG * (i)) +#define NBL_SEC030_SIZE (32) +#define NBL_SEC030_ADDR (0x862300) +#define NBL_SEC030_REGI(i) (0x862300 + NBL_BYTES_IN_REG * (i)) +#define NBL_SEC031_SIZE (1) +#define NBL_SEC031_ADDR (0x85c214) +#define NBL_SEC032_SIZE (1) +#define NBL_SEC032_ADDR (0x85c220) +#define NBL_SEC033_SIZE (1) +#define NBL_SEC033_ADDR (0x85c224) +#define NBL_SEC034_SIZE (1) +#define NBL_SEC034_ADDR (0x85c228) +#define NBL_SEC035_SIZE (1) +#define NBL_SEC035_ADDR (0x85c22c) +#define NBL_SEC036_SIZE (1) +#define NBL_SEC036_ADDR (0xb04200) +#define NBL_SEC037_SIZE (1) +#define NBL_SEC037_ADDR (0xb04230) +#define NBL_SEC038_SIZE (1) +#define NBL_SEC038_ADDR (0xb04234) +#define NBL_SEC039_SIZE (64) +#define NBL_SEC039_ADDR (0xb05800) +#define NBL_SEC039_REGI(i) (0xb05800 + NBL_BYTES_IN_REG * (i)) +#define NBL_SEC040_SIZE (32) +#define NBL_SEC040_ADDR (0xb05400) +#define NBL_SEC040_REGI(i) (0xb05400 + NBL_BYTES_IN_REG * (i)) +#define NBL_SEC041_SIZE (16) +#define NBL_SEC041_ADDR (0xb05500) +#define NBL_SEC041_REGI(i) (0xb05500 + NBL_BYTES_IN_REG * (i)) +#define NBL_SEC042_SIZE (1) +#define NBL_SEC042_ADDR (0xb14148) +#define NBL_SEC043_SIZE (1) +#define NBL_SEC043_ADDR (0xb14104) +#define NBL_SEC044_SIZE (1) +#define NBL_SEC044_ADDR (0xb1414c) +#define NBL_SEC045_SIZE (1) +#define NBL_SEC045_ADDR (0xb14150) +#define NBL_SEC046_SIZE (256) +#define NBL_SEC046_ADDR (0xb15000) +#define NBL_SEC046_REGI(i) (0xb15000 + NBL_BYTES_IN_REG * (i)) +#define NBL_SEC047_SIZE (32) +#define NBL_SEC047_ADDR (0xb15800) +#define NBL_SEC047_REGI(i) (0xb15800 + NBL_BYTES_IN_REG * (i)) +#define NBL_SEC048_SIZE (1) +#define NBL_SEC048_ADDR (0xb24148) +#define NBL_SEC049_SIZE (1) +#define NBL_SEC049_ADDR (0xb24104) +#define NBL_SEC050_SIZE (1) +#define NBL_SEC050_ADDR (0xb2414c) +#define NBL_SEC051_SIZE (1) +#define NBL_SEC051_ADDR (0xb24150) +#define NBL_SEC052_SIZE (256) +#define NBL_SEC052_ADDR (0xb25000) +#define NBL_SEC052_REGI(i) (0xb25000 + NBL_BYTES_IN_REG * (i)) +#define NBL_SEC053_SIZE (32) +#define NBL_SEC053_ADDR (0xb25800) +#define NBL_SEC053_REGI(i) (0xb25800 + NBL_BYTES_IN_REG * (i)) +#define NBL_SEC054_SIZE (1) +#define NBL_SEC054_ADDR (0xb34148) +#define NBL_SEC055_SIZE (1) +#define NBL_SEC055_ADDR (0xb34104) +#define NBL_SEC056_SIZE (1) +#define NBL_SEC056_ADDR (0xb3414c) +#define NBL_SEC057_SIZE (1) +#define NBL_SEC057_ADDR (0xb34150) +#define NBL_SEC058_SIZE (256) +#define NBL_SEC058_ADDR (0xb35000) +#define NBL_SEC058_REGI(i) (0xb35000 + NBL_BYTES_IN_REG * (i)) +#define NBL_SEC059_SIZE (32) +#define NBL_SEC059_ADDR (0xb35800) +#define NBL_SEC059_REGI(i) (0xb35800 + NBL_BYTES_IN_REG * (i)) +#define NBL_SEC060_SIZE (1) +#define NBL_SEC060_ADDR (0xe74630) +#define NBL_SEC061_SIZE (1) +#define NBL_SEC061_ADDR (0xe74634) +#define NBL_SEC062_SIZE (64) +#define NBL_SEC062_ADDR (0xe75000) +#define NBL_SEC062_REGI(i) (0xe75000 + NBL_BYTES_IN_REG * (i)) +#define NBL_SEC063_SIZE (32) +#define NBL_SEC063_ADDR (0xe75480) +#define NBL_SEC063_REGI(i) (0xe75480 + NBL_BYTES_IN_REG * (i)) +#define NBL_SEC064_SIZE (16) +#define NBL_SEC064_ADDR (0xe75980) +#define NBL_SEC064_REGI(i) (0xe75980 + NBL_BYTES_IN_REG * (i)) +#define NBL_SEC065_SIZE (32) +#define NBL_SEC065_ADDR (0x15f000) +#define NBL_SEC065_REGI(i) (0x15f000 + NBL_BYTES_IN_REG * (i)) +#define NBL_SEC066_SIZE (32) +#define NBL_SEC066_ADDR (0x75f000) +#define NBL_SEC066_REGI(i) (0x75f000 + NBL_BYTES_IN_REG * (i)) +#define NBL_SEC067_SIZE (1) +#define NBL_SEC067_ADDR (0xb64108) +#define NBL_SEC068_SIZE (1) +#define NBL_SEC068_ADDR (0xb6410c) +#define NBL_SEC069_SIZE (1) +#define NBL_SEC069_ADDR (0xb64140) +#define NBL_SEC070_SIZE (1) +#define NBL_SEC070_ADDR (0xb64144) +#define NBL_SEC071_SIZE (512) +#define NBL_SEC071_ADDR (0xb65000) +#define NBL_SEC071_REGI(i) (0xb65000 + NBL_BYTES_IN_REG * (i)) +#define NBL_SEC072_SIZE (32) +#define NBL_SEC072_ADDR (0xb65800) +#define NBL_SEC072_REGI(i) (0xb65800 + NBL_BYTES_IN_REG * (i)) +#define NBL_SEC073_SIZE (1) +#define NBL_SEC073_ADDR (0x8c210) +#define NBL_SEC074_SIZE (1) +#define NBL_SEC074_ADDR (0x85c210) +#define NBL_SEC075_SIZE (4) +#define NBL_SEC075_ADDR (0x8c1b0) +#define NBL_SEC075_REGI(i) (0x8c1b0 + NBL_BYTES_IN_REG * (i)) +#define NBL_SEC076_SIZE (4) +#define NBL_SEC076_ADDR (0x8c1c0) +#define NBL_SEC076_REGI(i) (0x8c1c0 + NBL_BYTES_IN_REG * (i)) +#define NBL_SEC077_SIZE (4) +#define NBL_SEC077_ADDR (0x85c1b0) +#define NBL_SEC077_REGI(i) (0x85c1b0 + NBL_BYTES_IN_REG * (i)) +#define NBL_SEC078_SIZE (1) +#define NBL_SEC078_ADDR (0x85c1ec) +#define NBL_SEC079_SIZE (1) +#define NBL_SEC079_ADDR (0x8c1ec) +#define NBL_SEC080_SIZE (1) +#define NBL_SEC080_ADDR (0xb04440) +#define NBL_SEC081_SIZE (1) +#define NBL_SEC081_ADDR (0xb04448) +#define NBL_SEC082_SIZE (1) +#define NBL_SEC082_ADDR (0xb14450) +#define NBL_SEC083_SIZE (1) +#define NBL_SEC083_ADDR (0xb24450) +#define NBL_SEC084_SIZE (1) +#define NBL_SEC084_ADDR (0xb34450) +#define NBL_SEC085_SIZE (1) +#define NBL_SEC085_ADDR (0xa04188) +#define NBL_SEC086_SIZE (1) +#define NBL_SEC086_ADDR (0xe74218) +#define NBL_SEC087_SIZE (1) +#define NBL_SEC087_ADDR (0xe7421c) +#define NBL_SEC088_SIZE (1) +#define NBL_SEC088_ADDR (0xe74220) +#define NBL_SEC089_SIZE (1) +#define NBL_SEC089_ADDR (0xe74224) +#define NBL_SEC090_SIZE (1) +#define NBL_SEC090_ADDR (0x75c22c) +#define NBL_SEC091_SIZE (1) +#define NBL_SEC091_ADDR (0x75c230) +#define NBL_SEC092_SIZE (1) +#define NBL_SEC092_ADDR (0x75c238) +#define NBL_SEC093_SIZE (1) +#define NBL_SEC093_ADDR (0x75c244) +#define NBL_SEC094_SIZE (1) +#define NBL_SEC094_ADDR (0x75c248) +#define NBL_SEC095_SIZE (1) +#define NBL_SEC095_ADDR (0x75c250) +#define NBL_SEC096_SIZE (1) +#define NBL_SEC096_ADDR (0x15c230) +#define NBL_SEC097_SIZE (1) +#define NBL_SEC097_ADDR (0x15c234) +#define NBL_SEC098_SIZE (1) +#define NBL_SEC098_ADDR (0x15c238) +#define NBL_SEC099_SIZE (1) +#define NBL_SEC099_ADDR (0x15c23c) +#define NBL_SEC100_SIZE (1) +#define NBL_SEC100_ADDR (0x15c244) +#define NBL_SEC101_SIZE (1) +#define NBL_SEC101_ADDR (0x15c248) +#define NBL_SEC102_SIZE (1) +#define NBL_SEC102_ADDR (0xb6432c) +#define NBL_SEC103_SIZE (1) +#define NBL_SEC103_ADDR (0xb64220) +#define NBL_SEC104_SIZE (1) +#define NBL_SEC104_ADDR (0xb44804) +#define NBL_SEC105_SIZE (1) +#define NBL_SEC105_ADDR (0xb44a00) +#define NBL_SEC106_SIZE (1) +#define NBL_SEC106_ADDR (0xe84210) +#define NBL_SEC107_SIZE (1) +#define NBL_SEC107_ADDR (0xe84214) +#define NBL_SEC108_SIZE (1) +#define NBL_SEC108_ADDR (0xe64228) +#define NBL_SEC109_SIZE (1) +#define NBL_SEC109_ADDR (0x65413c) +#define NBL_SEC110_SIZE (1) +#define NBL_SEC110_ADDR (0x984144) +#define NBL_SEC111_SIZE (1) +#define NBL_SEC111_ADDR (0x114130) +#define NBL_SEC112_SIZE (1) +#define NBL_SEC112_ADDR (0x714138) +#define NBL_SEC113_SIZE (1) +#define NBL_SEC113_ADDR (0x114134) +#define NBL_SEC114_SIZE (1) +#define NBL_SEC114_ADDR (0x71413c) +#define NBL_SEC115_SIZE (1) +#define NBL_SEC115_ADDR (0x90437c) +#define NBL_SEC116_SIZE (32) +#define NBL_SEC116_ADDR (0xb05000) +#define NBL_SEC116_REGI(i) (0xb05000 + NBL_BYTES_IN_REG * (i)) +#define NBL_SEC117_SIZE (1) +#define NBL_SEC117_ADDR (0xb043e0) +#define NBL_SEC118_SIZE (1) +#define NBL_SEC118_ADDR (0xb043f0) +#define NBL_SEC119_SIZE (5) +#define NBL_SEC119_ADDR (0x8c230) +#define NBL_SEC119_REGI(i) (0x8c230 + NBL_BYTES_IN_REG * (i)) +#define NBL_SEC120_SIZE (1) +#define NBL_SEC120_ADDR (0x8c1f4) +#define NBL_SEC121_SIZE (1) +#define NBL_SEC121_ADDR (0x2046c4) +#define NBL_SEC122_SIZE (1) +#define NBL_SEC122_ADDR (0x85c1f4) +#define NBL_SEC123_SIZE (1) +#define NBL_SEC123_ADDR (0x75c194) +#define NBL_SEC124_SIZE (256) +#define NBL_SEC124_ADDR (0xa05000) +#define NBL_SEC124_REGI(i) (0xa05000 + NBL_BYTES_IN_REG * (i)) +#define NBL_SEC125_SIZE (256) +#define NBL_SEC125_ADDR (0xa06000) +#define NBL_SEC125_REGI(i) (0xa06000 + NBL_BYTES_IN_REG * (i)) +#define NBL_SEC126_SIZE (256) +#define NBL_SEC126_ADDR (0xa07000) +#define NBL_SEC126_REGI(i) (0xa07000 + NBL_BYTES_IN_REG * (i)) +#define NBL_SEC127_SIZE (1) +#define NBL_SEC127_ADDR (0x75c204) +#define NBL_SEC128_SIZE (1) +#define NBL_SEC128_ADDR (0x15c204) +#define NBL_SEC129_SIZE (1) +#define NBL_SEC129_ADDR (0x75c208) +#define NBL_SEC130_SIZE (1) +#define NBL_SEC130_ADDR (0x15c208) +#define NBL_SEC131_SIZE (1) +#define NBL_SEC131_ADDR (0x75c20c) +#define NBL_SEC132_SIZE (1) +#define NBL_SEC132_ADDR (0x15c20c) +#define NBL_SEC133_SIZE (1) +#define NBL_SEC133_ADDR (0x75c210) +#define NBL_SEC134_SIZE (1) +#define NBL_SEC134_ADDR (0x15c210) +#define NBL_SEC135_SIZE (1) +#define NBL_SEC135_ADDR (0x75c214) +#define NBL_SEC136_SIZE (1) +#define NBL_SEC136_ADDR (0x15c214) +#define NBL_SEC137_SIZE (32) +#define NBL_SEC137_ADDR (0x15d000) +#define NBL_SEC137_REGI(i) (0x15d000 + NBL_BYTES_IN_REG * (i)) +#define NBL_SEC138_SIZE (32) +#define NBL_SEC138_ADDR (0x75d000) +#define NBL_SEC138_REGI(i) (0x75d000 + NBL_BYTES_IN_REG * (i)) +#define NBL_SEC139_SIZE (1) +#define NBL_SEC139_ADDR (0x75c310) +#define NBL_SEC140_SIZE (1) +#define NBL_SEC140_ADDR (0x75c314) +#define NBL_SEC141_SIZE (1) +#define NBL_SEC141_ADDR (0x75c340) +#define NBL_SEC142_SIZE (1) +#define NBL_SEC142_ADDR (0x75c344) +#define NBL_SEC143_SIZE (1) +#define NBL_SEC143_ADDR (0x75c348) +#define NBL_SEC144_SIZE (1) +#define NBL_SEC144_ADDR (0x75c34c) +#define NBL_SEC145_SIZE (32) +#define NBL_SEC145_ADDR (0xb15800) +#define NBL_SEC145_REGI(i) (0xb15800 + NBL_BYTES_IN_REG * (i)) +#define NBL_SEC146_SIZE (32) +#define NBL_SEC146_ADDR (0xb25800) +#define NBL_SEC146_REGI(i) (0xb25800 + NBL_BYTES_IN_REG * (i)) +#define NBL_SEC147_SIZE (32) +#define NBL_SEC147_ADDR (0xb35800) +#define NBL_SEC147_REGI(i) (0xb35800 + NBL_BYTES_IN_REG * (i)) + +static u32 nbl_sec046_1p_data[] =3D { + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xa0000000, + 0x00077c2b, 0x005c0000, 0x00000000, 0x00008100, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x20000000, 0x00073029, 0x00480000, + 0x00000000, 0x00008100, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x20000000, 0x00073029, 0x00480000, 0x70000000, 0x00000020, + 0x24140000, 0x00000020, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xa0000000, + 0x00000009, 0x00000000, 0x00000000, 0x00002100, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0xb0000000, 0x00000009, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000100, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x70000000, 0x00000000, 0x20140000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x70000000, 0x00000000, + 0x20140000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x38430000, 0x70000006, 0x00000020, 0x24140000, 0x00000020, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x98cb1180, 0x6e36d469, 0x9d8eb91c, 0x87e3ef47, 0xa2931288, 0x08405c5a, + 0x73865086, 0x00000080, 0x30140000, 0x00000080, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0xb0000000, 0x000b3849, 0x38430000, 0x00000006, 0x0000c100, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xb0000000, + 0x00133889, 0x08400000, 0x03865086, 0x4c016100, 0x00000014, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, +}; + +static u32 nbl_sec071_1p_data[] =3D { + 0x00000000, 0x00000000, 0x00113d00, 0x00000000, 0x00000000, 0x00000000, + 0xe7029b00, 0x00000000, 0x00000000, 0x43000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x51e00000, 0x00000c9c, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00293d00, 0x00000000, + 0x00000000, 0x00000000, 0x67089b00, 0x00000002, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x80000000, 0x00000000, 0xb1e00000, 0x0000189c, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00213d00, 0x00000000, 0x00000000, 0x00000000, 0xe7069b00, 0x00000001, + 0x00000000, 0x43000000, 0x014b0c70, 0x00000000, 0x00000000, 0x00000000, + 0x92600000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00213d00, 0x00000000, 0x00000000, 0x00000000, + 0xe7069b00, 0x00000001, 0x00000000, 0x43000000, 0x015b0c70, 0x00000000, + 0x00000000, 0x00000000, 0x92600000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00553d00, 0x00000000, + 0x00000000, 0x00000000, 0xe6d29a00, 0x000149c4, 0x00000000, 0x4b000000, + 0x00000004, 0x00000000, 0x80000000, 0x00022200, 0x62600000, 0x00000001, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00553d00, 0x00000000, 0x00000000, 0x00000000, 0xe6d2c000, 0x000149c4, + 0x00000000, 0x5b000000, 0x00000004, 0x00000000, 0x80000000, 0x00022200, + 0x62600000, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x006d3d00, 0x00000000, 0x00000000, 0x00000000, + 0x64d49200, 0x5e556945, 0xc666d89a, 0x4b0001a9, 0x00004c84, 0x00000000, + 0x80000000, 0x00022200, 0xc2600000, 0x00000001, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x006d3d00, 0x00000000, + 0x00000000, 0x00000000, 0x6ed4ba00, 0x5ef56bc5, 0xc666d8c0, 0x5b0001a9, + 0x00004dc4, 0x00000000, 0x80000000, 0x00022200, 0xc2600000, 0x00000001, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000002, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00700000, 0x00000000, 0x08028000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, +}; + +static u32 nbl_sec046_2p_data[] =3D { + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xa0000000, + 0x00077c2b, 0x005c0000, 0x00000000, 0x00008100, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x20000000, 0x00073029, 0x00480000, + 0x00000000, 0x00008100, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x20000000, 0x00073029, 0x00480000, 0x70000000, 0x00000020, + 0x04140000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xa0000000, + 0x00000009, 0x00000000, 0x00000000, 0x00002100, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0xb0000000, 0x00000009, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000100, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x70000000, 0x00000000, 0x00140000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x70000000, 0x00000000, + 0x00140000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x38430000, 0x70000006, 0x00000020, 0x04140000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x98cb1180, 0x6e36d469, 0x9d8eb91c, 0x87e3ef47, 0xa2931288, 0x08405c5a, + 0x73865086, 0x00000080, 0x10140000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0xb0000000, 0x000b3849, 0x38430000, 0x00000006, 0x0000c100, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xb0000000, + 0x00133889, 0x08400000, 0x03865086, 0x4c016100, 0x00000014, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, +}; + +static u32 nbl_sec071_2p_data[] =3D { + 0x00000000, 0x00000000, 0x00113d00, 0x00000000, 0x00000000, 0x00000000, + 0xe7029b00, 0x00000000, 0x00000000, 0x43000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x51e00000, 0x00000c9c, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00293d00, 0x00000000, + 0x00000000, 0x00000000, 0x67089b00, 0x00000002, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x80000000, 0x00000000, 0xb1e00000, 0x0000189c, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00213d00, 0x00000000, 0x00000000, 0x00000000, 0xe7069b00, 0x00000001, + 0x00000000, 0x43000000, 0x014b0c70, 0x00000000, 0x00000000, 0x00000000, + 0x92600000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00213d00, 0x00000000, 0x00000000, 0x00000000, + 0xe7069b00, 0x00000001, 0x00000000, 0x43000000, 0x015b0c70, 0x00000000, + 0x00000000, 0x00000000, 0x92600000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00553d00, 0x00000000, + 0x00000000, 0x00000000, 0xe6d29a00, 0x000149c4, 0x00000000, 0x4b000000, + 0x00000004, 0x00000000, 0x80000000, 0x00022200, 0x62600000, 0x00000001, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00553d00, 0x00000000, 0x00000000, 0x00000000, 0xe6d2c000, 0x000149c4, + 0x00000000, 0x5b000000, 0x00000004, 0x00000000, 0x80000000, 0x00022200, + 0x62600000, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x006d3d00, 0x00000000, 0x00000000, 0x00000000, + 0x64d49200, 0x5e556945, 0xc666d89a, 0x4b0001a9, 0x00004c84, 0x00000000, + 0x80000000, 0x00022200, 0xc2600000, 0x00000001, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x006d3d00, 0x00000000, + 0x00000000, 0x00000000, 0x6ed4ba00, 0x5ef56bc5, 0xc666d8c0, 0x5b0001a9, + 0x00004dc4, 0x00000000, 0x80000000, 0x00022200, 0xc2600000, 0x00000001, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000002, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00700000, 0x00000000, 0x00028000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, +}; + +static u32 nbl_sec006_data[] =3D { + 0x81008100, 0x00000001, 0x88a88100, 0x00000001, 0x810088a8, 0x00000001, + 0x88a888a8, 0x00000001, 0x81000000, 0x00000001, 0x88a80000, 0x00000001, + 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x08004000, 0x00000001, 0x86dd6000, 0x00000001, + 0x81000000, 0x00000001, 0x88a80000, 0x00000001, 0x08060000, 0x00000001, + 0x80350000, 0x00000001, 0x88080000, 0x00000001, 0x88f70000, 0x00000001, + 0x88cc0000, 0x00000001, 0x88090000, 0x00000001, 0x89150000, 0x00000001, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x11006000, 0x00000001, + 0x06006000, 0x00000001, 0x02006000, 0x00000001, 0x3a006000, 0x00000001, + 0x2f006000, 0x00000001, 0x84006000, 0x00000001, 0x32006000, 0x00000001, + 0x2c006000, 0x00000001, 0x3c006000, 0x00000001, 0x2b006000, 0x00000001, + 0x00006000, 0x00000001, 0x00004000, 0x00000001, 0x00004000, 0x00000001, + 0x20004000, 0x00000001, 0x40004000, 0x00000001, 0x00000000, 0x00000001, + 0x11000000, 0x00000001, 0x06000000, 0x00000001, 0x02000000, 0x00000001, + 0x3a000000, 0x00000001, 0x2f000000, 0x00000001, 0x84000000, 0x00000001, + 0x32000000, 0x00000001, 0x2c000000, 0x00000001, 0x2b000000, 0x00000001, + 0x3c000000, 0x00000001, 0x3b000000, 0x00000001, 0x00000000, 0x00000001, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x11000000, 0x00000001, 0x06000000, 0x00000001, + 0x02000000, 0x00000001, 0x3a000000, 0x00000001, 0x2f000000, 0x00000001, + 0x84000000, 0x00000001, 0x32000000, 0x00000001, 0x00000000, 0x00000000, + 0x2c000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x2b000000, 0x00000001, 0x3c000000, 0x00000001, + 0x3b000000, 0x00000001, 0x00000000, 0x00000001, 0x06001072, 0x00000001, + 0x06000000, 0x00000001, 0x110017c1, 0x00000001, 0x110012b7, 0x00000001, + 0x110012b5, 0x00000001, 0x01000000, 0x00000001, 0x02000000, 0x00000001, + 0x3a000000, 0x00000001, 0x11000043, 0x00000001, 0x11000044, 0x00000001, + 0x11000222, 0x00000001, 0x11000000, 0x00000001, 0x2f006558, 0x00000001, + 0x32000000, 0x00000001, 0x84000000, 0x00000001, 0x00000000, 0x00000001, + 0x65582000, 0x00000001, 0x65583000, 0x00000001, 0x6558a000, 0x00000001, + 0x6558b000, 0x00000001, 0x65580000, 0x00000001, 0x12b50000, 0x00000001, + 0x02000102, 0x00000001, 0x00000000, 0x00000001, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x65580000, 0x00000001, 0x00000000, 0x00000001, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x81008100, 0x00000001, + 0x88a88100, 0x00000001, 0x810088a8, 0x00000001, 0x88a888a8, 0x00000001, + 0x81000000, 0x00000001, 0x88a80000, 0x00000001, 0x00000000, 0x00000001, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x08004000, 0x00000001, 0x86dd6000, 0x00000001, 0x81000000, 0x00000001, + 0x88a80000, 0x00000001, 0x08060000, 0x00000001, 0x80350000, 0x00000001, + 0x88080000, 0x00000001, 0x88f70000, 0x00000001, 0x88cc0000, 0x00000001, + 0x88090000, 0x00000001, 0x89150000, 0x00000001, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000001, 0x11006000, 0x00000001, 0x06006000, 0x00000001, + 0x02006000, 0x00000001, 0x3a006000, 0x00000001, 0x2f006000, 0x00000001, + 0x84006000, 0x00000001, 0x32006000, 0x00000001, 0x2c006000, 0x00000001, + 0x3c006000, 0x00000001, 0x2b006000, 0x00000001, 0x00006000, 0x00000001, + 0x00004000, 0x00000001, 0x00004000, 0x00000001, 0x20004000, 0x00000001, + 0x40004000, 0x00000001, 0x00000000, 0x00000001, 0x11000000, 0x00000001, + 0x06000000, 0x00000001, 0x02000000, 0x00000001, 0x3a000000, 0x00000001, + 0x2f000000, 0x00000001, 0x84000000, 0x00000001, 0x32000000, 0x00000001, + 0x2c000000, 0x00000001, 0x2b000000, 0x00000001, 0x3c000000, 0x00000001, + 0x3b000000, 0x00000001, 0x00000000, 0x00000001, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x11000000, 0x00000001, 0x06000000, 0x00000001, 0x02000000, 0x00000001, + 0x3a000000, 0x00000001, 0x2f000000, 0x00000001, 0x84000000, 0x00000001, + 0x32000000, 0x00000001, 0x00000000, 0x00000000, 0x2c000000, 0x00000001, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x2b000000, 0x00000001, 0x3c000000, 0x00000001, 0x3b000000, 0x00000001, + 0x00000000, 0x00000001, 0x06001072, 0x00000001, 0x06000000, 0x00000001, + 0x110012b7, 0x00000001, 0x01000000, 0x00000001, 0x02000000, 0x00000001, + 0x3a000000, 0x00000001, 0x32000000, 0x00000001, 0x84000000, 0x00000001, + 0x11000043, 0x00000001, 0x11000044, 0x00000001, 0x11000222, 0x00000001, + 0x11000000, 0x00000001, 0x2f006558, 0x00000001, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, +}; + +static u32 nbl_sec007_data[] =3D { + 0x10001000, 0x00001000, 0x10000000, 0x00000000, 0x1000ffff, 0x0000ffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x00000fff, 0x00000fff, + 0x1000ffff, 0x0000ffff, 0x0000ffff, 0x0000ffff, 0x0000ffff, 0x0000ffff, + 0x0000ffff, 0x0000ffff, 0x0000ffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0x00ff0fff, 0x00ff0fff, 0x00ff0fff, 0x00ff0fff, + 0x00ff0fff, 0x00ff0fff, 0x00ff0fff, 0x00ff0fff, 0x00ff0fff, 0x10ff0fff, + 0xffff0fff, 0x00000fff, 0x1fff0fff, 0x1fff0fff, 0x1fff0fff, 0xffffffff, + 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff, + 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x00ffffff, 0x00ffffff, + 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff, 0xffffffff, + 0x00ffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x00ffffff, 0x00ffffff, + 0x00ffffff, 0xffffffff, 0x00ff0000, 0x00ffffff, 0x00ff0000, 0x00ff0000, + 0x00ff0000, 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ff0000, 0x00ff0000, + 0x00ff0001, 0x00ffffff, 0x00ff0000, 0x00ffffff, 0x00ffffff, 0xffffffff, + 0x00000fff, 0x00000fff, 0x00000fff, 0x00000fff, 0x00000fff, 0x0000ffff, + 0xc0ff0000, 0xc0ffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0000ffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0x10001000, 0x00001000, 0x10000000, 0x00000000, + 0x1000ffff, 0x0000ffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0x00000fff, 0x00000fff, 0x1000ffff, 0x0000ffff, 0x0000ffff, 0x0000ffff, + 0x0000ffff, 0x0000ffff, 0x0000ffff, 0x0000ffff, 0x0000ffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x00ff0fff, 0x00ff0fff, + 0x00ff0fff, 0x00ff0fff, 0x00ff0fff, 0x00ff0fff, 0x00ff0fff, 0x00ff0fff, + 0x00ff0fff, 0x10ff0fff, 0xffff0fff, 0x00000fff, 0x1fff0fff, 0x1fff0fff, + 0x1fff0fff, 0xffffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff, + 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff, + 0x00ffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff, + 0x00ffffff, 0xffffffff, 0x00ffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0x00ffffff, 0x00ffffff, 0x00ffffff, 0xffffffff, 0x00ff0000, 0x00ffffff, + 0x00ff0000, 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff, + 0x00ff0000, 0x00ff0000, 0x00ff0001, 0x00ffffff, 0x00ff0000, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, +}; + +static u32 nbl_sec008_data[] =3D { + 0x00809190, 0x16009496, 0x00000100, 0x00000000, 0x00809190, 0x16009496, + 0x00000100, 0x00000000, 0x00809190, 0x16009496, 0x00000100, 0x00000000, + 0x00809190, 0x16009496, 0x00000100, 0x00000000, 0x00800090, 0x12009092, + 0x00000100, 0x00000000, 0x00800090, 0x12009092, 0x00000100, 0x00000000, + 0x00800000, 0x0e008c8e, 0x00000100, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08909581, 0x00008680, + 0x00000200, 0x00000000, 0x10900082, 0x28008680, 0x00000200, 0x00000000, + 0x809b0093, 0x00000000, 0x00000100, 0x00000000, 0x809b0093, 0x00000000, + 0x00000100, 0x00000000, 0x009b008f, 0x00000000, 0x00000100, 0x00000000, + 0x009b008f, 0x00000000, 0x00000100, 0x00000000, 0x009b008f, 0x00000000, + 0x00000100, 0x00000000, 0x009b008f, 0x00000000, 0x00000100, 0x00000000, + 0x009b008f, 0x00000000, 0x00000100, 0x00000000, 0x009b008f, 0x00000000, + 0x00000100, 0x00000000, 0x009b0000, 0x00000000, 0x00000100, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x009b0000, 0x00000000, + 0x00000100, 0x00000000, 0x00000000, 0x00000082, 0x00000500, 0x00000000, + 0x00000000, 0x00000082, 0x00000500, 0x00000000, 0x00000000, 0x00000082, + 0x00000500, 0x00000000, 0x00000000, 0x00000082, 0x00000500, 0x00000000, + 0x00000000, 0x00000082, 0x00000500, 0x00000000, 0x00000000, 0x00000082, + 0x00000500, 0x00000000, 0x00000000, 0x00000082, 0x00000500, 0x00000000, + 0x00ab0085, 0x08000000, 0x00000200, 0x00000000, 0x00ab0000, 0x00000000, + 0x00000200, 0x00000000, 0x00ab0000, 0x00000000, 0x00000200, 0x00000000, + 0x40000000, 0x01c180c2, 0x00000300, 0x00000000, 0x00000000, 0x00a089c2, + 0x000005f0, 0x00000000, 0x000b0085, 0x00a00000, 0x000002f0, 0x00000000, + 0x000b0085, 0x00a00000, 0x000002f0, 0x00000000, 0x00000000, 0x00a089c2, + 0x000005f0, 0x00000000, 0x000b0000, 0x00000000, 0x00000200, 0x00000000, + 0x00000000, 0x00000082, 0x00000500, 0x00000000, 0x00000000, 0x00000082, + 0x00000500, 0x00000000, 0x00000000, 0x00000082, 0x00000500, 0x00000000, + 0x00000000, 0x00000082, 0x00000500, 0x00000000, 0x00000000, 0x00000082, + 0x00000500, 0x00000000, 0x00000000, 0x00000082, 0x00000500, 0x00000000, + 0x00000000, 0x00000082, 0x00000500, 0x00000000, 0x00ab0085, 0x08000000, + 0x00000300, 0x00000000, 0x00ab0000, 0x00000000, 0x00000300, 0x00000000, + 0x00ab0000, 0x00000000, 0x00000300, 0x00000000, 0x00ab0000, 0x00000000, + 0x00000300, 0x00000000, 0x40000000, 0x01c180c2, 0x00000400, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000082, + 0x00000500, 0x00000000, 0x00000000, 0x00000082, 0x00000500, 0x00000000, + 0x00000000, 0x00000082, 0x00000500, 0x00000000, 0x00000000, 0x00000082, + 0x00000500, 0x00000000, 0x00000000, 0x00000082, 0x00000500, 0x00000000, + 0x00000000, 0x00000082, 0x00000500, 0x00000000, 0x00000000, 0x00000082, + 0x00000500, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00ab0085, 0x08000000, 0x00000400, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00ab0000, 0x00000000, + 0x00000400, 0x00000000, 0x00ab0000, 0x00000000, 0x00000400, 0x00000000, + 0x00ab0000, 0x00000000, 0x00000400, 0x00000000, 0x00ab0000, 0x00000000, + 0x00000400, 0x00000000, 0x01ab0083, 0x0ca00000, 0x0000050f, 0x00000000, + 0x01ab0083, 0x0ca00000, 0x0000050f, 0x00000000, 0x02a00084, 0x08008890, + 0x00000600, 0x00000000, 0x02ab848a, 0x08000000, 0x00000500, 0x00000000, + 0x02a00084, 0x10008200, 0x00000600, 0x00000000, 0x00ab8f8e, 0x04000000, + 0x00000500, 0x00000000, 0x00ab0000, 0x00000000, 0x00000500, 0x00000000, + 0x00ab8f8e, 0x04000000, 0x00000500, 0x00000000, 0x02ab848f, 0x08000000, + 0x00000500, 0x00000000, 0x02ab848f, 0x08000000, 0x00000500, 0x00000000, + 0x02ab848f, 0x08000000, 0x00000500, 0x00000000, 0x02ab0084, 0x08000000, + 0x00000500, 0x00000000, 0x00a00000, 0x04008280, 0x00000600, 0x00000000, + 0x00ab0000, 0x00000000, 0x00000500, 0x00000000, 0x04ab8e84, 0x0c000000, + 0x00000500, 0x00000000, 0x00ab0000, 0x00000000, 0x00000500, 0x00000000, + 0x00000000, 0x0400ccd0, 0x00000800, 0x00000000, 0x00000000, 0x0800ccd0, + 0x00000800, 0x00000000, 0x00000000, 0x0800ccd0, 0x00000800, 0x00000000, + 0x00000000, 0x0c00ccd0, 0x00000800, 0x00000000, 0x00000000, 0x0000ccd0, + 0x00000800, 0x00000000, 0x00000000, 0x0000ccd0, 0x00000800, 0x00000000, + 0x00000000, 0x10008200, 0x00000700, 0x00000000, 0x00000000, 0x08008200, + 0x00000700, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000ccd0, + 0x00000800, 0x00000000, 0x00000000, 0x0000ccd0, 0x00000800, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00808786, 0x16009496, 0x00000900, 0x00000000, + 0x00808786, 0x16009496, 0x00000900, 0x00000000, 0x00808786, 0x16009496, + 0x00000900, 0x00000000, 0x00808786, 0x16009496, 0x00000900, 0x00000000, + 0x00800086, 0x12009092, 0x00000900, 0x00000000, 0x00800086, 0x12009092, + 0x00000900, 0x00000000, 0x00800000, 0x0e008c8e, 0x00000900, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x08908192, 0x00008680, 0x00000a00, 0x00000000, 0x10908292, 0x28008680, + 0x00000a00, 0x00000000, 0x809b9392, 0x00000000, 0x00000900, 0x00000000, + 0x809b9392, 0x00000000, 0x00000900, 0x00000000, 0x009b8f92, 0x00000000, + 0x00000900, 0x00000000, 0x009b8f92, 0x00000000, 0x00000900, 0x00000000, + 0x009b8f92, 0x00000000, 0x00000900, 0x00000000, 0x009b8f92, 0x00000000, + 0x00000900, 0x00000000, 0x009b8f92, 0x00000000, 0x00000900, 0x00000000, + 0x009b8f92, 0x00000000, 0x00000900, 0x00000000, 0x009b0092, 0x00000000, + 0x00000900, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x009b0092, 0x00000000, 0x00000900, 0x00000000, 0x00000000, 0x00000082, + 0x00000d00, 0x00000000, 0x00000000, 0x00000082, 0x00000d00, 0x00000000, + 0x00000000, 0x00000082, 0x00000d00, 0x00000000, 0x00000000, 0x00000082, + 0x00000d00, 0x00000000, 0x00000000, 0x00000082, 0x00000d00, 0x00000000, + 0x00000000, 0x00000082, 0x00000d00, 0x00000000, 0x00000000, 0x00000082, + 0x00000d00, 0x00000000, 0x00ab0085, 0x08000000, 0x00000a00, 0x00000000, + 0x00ab0000, 0x00000000, 0x00000a00, 0x00000000, 0x00ab0000, 0x00000000, + 0x00000a00, 0x00000000, 0x40000000, 0x01c180c2, 0x00000b00, 0x00000000, + 0x00000000, 0x00a089c2, 0x00000df0, 0x00000000, 0x000b0085, 0x00a00000, + 0x00000af0, 0x00000000, 0x000b0085, 0x00a00000, 0x00000af0, 0x00000000, + 0x00000000, 0x00a089c2, 0x00000df0, 0x00000000, 0x000b0000, 0x00000000, + 0x00000a00, 0x00000000, 0x00000000, 0x00000082, 0x00000d00, 0x00000000, + 0x00000000, 0x00000082, 0x00000d00, 0x00000000, 0x00000000, 0x00000082, + 0x00000d00, 0x00000000, 0x00000000, 0x00000082, 0x00000d00, 0x00000000, + 0x00000000, 0x00000082, 0x00000d00, 0x00000000, 0x00000000, 0x00000082, + 0x00000d00, 0x00000000, 0x00000000, 0x00000082, 0x00000d00, 0x00000000, + 0x00ab0085, 0x08000000, 0x00000b00, 0x00000000, 0x00ab0000, 0x00000000, + 0x00000b00, 0x00000000, 0x00ab0000, 0x00000000, 0x00000b00, 0x00000000, + 0x00ab0000, 0x00000000, 0x00000b00, 0x00000000, 0x40000000, 0x01c180c2, + 0x00000c00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000082, 0x00000d00, 0x00000000, 0x00000000, 0x00000082, + 0x00000d00, 0x00000000, 0x00000000, 0x00000082, 0x00000d00, 0x00000000, + 0x00000000, 0x00000082, 0x00000d00, 0x00000000, 0x00000000, 0x00000082, + 0x00000d00, 0x00000000, 0x00000000, 0x00000082, 0x00000d00, 0x00000000, + 0x00000000, 0x00000082, 0x00000d00, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00ab0085, 0x08000000, 0x00000c00, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00ab0000, 0x00000000, 0x00000c00, 0x00000000, 0x00ab0000, 0x00000000, + 0x00000c00, 0x00000000, 0x00ab0000, 0x00000000, 0x00000c00, 0x00000000, + 0x00ab0000, 0x00000000, 0x00000c00, 0x00000000, 0x01ab0083, 0x0ca00000, + 0x00000d0f, 0x00000000, 0x01ab0083, 0x0ca00000, 0x00000d0f, 0x00000000, + 0x02ab8a84, 0x08000000, 0x00000d00, 0x00000000, 0x00ab8f8e, 0x04000000, + 0x00000d00, 0x00000000, 0x00ab0000, 0x00000000, 0x00000d00, 0x00000000, + 0x00ab8f8e, 0x04000000, 0x00000d00, 0x00000000, 0x00ab0000, 0x00000000, + 0x00000d00, 0x00000000, 0x04ab8e84, 0x0c000000, 0x00000d00, 0x00000000, + 0x02ab848f, 0x08000000, 0x00000d00, 0x00000000, 0x02ab848f, 0x08000000, + 0x00000d00, 0x00000000, 0x02ab848f, 0x08000000, 0x00000d00, 0x00000000, + 0x02ab0084, 0x08000000, 0x00000d00, 0x00000000, 0x00ab0000, 0x04000000, + 0x00000d00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00ab0000, 0x00000000, + 0x00000d00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, +}; + +static u32 nbl_sec009_data[] =3D { + 0x00000000, 0x00000060, 0x00000000, 0x00000090, 0x00000001, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000050, 0x00000000, 0x000000a0, + 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000a0, + 0x00000000, 0x00000050, 0x00000001, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000800, 0x00000000, 0x00000700, 0x00000001, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000900, 0x00000000, 0x00000600, + 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00008000, + 0x00000000, 0x00007000, 0x00000001, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00009000, 0x00000000, 0x00006000, 0x00000001, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x0000a000, 0x00000000, 0x00005000, + 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000c0000, + 0x00000000, 0x00030000, 0x00000001, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x000d0000, 0x00000000, 0x00020000, 0x00000001, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x000e0000, 0x00000000, 0x00010000, + 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000040, + 0x00000000, 0x000000b0, 0x00000001, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000070, 0x00000000, 0x00000080, 0x00000001, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000090, 0x00000000, 0x00000060, + 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000080, + 0x00000000, 0x00000070, 0x00000001, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000700, 0x00000000, 0x00000800, 0x00000001, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00007000, 0x00000000, 0x00008000, + 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000, + 0x00000000, 0x00070000, 0x00000001, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000c00, 0x00000000, 0x00000300, 0x00000001, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000d00, 0x00000000, 0x00000200, + 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00600000, + 0x00000000, 0x00900000, 0x00000001, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00d00000, 0x00000000, 0x00200000, 0x00000001, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00500000, 0x00000000, 0x00a00000, + 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00700000, + 0x00000000, 0x00800000, 0x00000001, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00e00000, 0x00000000, 0x00100000, 0x00000001, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00f00000, + 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00f00000, 0x00000001, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00100000, 0x00000000, 0x00e00000, 0x00000001, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00300000, 0x00000000, 0x00c00000, + 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000, + 0x00000000, 0x00700000, 0x00000001, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00900000, 0x00000000, 0x00600000, 0x00000001, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00a00000, 0x00000000, 0x00500000, + 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00b00000, + 0x00000000, 0x00400000, 0x00000001, 0x00000000, 0x00000000, 0x00000000, + 0x00000060, 0x00400000, 0x00000090, 0x00b00000, 0x00000001, 0x00000000, + 0x00000000, 0x00000000, 0x00000050, 0x00400000, 0x000000a0, 0x00b00000, + 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x000000a0, 0x00400000, + 0x00000050, 0x00b00000, 0x00000001, 0x00000000, 0x00000000, 0x00000000, + 0x00000800, 0x00400000, 0x00000700, 0x00b00000, 0x00000001, 0x00000000, + 0x00000000, 0x00000000, 0x00000900, 0x00400000, 0x00000600, 0x00b00000, + 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00008000, 0x00400000, + 0x00007000, 0x00b00000, 0x00000001, 0x00000000, 0x00000000, 0x00000000, + 0x00009000, 0x00400000, 0x00006000, 0x00b00000, 0x00000001, 0x00000000, + 0x00000000, 0x00000000, 0x0000a000, 0x00400000, 0x00005000, 0x00b00000, + 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x000c0000, 0x00400000, + 0x00030000, 0x00b00000, 0x00000001, 0x00000000, 0x00000000, 0x00000000, + 0x000d0000, 0x00400000, 0x00020000, 0x00b00000, 0x00000001, 0x00000000, + 0x00000000, 0x00000000, 0x000e0000, 0x00400000, 0x00010000, 0x00b00000, + 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000070, 0x00400000, + 0x00000080, 0x00b00000, 0x00000001, 0x00000000, 0x00000000, 0x00000000, + 0x00000700, 0x00400000, 0x00000800, 0x00b00000, 0x00000001, 0x00000000, + 0x00000000, 0x00000000, 0x00007000, 0x00400000, 0x00008000, 0x00b00000, + 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00080000, 0x00400000, + 0x00070000, 0x00b00000, 0x00000001, 0x00000000, 0x00000000, 0x00000000, + 0x00000c00, 0x00400000, 0x00000300, 0x00b00000, 0x00000001, 0x00000000, + 0x00000000, 0x00000000, 0x00000d00, 0x00400000, 0x00000200, 0x00b00000, + 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000040, 0x00400000, + 0x000000b0, 0x00b00000, 0x00000001, 0x00000000, 0x00000000, 0x00000000, + 0x00000090, 0x00400000, 0x00000060, 0x00b00000, 0x00000001, 0x00000000, + 0x00000000, 0x00000000, 0x00000080, 0x00400000, 0x00000070, 0x00b00000, + 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000060, 0x06000000, + 0x00000090, 0x09000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000, + 0x00000060, 0x07000000, 0x00000090, 0x08000000, 0x00000001, 0x00000000, + 0x00000000, 0x00000000, 0x00000050, 0x06000000, 0x000000a0, 0x09000000, + 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000050, 0x07000000, + 0x000000a0, 0x08000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000, + 0x000000a0, 0x06000000, 0x00000050, 0x09000000, 0x00000001, 0x00000000, + 0x00000000, 0x00000000, 0x000000a0, 0x07000000, 0x00000050, 0x08000000, + 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000800, 0x06000000, + 0x00000700, 0x09000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000, + 0x00000900, 0x06000000, 0x00000600, 0x09000000, 0x00000001, 0x00000000, + 0x00000000, 0x00000000, 0x00008000, 0x06000000, 0x00007000, 0x09000000, + 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00009000, 0x06000000, + 0x00006000, 0x09000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000, + 0x0000a000, 0x06000000, 0x00005000, 0x09000000, 0x00000001, 0x00000000, + 0x00000000, 0x00000000, 0x000c0000, 0x06000000, 0x00030000, 0x09000000, + 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x000d0000, 0x06000000, + 0x00020000, 0x09000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000, + 0x000e0000, 0x06000000, 0x00010000, 0x09000000, 0x00000001, 0x00000000, + 0x00000000, 0x00000000, 0x00000800, 0x07000000, 0x00000700, 0x08000000, + 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000900, 0x07000000, + 0x00000600, 0x08000000, 0x00000001, 0x00000000, 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0x00000040, 0x00000040, 0x00000040, 0x00000040, 0x00000040, + 0x00000040, 0x00000040, 0x00000045, 0x00000044, 0x00000044, 0x00000044, + 0x00000044, 0x00000044, 0x00000041, 0x00000042, 0x00000043, 0x00000046, + 0x00000046, 0x00000046, 0x00000046, 0x00000046, 0x00000046, 0x00000046, + 0x00000046, 0x00000046, 0x00000046, 0x00000046, 0x00000046, 0x00000046, + 0x00000046, 0x00000046, 0x00000046, 0x00000046, 0x00000046, 0x00000046, + 0x00000046, 0x00000046, 0x00000046, 0x0000004b, 0x0000004b, 0x0000004a, + 0x0000004a, 0x0000004a, 0x0000004a, 0x0000004a, 0x0000004a, 0x0000004a, + 0x0000004a, 0x0000004a, 0x0000004a, 0x00000047, 0x00000047, 0x00000048, + 0x00000048, 0x00000049, 0x00000049, 0x0000004c, 0x0000004c, 0x0000004c, + 0x0000004c, 0x0000004c, 0x0000004c, 0x0000004c, 0x0000004c, 0x0000004c, + 0x0000004c, 0x0000004c, 0x00000051, 0x00000050, 0x00000050, 0x00000050, + 0x00000050, 0x00000050, 0x0000004d, 0x0000004e, 0x0000004f, 0x00000052, + 0x00000053, 0x00000054, 0x00000054, 0x00000055, 0x00000056, 0x00000057, + 0x00000057, 0x00000057, 0x00000057, 0x00000058, 0x00000059, 0x00000059, + 0x0000005a, 0x0000005a, 0x0000005b, 0x0000005b, 0x0000005c, 0x0000005c, + 0x0000005c, 0x0000005c, 0x0000005d, 0x0000005d, 0x0000005e, 0x0000005e, + 0x0000005f, 0x0000005f, 0x0000005f, 0x0000005f, 0x0000005f, 0x0000005f, + 0x0000005f, 0x0000005f, 0x00000060, 0x00000060, 0x00000061, 0x00000061, + 0x00000061, 0x00000061, 0x00000062, 0x00000063, 0x00000064, 0x00000064, + 0x00000065, 0x00000066, 0x00000067, 0x00000067, 0x00000067, 0x00000067, + 0x00000068, 0x00000069, 0x00000069, 0x00000040, 0x00000040, 0x00000046, + 0x00000046, 0x00000046, 0x00000046, 0x0000004c, 0x0000004c, 0x0000000a, + 0x0000000a, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, +}; + +static u32 nbl_sec011_data[] =3D { + 0x0008002c, 0x00080234, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00080230, 0x00080332, 0x0008063c, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0008002c, 0x00080234, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080230, + 0x00080332, 0x00080738, 0x0008083c, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x0008002c, 0x00080234, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00080230, 0x00080332, 0x00080738, + 0x0008093a, 0x00080a3c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00080020, 0x00080228, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00080224, 0x00080326, 0x00080634, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080020, 0x00080228, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080224, + 0x00080326, 0x00080730, 0x00080834, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00080020, 0x00080228, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00080224, 0x00080326, 0x00080730, + 0x00080932, 0x00080a34, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00090200, 0x00090304, 0x00090408, 0x0009050c, + 0x00090610, 0x00090714, 0x00090818, 0x0009121c, 0x0009131e, 0x00000000, + 0x00000000, 0x00000000, 0x00090644, 0x00000000, 0x000d8045, 0x000d4145, + 0x0009030c, 0x0009041c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00090145, 0x00090944, 0x00000000, 0x00000000, 0x0009061c, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0009033a, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00090200, 0x00090304, 0x00090408, 0x0009050c, + 0x00090610, 0x00090714, 0x00090818, 0x0009121c, 0x0009131e, 0x00000000, + 0x00000000, 0x00000000, 0x0009063d, 0x00090740, 0x000d803f, 0x000d413f, + 0x0009030c, 0x0009041c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x0009013f, 0x00090840, 0x000dc93d, 0x000d093d, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000a0324, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000a003e, + 0x000a0140, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x000a0324, 0x000a0520, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x000a003e, 0x000a0140, 0x000a0842, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x000a0124, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000a0224, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x000a003c, 0x000a0037, 0x000ec139, 0x000e0139, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x000a0036, 0x000a0138, 0x000a0742, 0x00000000, 0x00000000, + 0x000a0d41, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000a0036, + 0x000a0138, 0x00000000, 0x00000000, 0x00000000, 0x000a0d3e, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x000a0036, 0x000a0138, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000a0037, 0x000a0139, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00080020, 0x00080228, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00080224, 0x00080326, 0x00080634, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00080020, 0x00080228, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00080224, 0x00080326, 0x00080730, 0x00080834, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080020, 0x00080228, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080224, + 0x00080326, 0x00080730, 0x00080932, 0x00080a34, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0009061c, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0009033a, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00090200, 0x00090304, 0x00090408, 0x0009050c, + 0x00090610, 0x00090714, 0x00090818, 0x0009121c, 0x0009131e, 0x00000000, + 0x00000000, 0x00000000, 0x0009063d, 0x00090740, 0x000d803f, 0x000d413f, + 0x0009030c, 0x0009041c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x0009013f, 0x00090840, 0x000dc93d, 0x000d093d, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x000a003c, 0x000a0037, 0x000ec139, 0x000e0139, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000a0036, + 0x000a0138, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x000a0036, 0x000a0138, 0x000a0742, + 0x00000000, 0x00000000, 0x000a0d41, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x000a0036, 0x000a0138, 0x00000000, 0x00000000, 0x00000000, + 0x000a0d3e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000a0037, 0x000a0139, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, +}; + +static u32 nbl_sec012_data[] =3D { + 0x00000006, 0x00000001, 0x00000004, 0x00000001, 0x00000006, 0x00000001, + 0x00000000, 0x00000001, 0x00000004, 0x00000001, 0x00000000, 0x00000001, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000010, 0x00000001, + 0x00000000, 0x00000001, 0x00000040, 0x00000001, 0x00000010, 0x00000001, + 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x06200000, 0x00000001, 0x00c00000, 0x00000001, + 0x02c00000, 0x00000001, 0x00200000, 0x00000001, 0x00400000, 0x00000001, + 0x00700000, 0x00000001, 0x00300000, 0x00000001, 0x00000000, 0x00000001, + 0x00a00000, 0x00000001, 0x00b00000, 0x00000001, 0x00e00000, 0x00000001, + 0x00500000, 0x00000001, 0x00800000, 0x00000001, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000004, 0x00000001, + 0x00000000, 0x00000001, 0x00000000, 0x00000001, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000040, 0x00000001, 0x00000010, 0x00000001, + 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00500000, 0x00000001, 0x00700000, 0x00000001, 0x00a00000, 0x00000001, + 0x00b00000, 0x00000001, 0x00200000, 0x00000001, 0x00000000, 0x00000001, + 0x00300000, 0x00000001, 0x00800000, 0x00000001, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, +}; + +static u32 nbl_sec013_data[] =3D { + 0xf7fffff0, 0xf7fffff1, 0xfffffff0, 0xf7fffff3, 0xfffffff1, 0xfffffff3, + 0xffffffff, 0xffffffff, 0xf7ffff0f, 0xf7ffff0f, 0xffffff0f, 0xffffff0f, + 0xffffff0f, 0xffffffff, 0xffffffff, 0xffffffff, 0x100fffff, 0xf10fffff, + 0xf10fffff, 0xf70fffff, 0xf70fffff, 0xff0fffff, 0xff0fffff, 0xff1fffff, + 0xff0fffff, 0xff0fffff, 0xff0fffff, 0xff0fffff, 0xff1fffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xfffffff1, 0xfffffff3, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffff0f, 0xffffff0f, + 0xffffff0f, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0xff0fffff, 0xff0fffff, 0xff0fffff, 0xff0fffff, 0xff0fffff, 0xff1fffff, + 0xff0fffff, 0xff1fffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, +}; + +static u32 nbl_sec014_data[] =3D { + 0x00000000, 0x00000001, 0x00000003, 0x00000002, 0x00000004, 0x00000005, + 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00000002, 0x00000003, + 0x00000004, 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00000002, + 0x00000003, 0x00000000, 0x00000000, 0x00000004, 0x00000005, 0x00000006, + 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000001, 0x00000002, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000001, + 0x00000002, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000001, 0x00000001, 0x00000001, 0x00000002, 0x00000003, + 0x00000004, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, +}; + +static u32 nbl_sec022_data[] =3D { + 0x81008100, 0x00000001, 0x88a88100, 0x00000001, 0x810088a8, 0x00000001, + 0x88a888a8, 0x00000001, 0x81000000, 0x00000001, 0x88a80000, 0x00000001, + 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x08004000, 0x00000001, 0x86dd6000, 0x00000001, + 0x81000000, 0x00000001, 0x88a80000, 0x00000001, 0x08060000, 0x00000001, + 0x80350000, 0x00000001, 0x88080000, 0x00000001, 0x88f70000, 0x00000001, + 0x88cc0000, 0x00000001, 0x88090000, 0x00000001, 0x89150000, 0x00000001, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x11006000, 0x00000001, + 0x06006000, 0x00000001, 0x02006000, 0x00000001, 0x3a006000, 0x00000001, + 0x2f006000, 0x00000001, 0x84006000, 0x00000001, 0x32006000, 0x00000001, + 0x2c006000, 0x00000001, 0x3c006000, 0x00000001, 0x2b006000, 0x00000001, + 0x00006000, 0x00000001, 0x00004000, 0x00000001, 0x00004000, 0x00000001, + 0x20004000, 0x00000001, 0x40004000, 0x00000001, 0x00000000, 0x00000001, + 0x11000000, 0x00000001, 0x06000000, 0x00000001, 0x02000000, 0x00000001, + 0x3a000000, 0x00000001, 0x2f000000, 0x00000001, 0x84000000, 0x00000001, + 0x32000000, 0x00000001, 0x2c000000, 0x00000001, 0x2b000000, 0x00000001, + 0x3c000000, 0x00000001, 0x3b000000, 0x00000001, 0x00000000, 0x00000001, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x11000000, 0x00000001, 0x06000000, 0x00000001, + 0x02000000, 0x00000001, 0x3a000000, 0x00000001, 0x2f000000, 0x00000001, + 0x84000000, 0x00000001, 0x32000000, 0x00000001, 0x00000000, 0x00000000, + 0x2c000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x2b000000, 0x00000001, 0x3c000000, 0x00000001, + 0x3b000000, 0x00000001, 0x00000000, 0x00000001, 0x06001072, 0x00000001, + 0x06000000, 0x00000001, 0x110012b7, 0x00000001, 0x01000000, 0x00000001, + 0x02000000, 0x00000001, 0x3a000000, 0x00000001, 0x32000000, 0x00000001, + 0x84000000, 0x00000001, 0x11000043, 0x00000001, 0x11000044, 0x00000001, + 0x11000222, 0x00000001, 0x11000000, 0x00000001, 0x2f006558, 0x00000001, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000001, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, +}; + +static u32 nbl_sec023_data[] =3D { + 0x10001000, 0x00001000, 0x10000000, 0x00000000, 0x1000ffff, 0x0000ffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x00000fff, 0x00000fff, + 0x1000ffff, 0x0000ffff, 0x0000ffff, 0x0000ffff, 0x0000ffff, 0x0000ffff, + 0x0000ffff, 0x0000ffff, 0x0000ffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0x00ff0fff, 0x00ff0fff, 0x00ff0fff, 0x00ff0fff, + 0x00ff0fff, 0x00ff0fff, 0x00ff0fff, 0x00ff0fff, 0x00ff0fff, 0x10ff0fff, + 0xffff0fff, 0x00000fff, 0x1fff0fff, 0x1fff0fff, 0x1fff0fff, 0xffffffff, + 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff, + 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x00ffffff, 0x00ffffff, + 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff, 0xffffffff, + 0x00ffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x00ffffff, 0x00ffffff, + 0x00ffffff, 0xffffffff, 0x00ff0000, 0x00ffffff, 0x00ff0000, 0x00ffffff, + 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ff0000, 0x00ff0000, + 0x00ff0001, 0x00ffffff, 0x00ff0000, 0xffffffff, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, +}; + +static u32 nbl_sec024_data[] =3D { + 0x00809190, 0x16009496, 0x00000100, 0x00000000, 0x00809190, 0x16009496, + 0x00000100, 0x00000000, 0x00809190, 0x16009496, 0x00000100, 0x00000000, + 0x00809190, 0x16009496, 0x00000100, 0x00000000, 0x00800090, 0x12009092, + 0x00000100, 0x00000000, 0x00800090, 0x12009092, 0x00000100, 0x00000000, + 0x00800000, 0x0e008c8e, 0x00000100, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08900081, 0x00008680, + 0x00000200, 0x00000000, 0x10900082, 0x28008680, 0x00000200, 0x00000000, + 0x809b0093, 0x00000000, 0x00000100, 0x00000000, 0x809b0093, 0x00000000, + 0x00000100, 0x00000000, 0x009b008f, 0x00000000, 0x00000100, 0x00000000, + 0x009b008f, 0x00000000, 0x00000100, 0x00000000, 0x009b008f, 0x00000000, + 0x00000100, 0x00000000, 0x009b008f, 0x00000000, 0x00000100, 0x00000000, + 0x009b008f, 0x00000000, 0x00000100, 0x00000000, 0x009b008f, 0x00000000, + 0x00000100, 0x00000000, 0x009b0000, 0x00000000, 0x00000100, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x009b0000, 0x00000000, + 0x00000100, 0x00000000, 0x00000000, 0x00000082, 0x00000500, 0x00000000, + 0x00000000, 0x00000082, 0x00000500, 0x00000000, 0x00000000, 0x00000082, + 0x00000500, 0x00000000, 0x00000000, 0x00000082, 0x00000500, 0x00000000, + 0x00000000, 0x00000082, 0x00000500, 0x00000000, 0x00000000, 0x00000082, + 0x00000500, 0x00000000, 0x00000000, 0x00000082, 0x00000500, 0x00000000, + 0x00ab0085, 0x08000000, 0x00000200, 0x00000000, 0x00ab0000, 0x00000000, + 0x00000200, 0x00000000, 0x00ab0000, 0x00000000, 0x00000200, 0x00000000, + 0x40000000, 0x01c180c2, 0x00000300, 0x00000000, 0x00000000, 0x00a089c2, + 0x000005f0, 0x00000000, 0x000b0085, 0x00a00000, 0x000002f0, 0x00000000, + 0x000b0085, 0x00a00000, 0x000002f0, 0x00000000, 0x00000000, 0x00a089c2, + 0x000005f0, 0x00000000, 0x000b0000, 0x00000000, 0x00000200, 0x00000000, + 0x00000000, 0x00000082, 0x00000500, 0x00000000, 0x00000000, 0x00000082, + 0x00000500, 0x00000000, 0x00000000, 0x00000082, 0x00000500, 0x00000000, + 0x00000000, 0x00000082, 0x00000500, 0x00000000, 0x00000000, 0x00000082, + 0x00000500, 0x00000000, 0x00000000, 0x00000082, 0x00000500, 0x00000000, + 0x00000000, 0x00000082, 0x00000500, 0x00000000, 0x00ab0085, 0x08000000, + 0x00000300, 0x00000000, 0x00ab0000, 0x00000000, 0x00000300, 0x00000000, + 0x00ab0000, 0x00000000, 0x00000300, 0x00000000, 0x00ab0000, 0x00000000, + 0x00000300, 0x00000000, 0x40000000, 0x01c180c2, 0x00000400, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000082, + 0x00000500, 0x00000000, 0x00000000, 0x00000082, 0x00000500, 0x00000000, + 0x00000000, 0x00000082, 0x00000500, 0x00000000, 0x00000000, 0x00000082, + 0x00000500, 0x00000000, 0x00000000, 0x00000082, 0x00000500, 0x00000000, + 0x00000000, 0x00000082, 0x00000500, 0x00000000, 0x00000000, 0x00000082, + 0x00000500, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00ab0085, 0x08000000, 0x00000400, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00ab0000, 0x00000000, + 0x00000400, 0x00000000, 0x00ab0000, 0x00000000, 0x00000400, 0x00000000, + 0x00ab0000, 0x00000000, 0x00000400, 0x00000000, 0x00ab0000, 0x00000000, + 0x00000400, 0x00000000, 0x01ab0083, 0x0ca00000, 0x0000050f, 0x00000000, + 0x01ab0083, 0x0ca00000, 0x0000050f, 0x00000000, 0x02ab848a, 0x08000000, + 0x00000500, 0x00000000, 0x00ab8f8e, 0x04000000, 0x00000500, 0x00000000, + 0x00ab0000, 0x00000000, 0x00000500, 0x00000000, 0x00ab8f8e, 0x04000000, + 0x00000500, 0x00000000, 0x00ab0000, 0x00000000, 0x00000500, 0x00000000, + 0x04ab8e84, 0x0c000000, 0x00000500, 0x00000000, 0x02ab848f, 0x08000000, + 0x00000500, 0x00000000, 0x02ab848f, 0x08000000, 0x00000500, 0x00000000, + 0x02ab848f, 0x08000000, 0x00000500, 0x00000000, 0x02ab0084, 0x08000000, + 0x00000500, 0x00000000, 0x00ab0000, 0x04000000, 0x00000500, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00ab0000, 0x00000000, 0x00000500, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, +}; + +static u32 nbl_sec025_data[] =3D { + 0x00000060, 0x00000090, 0x00000001, 0x00000000, 0x00000050, 0x000000a0, + 0x00000001, 0x00000000, 0x000000a0, 0x00000050, 0x00000001, 0x00000000, + 0x00000800, 0x00000700, 0x00000001, 0x00000000, 0x00000900, 0x00000600, + 0x00000001, 0x00000000, 0x00008000, 0x00007000, 0x00000001, 0x00000000, + 0x00009000, 0x00006000, 0x00000001, 0x00000000, 0x0000a000, 0x00005000, + 0x00000001, 0x00000000, 0x000c0000, 0x00030000, 0x00000001, 0x00000000, + 0x000d0000, 0x00020000, 0x00000001, 0x00000000, 0x000e0000, 0x00010000, + 0x00000001, 0x00000000, 0x00000040, 0x000000b0, 0x00000001, 0x00000000, + 0x00000070, 0x00000080, 0x00000001, 0x00000000, 0x00000090, 0x00000060, + 0x00000001, 0x00000000, 0x00000080, 0x00000070, 0x00000001, 0x00000000, + 0x00000700, 0x00000800, 0x00000001, 0x00000000, 0x00007000, 0x00008000, + 0x00000001, 0x00000000, 0x00080000, 0x00070000, 0x00000001, 0x00000000, + 0x00000c00, 0x00000300, 0x00000001, 0x00000000, 0x00000d00, 0x00000200, + 0x00000001, 0x00000000, 0x00400000, 0x00b00000, 0x00000001, 0x00000000, + 0x00600000, 0x00900000, 0x00000001, 0x00000000, 0x00300000, 0x00c00000, + 0x00000001, 0x00000000, 0x00500000, 0x00a00000, 0x00000001, 0x00000000, + 0x00700000, 0x00800000, 0x00000001, 0x00000000, 0x00000000, 0x00f00000, + 0x00000001, 0x00000000, 0x00000000, 0x00f00000, 0x00000001, 0x00000000, + 0x00100000, 0x00e00000, 0x00000001, 0x00000000, 0x00200000, 0x00d00000, + 0x00000001, 0x00000000, 0x00800000, 0x00700000, 0x00000001, 0x00000000, + 0x00900000, 0x00600000, 0x00000001, 0x00000000, 0x00a00000, 0x00500000, + 0x00000001, 0x00000000, 0x00b00000, 0x00400000, 0x00000001, 0x00000000, + 0x000f0000, 0x00000000, 0x00000001, 0x00000000, 0x00f00000, 0x00000000, + 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 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0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, +}; + +static u32 nbl_sec026_data[] =3D { + 0x0000000a, 0x0000000a, 0x0000000a, 0x0000000a, 0x0000000a, 0x0000000a, + 0x0000000a, 0x0000000a, 0x0000000a, 0x0000000a, 0x0000000a, 0x00000000, + 0x0000000b, 0x00000008, 0x00000009, 0x0000000f, 0x0000000f, 0x0000000f, + 0x0000000f, 0x0000000f, 0x0000000c, 0x0000000d, 0x00000001, 0x00000001, + 0x0000000e, 0x00000005, 0x00000002, 0x00000002, 0x00000004, 0x00000003, + 0x00000003, 0x00000003, 0x00000003, 0x0000000a, 0x0000000a, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, +}; + +static u32 nbl_sec027_data[] =3D { + 0x00080020, 0x00080228, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00080224, 0x00080326, 0x00080634, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080020, 0x00080228, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080224, + 0x00080326, 0x00080730, 0x00080834, 0x0008082e, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00080020, 0x00080228, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00080224, 0x00080326, 0x00080730, + 0x00080932, 0x00080a34, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x0009061c, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x0009033a, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00090200, 0x00090304, 0x00090408, 0x0009050c, 0x00090610, 0x00090714, + 0x00090818, 0x0009121c, 0x0009131e, 0x00000000, 0x00000000, 0x00000000, + 0x0009063d, 0x00090740, 0x000d803f, 0x000d413f, 0x0009030c, 0x0009041c, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0009013f, 0x00090840, + 0x000dc93d, 0x000d093d, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000a003c, 0x000a0037, + 0x000ec139, 0x000e0139, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x000a0036, 0x000a0138, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x000a0036, 0x000a0138, 0x000a0742, 0x00000000, 0x00000000, + 0x000a0d41, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000a0036, + 0x000a0138, 0x00000000, 0x00000000, 0x00000000, 0x000a0d3e, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x000a0037, 0x000a0139, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, +}; + +static u32 nbl_sec028_data[] =3D { + 0x00000006, 0x00000001, 0x00000004, 0x00000001, 0x00000000, 0x00000001, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000040, 0x00000001, + 0x00000010, 0x00000001, 0x00000000, 0x00000001, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00500000, 0x00000001, 0x00700000, 0x00000001, + 0x00a00000, 0x00000001, 0x00b00000, 0x00000001, 0x00200000, 0x00000001, + 0x00000000, 0x00000001, 0x00300000, 0x00000001, 0x00800000, 0x00000001, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, +}; + +static u32 nbl_sec029_data[] =3D { + 0xfffffff0, 0xfffffff1, 0xfffffff3, 0xffffffff, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffff0f, 0xffffff0f, 0xffffff0f, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xff0fffff, 0xff0fffff, + 0xff0fffff, 0xff0fffff, 0xff0fffff, 0xff1fffff, 0xff0fffff, 0xff1fffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, +}; + +static u32 nbl_sec030_data[] =3D { + 0x00000000, 0x00000001, 0x00000002, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00000002, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000001, + 0x00000001, 0x00000001, 0x00000002, 0x00000003, 0x00000004, 0x00000001, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, +}; + +static u32 nbl_sec039_data[] =3D { + 0xfef80000, 0x00000002, 0x000002e0, 0x00000000, 0xfef8013e, 0x00000002, + 0x000002e0, 0x00000000, 0x6660013e, 0x726e6802, 0x02224e42, 0x00000000, + 0x6660013e, 0x726e6802, 0x02224e42, 0x00000000, 0x66600000, 0x726e6802, + 0x02224e42, 0x00000000, 0x66600000, 0x726e6802, 0x02224e42, 0x00000000, + 0x66600000, 0x00026802, 0x02224e40, 0x00000000, 0x66627800, 0x00026802, + 0x02224e40, 0x00000000, 0x66600000, 0x00026a76, 0x02224e40, 0x00000000, + 0x66600000, 0x00026802, 0x00024e40, 0x00000000, 0x66600000, 0x00026802, + 0x00024e40, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, +}; + +static u32 nbl_sec040_data[] =3D { + 0x0040fb3f, 0x00000001, 0x0440fb3f, 0x00000001, 0x0502fa00, 0x00000001, + 0x0602f900, 0x00000001, 0x0903e600, 0x00000001, 0x0a03e500, 0x00000001, + 0x1101e600, 0x00000001, 0x1201e500, 0x00000001, 0x0000ff00, 0x00000001, + 0x0008ff07, 0x00000001, 0x00ffff00, 0x00000001, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, +}; + +static u32 nbl_sec046_4p_data[] =3D { + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xa0000000, + 0x00077c2b, 0x005c0000, 0x00000000, 0x00008100, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x20000000, 0x00073029, 0x00480000, + 0x00000000, 0x00008100, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x20000000, 0x00073029, 0x00480000, 0x70000000, 0x00000020, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xa0000000, + 0x00000009, 0x00000000, 0x00000000, 0x00002100, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0xb0000000, 0x00000009, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000100, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x70000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x70000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x38430000, 0x70000006, 0x00000020, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x98cb1180, 0x6e36d469, 0x9d8eb91c, 0x87e3ef47, 0xa2931288, 0x08405c5a, + 0x73865086, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0xb0000000, 0x000b3849, 0x38430000, 0x00000006, 0x0000c100, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xb0000000, + 0x00133889, 0x08400000, 0x03865086, 0x4c016100, 0x00000014, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, +}; + +static u32 nbl_sec047_data[] =3D { + 0x2040dc3f, 0x00000001, 0x2000dcff, 0x00000001, 0x2200dcff, 0x00000001, + 0x0008dc01, 0x00000001, 0x0001de00, 0x00000001, 0x2900c4ff, 0x00000001, + 0x3100c4ff, 0x00000001, 0x2b00c4ff, 0x00000001, 0x3300c4ff, 0x00000001, + 0x2700d8ff, 0x00000001, 0x2300d8ff, 0x00000001, 0x2502d800, 0x00000001, + 0x2102d800, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, +}; + +static u32 nbl_sec052_data[] =3D { + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x30000000, + 0x000b844c, 0xc8580000, 0x00000006, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x20000000, 0xb0d3668b, 0xb0555e12, + 0x03b055c6, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x20000000, 0xa64b3449, 0x405a3cc1, 0x00000006, 0x3d2d3300, + 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x20000000, + 0x26473429, 0x00482cc1, 0x00000000, 0x00ccd300, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, +}; + +static u32 nbl_sec053_data[] =3D { + 0x0840f03f, 0x00000001, 0x0040f03f, 0x00000001, 0x0140fa3f, 0x00000001, + 0x0100fa0f, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, +}; + +static u32 nbl_sec058_data[] =3D { + 0x00000000, 0x00000000, 0x59f89400, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00470000, 0x00000000, 0x3c000000, 0xa2e40006, 0x00000017, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x19fa1400, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x28440000, + 0x038e5186, 0x3c000000, 0xa8e40012, 0x00000047, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0001f3d0, 0x00000000, + 0x00000000, 0xb0000000, 0x00133889, 0x38c30000, 0x0000000a, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x0001f3d0, 0x00000000, 0x00000000, 0xb0000000, + 0x00133889, 0x38c30000, 0x0000000a, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x000113d0, 0x00000000, 0x00000000, 0xb0000000, 0x00073829, 0x00430000, + 0x00000000, 0x3c000000, 0x0000000a, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000293d0, 0x00000000, + 0x00000000, 0xb0000000, 0x00133889, 0x08400000, 0x03865086, 0x3c000000, + 0x00000016, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, +}; + +static u32 nbl_sec059_data[] =3D { + 0x0200e4ff, 0x00000001, 0x0400e2ff, 0x00000001, 0x1300ecff, 0x00000001, + 0x1500eaff, 0x00000001, 0x0300e4ff, 0x00000001, 0x0500e2ff, 0x00000001, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, +}; + +static u32 nbl_sec062_data[] =3D { + 0x90939899, 0x88809c9b, 0x0000013d, 0x00000000, 0x90939899, 0x88809c9b, + 0x0000013d, 0x00000000, 0x90939899, 0x88809c9b, 0x0000013d, 0x00000000, + 0x90939899, 0x88809c9b, 0x0000013d, 0x00000000, 0x90939899, 0x88809c9b, + 0x0000013d, 0x00000000, 0x90939899, 0x88809c9b, 0x0000013d, 0x00000000, + 0x90939899, 0x88809c9b, 0x0000013d, 0x00000000, 0x90939899, 0x88809c9b, + 0x0000013d, 0x00000000, 0x90939899, 0x88809c9b, 0x0000013d, 0x00000000, + 0x90939899, 0x88809c9b, 0x0000013d, 0x00000000, 0x90939899, 0x88809c9b, + 0x0000013d, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, +}; + +static u32 nbl_sec063_data[] =3D { + 0x0500e2ff, 0x00000001, 0x0900e2ff, 0x00000001, 0x1900e2ff, 0x00000001, + 0x1100e2ff, 0x00000001, 0x0100e2ff, 0x00000001, 0x0600e1ff, 0x00000001, + 0x0a00e1ff, 0x00000001, 0x1a00e1ff, 0x00000001, 0x1200e1ff, 0x00000001, + 0x0200e1ff, 0x00000001, 0x0000fcff, 0x00000001, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, +}; + +static u32 nbl_sec065_data[] =3D { + 0x006e120c, 0x006e1210, 0x006e4208, 0x006e4218, 0x00200b02, 0x00200b00, + 0x000e1900, 0x000e1906, 0x00580208, 0x00580204, 0x004c0208, 0x004c0207, + 0x0002110c, 0x0002110c, 0x0012010c, 0x00100110, 0x0010010c, 0x000a010c, + 0x0008010c, 0x00060000, 0x00160000, 0x00140000, 0x001e0000, 0x001e0000, + 0x001e0000, 0x001e0000, 0x001e0000, 0x001e0000, 0x001e0000, 0x001e0000, + 0x001e0000, 0x001e0000, +}; + +static u32 nbl_sec066_data[] =3D { + 0x006e120c, 0x006e1210, 0x006e4208, 0x006e4218, 0x00200b02, 0x00200b00, + 0x000e1900, 0x000e1906, 0x00580208, 0x00580204, 0x004c0208, 0x004c0207, + 0x0002110c, 0x0002110c, 0x0012010c, 0x00100110, 0x0010010c, 0x000a010c, + 0x0008010c, 0x00060000, 0x00160000, 0x00140000, 0x001e0000, 0x001e0000, + 0x001e0000, 0x001e0000, 0x001e0000, 0x001e0000, 0x001e0000, 0x001e0000, + 0x001e0000, 0x001e0000, +}; + +static u32 nbl_sec071_4p_data[] =3D { + 0x00000000, 0x00000000, 0x00113d00, 0x00000000, 0x00000000, 0x00000000, + 0xe7029b00, 0x00000000, 0x00000000, 0x43000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x51e00000, 0x00000c9c, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00293d00, 0x00000000, + 0x00000000, 0x00000000, 0x67089b00, 0x00000002, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x80000000, 0x00000000, 0xb1e00000, 0x0000189c, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00213d00, 0x00000000, 0x00000000, 0x00000000, 0xe7069b00, 0x00000001, + 0x00000000, 0x43000000, 0x014b0c70, 0x00000000, 0x00000000, 0x00000000, + 0x92600000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00213d00, 0x00000000, 0x00000000, 0x00000000, + 0xe7069b00, 0x00000001, 0x00000000, 0x43000000, 0x015b0c70, 0x00000000, + 0x00000000, 0x00000000, 0x92600000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00553d00, 0x00000000, + 0x00000000, 0x00000000, 0xe6d29a00, 0x000149c4, 0x00000000, 0x4b000000, + 0x00000004, 0x00000000, 0x80000000, 0x00022200, 0x62600000, 0x00000001, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00553d00, 0x00000000, 0x00000000, 0x00000000, 0xe6d2c000, 0x000149c4, + 0x00000000, 0x5b000000, 0x00000004, 0x00000000, 0x80000000, 0x00022200, + 0x62600000, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x006d3d00, 0x00000000, 0x00000000, 0x00000000, + 0x64d49200, 0x5e556945, 0xc666d89a, 0x4b0001a9, 0x00004c84, 0x00000000, + 0x80000000, 0x00022200, 0xc2600000, 0x00000001, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x006d3d00, 0x00000000, + 0x00000000, 0x00000000, 0x6ed4ba00, 0x5ef56bc5, 0xc666d8c0, 0x5b0001a9, + 0x00004dc4, 0x00000000, 0x80000000, 0x00022200, 0xc2600000, 0x00000001, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000002, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00700000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, +}; + +static u32 nbl_sec072_data[] =3D { + 0x84006aff, 0x00000001, 0x880066ff, 0x00000001, 0x140040ff, 0x00000001, + 0x70000cff, 0x00000001, 0x180040ff, 0x00000001, 0x30000cff, 0x00000001, + 0x10004cff, 0x00000001, 0x30004cff, 0x00000001, 0x0100ecff, 0x00000001, + 0x0300ecff, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, +}; + +static u32 nbl_sec116_data[] =3D { + 0x00000000, 0x00000000, 0x3fff8000, 0x00000007, 0x3fff8000, 0x00000007, + 0x3fff8000, 0x00000007, 0x3fff8000, 0x00000003, 0x3fff8000, 0x00000003, + 0x3fff8000, 0x00000007, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, +}; + +static u32 nbl_sec124_data[] =3D { + 0xfffffffc, 0xffffffff, 0x00300000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000500, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfffffffc, 0xffffffff, + 0x00300010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000500, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0xfffffffc, 0xffffffff, 0x00300010, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000500, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0xfffffffc, 0xffffffff, 0x00300fff, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000580, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfffffffc, 0xffffffff, + 0x00301fff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000580, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0xfffffffc, 0xffffffff, 0x0030ffff, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000580, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0xfffffffc, 0xffffffff, 0x0030ffff, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000580, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfffffffc, 0xffffffff, + 0x0030ffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000580, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0xfffffffc, 0xffffffff, 0x0030ffff, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000580, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0xfffffffc, 0xffffffff, 0x00300000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000500, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000fffe, 0x00000000, + 0x00300000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000480, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0xfffffffc, 0x00ffffff, 0x00300000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000480, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0xfffffffe, 0x0000000f, 0x00300000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000580, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, +}; + +static u32 nbl_sec125_data[] =3D { + 0xfffffffc, 0x01ffffff, 0x00300000, 0x70000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000480, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfffffffe, 0x00000001, + 0x00300000, 0x70000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000540, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0xfffffffe, 0x011003ff, 0x00300000, 0x70000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000005c0, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0xfffffffc, 0x103fffff, 0x00300001, 0x70000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000480, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, +}; + +static u32 nbl_sec126_data[] =3D { + 0xfffffffc, 0xffffffff, 0x00300001, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000500, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfffffffe, 0x000001ff, + 0x00300000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x000005c0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00002013, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000400, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00002013, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000400, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfffffffc, 0x01ffffff, + 0x00300000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000480, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0xfffffffe, 0x00000001, 0x00300000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000540, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, +}; + +static u32 nbl_sec137_data[] =3D { + 0x0000017a, 0x000000f2, 0x00000076, 0x0000017a, 0x0000017a, 0x00000080, + 0x00000024, 0x0000017a, 0x0000017a, 0x00000191, 0x00000035, 0x0000017a, + 0x0000017a, 0x0000017a, 0x0000017a, 0x0000017a, 0x0000017a, 0x000000d2, + 0x00000066, 0x0000017a, 0x0000017a, 0x0000017a, 0x0000017a, 0x0000017a, + 0x0000017a, 0x000000f2, 0x00000076, 0x0000017a, 0x0000017a, 0x0000017a, + 0x0000017a, 0x0000017a, +}; + +static u32 nbl_sec138_data[] =3D { + 0x0000017a, 0x000000f2, 0x00000076, 0x0000017a, 0x0000017a, 0x00000080, + 0x00000024, 0x0000017a, 0x0000017a, 0x00000191, 0x00000035, 0x0000017a, + 0x0000017a, 0x0000017a, 0x0000017a, 0x0000017a, 0x0000017a, 0x000000d2, + 0x00000066, 0x0000017a, 0x0000017a, 0x0000017a, 0x0000017a, 0x0000017a, + 0x0000017a, 0x000000f2, 0x00000076, 0x0000017a, 0x0000017a, 0x0000017a, + 0x0000017a, 0x0000017a, +}; + +void nbl_write_all_regs(struct nbl_hw_mgt *hw_mgt) +{ + struct nbl_common_info *common =3D hw_mgt->common; + u32 *nbl_sec046_data; + u32 *nbl_sec071_data; + u8 eth_mode =3D common->eth_mode; + u32 i =3D 0; + + switch (eth_mode) { + case 1: + nbl_sec046_data =3D nbl_sec046_1p_data; + nbl_sec071_data =3D nbl_sec071_1p_data; + break; + case 2: + nbl_sec046_data =3D nbl_sec046_2p_data; + nbl_sec071_data =3D nbl_sec071_2p_data; + break; + case 4: + nbl_sec046_data =3D nbl_sec046_4p_data; + nbl_sec071_data =3D nbl_sec071_4p_data; + break; + default: + nbl_sec046_data =3D nbl_sec046_2p_data; + nbl_sec071_data =3D nbl_sec071_2p_data; + } + + nbl_flush_writes(hw_mgt); + for (i =3D 0; i < NBL_SEC006_SIZE; i++) { + if ((i + 1) % NBL_SEC_BLOCK_SIZE =3D=3D 0) + nbl_hw_rd32(hw_mgt, NBL_HW_DUMMY_REG); + + nbl_hw_wr32(hw_mgt, NBL_SEC006_REGI(i), nbl_sec006_data[i]); + } + + nbl_flush_writes(hw_mgt); + for (i =3D 0; i < NBL_SEC007_SIZE; i++) + nbl_hw_wr32(hw_mgt, NBL_SEC007_REGI(i), nbl_sec007_data[i]); + + nbl_flush_writes(hw_mgt); + for (i =3D 0; i < NBL_SEC008_SIZE; i++) { + if ((i + 1) % NBL_SEC_BLOCK_SIZE =3D=3D 0) + nbl_hw_rd32(hw_mgt, NBL_HW_DUMMY_REG); + + nbl_hw_wr32(hw_mgt, NBL_SEC008_REGI(i), nbl_sec008_data[i]); + } + + nbl_flush_writes(hw_mgt); + for (i =3D 0; i < NBL_SEC009_SIZE; i++) { + if ((i + 1) % NBL_SEC_BLOCK_SIZE =3D=3D 0) + nbl_hw_rd32(hw_mgt, NBL_HW_DUMMY_REG); + + nbl_hw_wr32(hw_mgt, NBL_SEC009_REGI(i), nbl_sec009_data[i]); + } + + nbl_flush_writes(hw_mgt); + for (i =3D 0; i < NBL_SEC010_SIZE; i++) + nbl_hw_wr32(hw_mgt, NBL_SEC010_REGI(i), nbl_sec010_data[i]); + + nbl_flush_writes(hw_mgt); + for (i =3D 0; i < NBL_SEC011_SIZE; i++) { + if ((i + 1) % NBL_SEC_BLOCK_SIZE =3D=3D 0) + nbl_hw_rd32(hw_mgt, NBL_HW_DUMMY_REG); + + nbl_hw_wr32(hw_mgt, NBL_SEC011_REGI(i), nbl_sec011_data[i]); + } + + nbl_flush_writes(hw_mgt); + for (i =3D 0; i < NBL_SEC012_SIZE; i++) + nbl_hw_wr32(hw_mgt, NBL_SEC012_REGI(i), nbl_sec012_data[i]); + + nbl_flush_writes(hw_mgt); + for (i =3D 0; i < NBL_SEC013_SIZE; i++) + nbl_hw_wr32(hw_mgt, NBL_SEC013_REGI(i), nbl_sec013_data[i]); + + nbl_flush_writes(hw_mgt); + for (i =3D 0; i < NBL_SEC014_SIZE; i++) + nbl_hw_wr32(hw_mgt, NBL_SEC014_REGI(i), nbl_sec014_data[i]); + + nbl_flush_writes(hw_mgt); + for (i =3D 0; i < NBL_SEC022_SIZE; i++) + nbl_hw_wr32(hw_mgt, NBL_SEC022_REGI(i), nbl_sec022_data[i]); + + nbl_flush_writes(hw_mgt); + for (i =3D 0; i < NBL_SEC023_SIZE; i++) + nbl_hw_wr32(hw_mgt, NBL_SEC023_REGI(i), nbl_sec023_data[i]); + + nbl_flush_writes(hw_mgt); + for (i =3D 0; i < NBL_SEC024_SIZE; i++) { + if ((i + 1) % NBL_SEC_BLOCK_SIZE =3D=3D 0) + nbl_hw_rd32(hw_mgt, NBL_HW_DUMMY_REG); + + nbl_hw_wr32(hw_mgt, NBL_SEC024_REGI(i), nbl_sec024_data[i]); + } + + nbl_flush_writes(hw_mgt); + for (i =3D 0; i < NBL_SEC025_SIZE; i++) { + if ((i + 1) % NBL_SEC_BLOCK_SIZE =3D=3D 0) + nbl_hw_rd32(hw_mgt, NBL_HW_DUMMY_REG); + + nbl_hw_wr32(hw_mgt, NBL_SEC025_REGI(i), nbl_sec025_data[i]); + } + + nbl_flush_writes(hw_mgt); + for (i =3D 0; i < NBL_SEC026_SIZE; i++) + nbl_hw_wr32(hw_mgt, NBL_SEC026_REGI(i), nbl_sec026_data[i]); + + nbl_flush_writes(hw_mgt); + for (i =3D 0; i < NBL_SEC027_SIZE; i++) { + if ((i + 1) % NBL_SEC_BLOCK_SIZE =3D=3D 0) + nbl_hw_rd32(hw_mgt, NBL_HW_DUMMY_REG); + + nbl_hw_wr32(hw_mgt, NBL_SEC027_REGI(i), nbl_sec027_data[i]); + } + + nbl_flush_writes(hw_mgt); + for (i =3D 0; i < NBL_SEC028_SIZE; i++) + nbl_hw_wr32(hw_mgt, NBL_SEC028_REGI(i), nbl_sec028_data[i]); + + nbl_flush_writes(hw_mgt); + for (i =3D 0; i < NBL_SEC029_SIZE; i++) + nbl_hw_wr32(hw_mgt, NBL_SEC029_REGI(i), nbl_sec029_data[i]); + + nbl_flush_writes(hw_mgt); + for (i =3D 0; i < NBL_SEC030_SIZE; i++) + nbl_hw_wr32(hw_mgt, NBL_SEC030_REGI(i), nbl_sec030_data[i]); + + nbl_flush_writes(hw_mgt); + for (i =3D 0; i < NBL_SEC039_SIZE; i++) + nbl_hw_wr32(hw_mgt, NBL_SEC039_REGI(i), nbl_sec039_data[i]); + + nbl_flush_writes(hw_mgt); + for (i =3D 0; i < NBL_SEC040_SIZE; i++) + nbl_hw_wr32(hw_mgt, NBL_SEC040_REGI(i), nbl_sec040_data[i]); + + nbl_flush_writes(hw_mgt); + for (i =3D 0; i < NBL_SEC046_SIZE; i++) + nbl_hw_wr32(hw_mgt, NBL_SEC046_REGI(i), nbl_sec046_data[i]); + + nbl_flush_writes(hw_mgt); + for (i =3D 0; i < NBL_SEC047_SIZE; i++) + nbl_hw_wr32(hw_mgt, NBL_SEC047_REGI(i), nbl_sec047_data[i]); + + nbl_flush_writes(hw_mgt); + for (i =3D 0; i < NBL_SEC052_SIZE; i++) + nbl_hw_wr32(hw_mgt, NBL_SEC052_REGI(i), nbl_sec052_data[i]); + + nbl_flush_writes(hw_mgt); + for (i =3D 0; i < NBL_SEC053_SIZE; i++) + nbl_hw_wr32(hw_mgt, NBL_SEC053_REGI(i), nbl_sec053_data[i]); + + nbl_flush_writes(hw_mgt); + for (i =3D 0; i < NBL_SEC058_SIZE; i++) + nbl_hw_wr32(hw_mgt, NBL_SEC058_REGI(i), nbl_sec058_data[i]); + + nbl_flush_writes(hw_mgt); + for (i =3D 0; i < NBL_SEC059_SIZE; i++) + nbl_hw_wr32(hw_mgt, NBL_SEC059_REGI(i), nbl_sec059_data[i]); + + nbl_flush_writes(hw_mgt); + for (i =3D 0; i < NBL_SEC062_SIZE; i++) + nbl_hw_wr32(hw_mgt, NBL_SEC062_REGI(i), nbl_sec062_data[i]); + + nbl_flush_writes(hw_mgt); + for (i =3D 0; i < NBL_SEC063_SIZE; i++) + nbl_hw_wr32(hw_mgt, NBL_SEC063_REGI(i), nbl_sec063_data[i]); + + nbl_flush_writes(hw_mgt); + for (i =3D 0; i < NBL_SEC065_SIZE; i++) + nbl_hw_wr32(hw_mgt, NBL_SEC065_REGI(i), nbl_sec065_data[i]); + + nbl_flush_writes(hw_mgt); + for (i =3D 0; i < NBL_SEC066_SIZE; i++) + nbl_hw_wr32(hw_mgt, NBL_SEC066_REGI(i), nbl_sec066_data[i]); + + nbl_flush_writes(hw_mgt); + for (i =3D 0; i < NBL_SEC071_SIZE; i++) { + if ((i + 1) % NBL_SEC_BLOCK_SIZE =3D=3D 0) + nbl_hw_rd32(hw_mgt, NBL_HW_DUMMY_REG); + + nbl_hw_wr32(hw_mgt, NBL_SEC071_REGI(i), nbl_sec071_data[i]); + } + + nbl_flush_writes(hw_mgt); + for (i =3D 0; i < NBL_SEC072_SIZE; i++) + nbl_hw_wr32(hw_mgt, NBL_SEC072_REGI(i), nbl_sec072_data[i]); + + nbl_flush_writes(hw_mgt); + for (i =3D 0; i < NBL_SEC116_SIZE; i++) + nbl_hw_wr32(hw_mgt, NBL_SEC116_REGI(i), nbl_sec116_data[i]); + + nbl_flush_writes(hw_mgt); + for (i =3D 0; i < NBL_SEC124_SIZE; i++) + nbl_hw_wr32(hw_mgt, NBL_SEC124_REGI(i), nbl_sec124_data[i]); + + nbl_flush_writes(hw_mgt); + for (i =3D 0; i < NBL_SEC125_SIZE; i++) + nbl_hw_wr32(hw_mgt, NBL_SEC125_REGI(i), nbl_sec125_data[i]); + + nbl_flush_writes(hw_mgt); + for (i =3D 0; i < NBL_SEC126_SIZE; i++) + nbl_hw_wr32(hw_mgt, NBL_SEC126_REGI(i), nbl_sec126_data[i]); + + nbl_flush_writes(hw_mgt); + for (i =3D 0; i < NBL_SEC137_SIZE; i++) + nbl_hw_wr32(hw_mgt, NBL_SEC137_REGI(i), nbl_sec137_data[i]); + + nbl_flush_writes(hw_mgt); + for (i =3D 0; i < NBL_SEC138_SIZE; i++) + nbl_hw_wr32(hw_mgt, NBL_SEC138_REGI(i), nbl_sec138_data[i]); + + nbl_flush_writes(hw_mgt); + nbl_hw_wr32(hw_mgt, NBL_SEC000_ADDR, 0x00000001); + nbl_hw_wr32(hw_mgt, NBL_SEC001_ADDR, 0x00000001); + nbl_hw_wr32(hw_mgt, NBL_SEC002_ADDR, 0x00000001); + nbl_hw_wr32(hw_mgt, NBL_SEC003_ADDR, 0x00000001); + nbl_hw_wr32(hw_mgt, NBL_SEC004_ADDR, 0x00000001); + nbl_hw_wr32(hw_mgt, NBL_SEC005_ADDR, 0x00000001); + nbl_hw_wr32(hw_mgt, NBL_SEC015_ADDR, 0x000f0908); + nbl_hw_wr32(hw_mgt, NBL_SEC016_ADDR, 0x10110607); + nbl_hw_wr32(hw_mgt, NBL_SEC017_ADDR, 0x383a3032); + nbl_hw_wr32(hw_mgt, NBL_SEC018_ADDR, 0x0201453f); + nbl_hw_wr32(hw_mgt, NBL_SEC019_ADDR, 0x00000a41); + nbl_hw_wr32(hw_mgt, NBL_SEC020_ADDR, 0x000000c8); + nbl_hw_wr32(hw_mgt, NBL_SEC021_ADDR, 0x00000400); + nbl_hw_wr32(hw_mgt, NBL_SEC031_ADDR, 0x000f0908); + nbl_hw_wr32(hw_mgt, NBL_SEC032_ADDR, 0x00001011); + nbl_hw_wr32(hw_mgt, NBL_SEC033_ADDR, 0x00003032); + nbl_hw_wr32(hw_mgt, NBL_SEC034_ADDR, 0x0201003f); + nbl_hw_wr32(hw_mgt, NBL_SEC035_ADDR, 0x0000000a); + nbl_hw_wr32(hw_mgt, NBL_SEC036_ADDR, 0x00001701); + nbl_hw_wr32(hw_mgt, NBL_SEC037_ADDR, 0x009238a1); + nbl_hw_wr32(hw_mgt, NBL_SEC038_ADDR, 0x0000002e); + nbl_hw_wr32(hw_mgt, NBL_SEC041_REGI(0), 0x00000200); + nbl_hw_wr32(hw_mgt, NBL_SEC041_REGI(1), 0x00000300); + nbl_hw_wr32(hw_mgt, NBL_SEC041_REGI(2), 0x00000105); + nbl_hw_wr32(hw_mgt, NBL_SEC041_REGI(3), 0x00000106); + nbl_hw_wr32(hw_mgt, NBL_SEC041_REGI(4), 0x00000009); + nbl_hw_wr32(hw_mgt, NBL_SEC041_REGI(5), 0x0000000a); + nbl_hw_wr32(hw_mgt, NBL_SEC041_REGI(6), 0x00000041); + nbl_hw_wr32(hw_mgt, NBL_SEC041_REGI(7), 0x00000082); + nbl_hw_wr32(hw_mgt, NBL_SEC041_REGI(8), 0x00000020); + nbl_hw_wr32(hw_mgt, NBL_SEC041_REGI(9), 0x00000000); + nbl_hw_wr32(hw_mgt, NBL_SEC041_REGI(10), 0x00000000); + nbl_hw_wr32(hw_mgt, NBL_SEC041_REGI(11), 0x00000000); + nbl_hw_wr32(hw_mgt, NBL_SEC041_REGI(12), 0x00000000); + nbl_hw_wr32(hw_mgt, NBL_SEC041_REGI(13), 0x00000000); + nbl_hw_wr32(hw_mgt, NBL_SEC041_REGI(14), 0x00000000); + nbl_hw_wr32(hw_mgt, NBL_SEC041_REGI(15), 0x00000000); + nbl_hw_wr32(hw_mgt, NBL_SEC042_ADDR, 0x00000001); + nbl_hw_wr32(hw_mgt, NBL_SEC043_ADDR, 0x00000002); + nbl_hw_wr32(hw_mgt, NBL_SEC044_ADDR, 0x28212000); + nbl_hw_wr32(hw_mgt, NBL_SEC045_ADDR, 0x00002b29); + nbl_hw_wr32(hw_mgt, NBL_SEC048_ADDR, 0x00000001); + nbl_hw_wr32(hw_mgt, NBL_SEC049_ADDR, 0x00000002); + nbl_hw_wr32(hw_mgt, NBL_SEC050_ADDR, 0x352b2000); + nbl_hw_wr32(hw_mgt, NBL_SEC051_ADDR, 0x00000000); + nbl_hw_wr32(hw_mgt, NBL_SEC054_ADDR, 0x00000001); + nbl_hw_wr32(hw_mgt, NBL_SEC055_ADDR, 0x00000002); + nbl_hw_wr32(hw_mgt, NBL_SEC056_ADDR, 0x2b222100); + nbl_hw_wr32(hw_mgt, NBL_SEC057_ADDR, 0x00000038); + nbl_hw_wr32(hw_mgt, NBL_SEC060_ADDR, 0x24232221); + nbl_hw_wr32(hw_mgt, NBL_SEC061_ADDR, 0x0000002e); + nbl_hw_wr32(hw_mgt, NBL_SEC064_REGI(0), 0x00000009); + nbl_hw_wr32(hw_mgt, NBL_SEC064_REGI(1), 0x00000005); + nbl_hw_wr32(hw_mgt, NBL_SEC064_REGI(2), 0x00000011); + nbl_hw_wr32(hw_mgt, NBL_SEC064_REGI(3), 0x00000005); + nbl_hw_wr32(hw_mgt, NBL_SEC064_REGI(4), 0x00000001); + nbl_hw_wr32(hw_mgt, NBL_SEC064_REGI(5), 0x0000000a); + nbl_hw_wr32(hw_mgt, NBL_SEC064_REGI(6), 0x00000006); + nbl_hw_wr32(hw_mgt, NBL_SEC064_REGI(7), 0x00000012); + nbl_hw_wr32(hw_mgt, NBL_SEC064_REGI(8), 0x00000006); + nbl_hw_wr32(hw_mgt, NBL_SEC064_REGI(9), 0x00000002); + nbl_hw_wr32(hw_mgt, NBL_SEC064_REGI(10), 0x00000000); + nbl_hw_wr32(hw_mgt, NBL_SEC064_REGI(11), 0x00000000); + nbl_hw_wr32(hw_mgt, NBL_SEC064_REGI(12), 0x00000000); + nbl_hw_wr32(hw_mgt, NBL_SEC064_REGI(13), 0x00000000); + nbl_hw_wr32(hw_mgt, NBL_SEC064_REGI(14), 0x00000000); + nbl_hw_wr32(hw_mgt, NBL_SEC064_REGI(15), 0x00000000); + nbl_hw_wr32(hw_mgt, NBL_SEC067_ADDR, 0x00000001); + nbl_hw_wr32(hw_mgt, NBL_SEC068_ADDR, 0x00000001); + nbl_hw_wr32(hw_mgt, NBL_SEC069_ADDR, 0x22212000); + nbl_hw_wr32(hw_mgt, NBL_SEC070_ADDR, 0x3835322b); + nbl_hw_wr32(hw_mgt, NBL_SEC073_ADDR, 0x0316a5ff); + nbl_hw_wr32(hw_mgt, NBL_SEC074_ADDR, 0x0316a5ff); + nbl_hw_wr32(hw_mgt, NBL_SEC075_REGI(0), 0x08802080); + nbl_hw_wr32(hw_mgt, NBL_SEC075_REGI(1), 0x12a05080); + nbl_hw_wr32(hw_mgt, NBL_SEC075_REGI(2), 0xffffffff); + nbl_hw_wr32(hw_mgt, NBL_SEC075_REGI(3), 0xffffffff); + nbl_hw_wr32(hw_mgt, NBL_SEC076_REGI(0), 0x08802080); + nbl_hw_wr32(hw_mgt, NBL_SEC076_REGI(1), 0x12a05080); + nbl_hw_wr32(hw_mgt, NBL_SEC076_REGI(2), 0xffffffff); + nbl_hw_wr32(hw_mgt, NBL_SEC076_REGI(3), 0xffffffff); + nbl_hw_wr32(hw_mgt, NBL_SEC077_REGI(0), 0x08802080); + nbl_hw_wr32(hw_mgt, NBL_SEC077_REGI(1), 0x12a05080); + nbl_hw_wr32(hw_mgt, NBL_SEC077_REGI(2), 0xffffffff); + nbl_hw_wr32(hw_mgt, NBL_SEC077_REGI(3), 0xffffffff); + nbl_hw_wr32(hw_mgt, NBL_SEC078_ADDR, 0x00000009); + nbl_hw_wr32(hw_mgt, NBL_SEC079_ADDR, 0x00000009); + nbl_hw_wr32(hw_mgt, NBL_SEC080_ADDR, 0x0014a248); + nbl_hw_wr32(hw_mgt, NBL_SEC081_ADDR, 0x00000d33); + nbl_hw_wr32(hw_mgt, NBL_SEC082_ADDR, 0x00000009); + nbl_hw_wr32(hw_mgt, NBL_SEC083_ADDR, 0x00000009); + nbl_hw_wr32(hw_mgt, NBL_SEC084_ADDR, 0x00000009); + nbl_hw_wr32(hw_mgt, NBL_SEC085_ADDR, 0x000144d2); + nbl_hw_wr32(hw_mgt, NBL_SEC086_ADDR, 0x31322e2f); + nbl_hw_wr32(hw_mgt, NBL_SEC087_ADDR, 0x0a092d2c); + nbl_hw_wr32(hw_mgt, NBL_SEC088_ADDR, 0x33050804); + nbl_hw_wr32(hw_mgt, NBL_SEC089_ADDR, 0x14131535); + nbl_hw_wr32(hw_mgt, NBL_SEC090_ADDR, 0x0000000a); + nbl_hw_wr32(hw_mgt, NBL_SEC091_ADDR, 0x00000009); + nbl_hw_wr32(hw_mgt, NBL_SEC092_ADDR, 0x00000008); + nbl_hw_wr32(hw_mgt, NBL_SEC093_ADDR, 0x0000000e); + nbl_hw_wr32(hw_mgt, NBL_SEC094_ADDR, 0x0000000f); + nbl_hw_wr32(hw_mgt, NBL_SEC095_ADDR, 0x00000015); + nbl_hw_wr32(hw_mgt, NBL_SEC096_ADDR, 0x00000009); + nbl_hw_wr32(hw_mgt, NBL_SEC097_ADDR, 0x0000000a); + nbl_hw_wr32(hw_mgt, NBL_SEC098_ADDR, 0x00000008); + nbl_hw_wr32(hw_mgt, NBL_SEC099_ADDR, 0x00000011); + nbl_hw_wr32(hw_mgt, NBL_SEC100_ADDR, 0x00000013); + nbl_hw_wr32(hw_mgt, NBL_SEC101_ADDR, 0x00000014); + nbl_hw_wr32(hw_mgt, NBL_SEC102_ADDR, 0x00000010); + nbl_hw_wr32(hw_mgt, NBL_SEC103_ADDR, 0x00000009); + nbl_hw_wr32(hw_mgt, NBL_SEC104_ADDR, 0x0000004d); + nbl_hw_wr32(hw_mgt, NBL_SEC105_ADDR, 0x08020a09); + nbl_hw_wr32(hw_mgt, NBL_SEC106_ADDR, 0x00000005); + nbl_hw_wr32(hw_mgt, NBL_SEC107_ADDR, 0x00000006); + nbl_hw_wr32(hw_mgt, NBL_SEC108_ADDR, 0x00000009); + nbl_hw_wr32(hw_mgt, NBL_SEC109_ADDR, 0x00110a09); + nbl_hw_wr32(hw_mgt, NBL_SEC110_ADDR, 0x00000009); + nbl_hw_wr32(hw_mgt, NBL_SEC111_ADDR, 0x00000009); + nbl_hw_wr32(hw_mgt, NBL_SEC112_ADDR, 0x00000009); + nbl_hw_wr32(hw_mgt, NBL_SEC113_ADDR, 0x0000000a); + nbl_hw_wr32(hw_mgt, NBL_SEC114_ADDR, 0x0000000a); + nbl_hw_wr32(hw_mgt, NBL_SEC115_ADDR, 0x00000009); + nbl_hw_wr32(hw_mgt, NBL_SEC117_ADDR, 0x0000000a); + nbl_hw_wr32(hw_mgt, NBL_SEC118_ADDR, 0x00000001); + nbl_hw_wr32(hw_mgt, NBL_SEC119_REGI(0), 0x00000000); + nbl_hw_wr32(hw_mgt, NBL_SEC119_REGI(1), 0x00000000); + nbl_hw_wr32(hw_mgt, NBL_SEC119_REGI(2), 0x00000000); + nbl_hw_wr32(hw_mgt, NBL_SEC119_REGI(3), 0x00000000); + nbl_hw_wr32(hw_mgt, NBL_SEC119_REGI(4), 0x00000100); + nbl_hw_wr32(hw_mgt, NBL_SEC120_ADDR, 0x0000003c); + nbl_hw_wr32(hw_mgt, NBL_SEC121_ADDR, 0x00000003); + nbl_hw_wr32(hw_mgt, NBL_SEC122_ADDR, 0x000000bc); + nbl_hw_wr32(hw_mgt, NBL_SEC123_ADDR, 0x0000023b); + nbl_hw_wr32(hw_mgt, NBL_SEC127_ADDR, 0x00000001); + nbl_hw_wr32(hw_mgt, NBL_SEC128_ADDR, 0x00000001); + nbl_hw_wr32(hw_mgt, NBL_SEC129_ADDR, 0x00000002); + nbl_hw_wr32(hw_mgt, NBL_SEC130_ADDR, 0x00000002); + nbl_hw_wr32(hw_mgt, NBL_SEC131_ADDR, 0x00000003); + nbl_hw_wr32(hw_mgt, NBL_SEC132_ADDR, 0x00000003); + nbl_hw_wr32(hw_mgt, NBL_SEC133_ADDR, 0x00000004); + nbl_hw_wr32(hw_mgt, NBL_SEC134_ADDR, 0x00000004); + nbl_hw_wr32(hw_mgt, NBL_SEC135_ADDR, 0x0000000e); + nbl_hw_wr32(hw_mgt, NBL_SEC136_ADDR, 0x0000000e); + nbl_flush_writes(hw_mgt); +} diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nb= l_hw_leonis_regs.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_l= eonis/nbl_hw_leonis_regs.h new file mode 100644 index 000000000000..75b7dd783354 --- /dev/null +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_le= onis_regs.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0*/ +/* + * Copyright (c) 2025 Nebula Matrix Limited. + * Author: + */ + +#ifndef _NBL_HW_LEONIS_REGS_H_ +#define _NBL_HW_LEONIS_REGS_H_ + +void nbl_write_all_regs(struct nbl_hw_mgt *hw_mgt); + +#endif --=20 2.47.3 From nobody Sun Feb 8 00:11:39 2026 Received: from out28-196.mail.aliyun.com (out28-196.mail.aliyun.com [115.124.28.196]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BE0642566D3; Fri, 6 Feb 2026 02:23:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.28.196 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770344626; cv=none; b=rRWY2DD5Ro1E+5922UjjcjMv/qUk+LzivQ8oZz9TheBiC86xuGweTFx9h+Tm5h6QCDUiiWk4fKbass6o/uGPLhbeWMlEfdMgGFmS+hqv1vDj8NDouySfC1p2DiCfZ4KOcjKGmXz5dYJZcAXJyxyvDHAW98OVRE0ZtqSO0Q5+vbM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770344626; c=relaxed/simple; bh=kUBfN/6q5wbGcW1m45DVYJL1n4JWDBJelkKCTGO2klY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=j7oFZ1YGH9l80V1YkILDJXmP4KFyi5RnBXg5Cg7d8GmgePoKJU5Nj17PTFGVrUPK0AC0TCZn14o2tOoqP+Unkw5NYOSwUbyJKWkVIbU784MO/G8jq5l9/KkGIOmZXoS1XXwr9Ubc9xFh8uoTwAgOgQ/LsLl90CXMTO7aCkt5NsM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=nebula-matrix.com; spf=pass smtp.mailfrom=nebula-matrix.com; arc=none smtp.client-ip=115.124.28.196 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=nebula-matrix.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nebula-matrix.com Received: from localhost.localdomain(mailfrom:illusion.wang@nebula-matrix.com fp:SMTPD_---.gQHg4i8_1770344294 cluster:ay29) by smtp.aliyun-inc.com; Fri, 06 Feb 2026 10:18:15 +0800 From: "illusion.wang" To: dimon.zhao@nebula-matrix.com, illusion.wang@nebula-matrix.com, alvin.wang@nebula-matrix.com, sam.chen@nebula-matrix.com, netdev@vger.kernel.org Cc: andrew+netdev@lunn.ch, corbet@lwn.net, kuba@kernel.org, linux-doc@vger.kernel.org, lorenzo@kernel.org, pabeni@redhat.com, horms@kernel.org, vadim.fedorenko@linux.dev, lukas.bulwahn@redhat.com, edumazet@google.com, linux-kernel@vger.kernel.org (open list) Subject: [PATCH v4 net-next 04/11] net/nebula-matrix: channel msg value and msg struct Date: Fri, 6 Feb 2026 10:15:56 +0800 Message-ID: <20260206021608.85381-5-illusion.wang@nebula-matrix.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260206021608.85381-1-illusion.wang@nebula-matrix.com> References: <20260206021608.85381-1-illusion.wang@nebula-matrix.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For compatibility, the msg id value is fixed, and each msg struct can only have fields added (not removed). Signed-off-by: illusion.wang --- .../nbl/nbl_include/nbl_def_channel.h | 249 ++++++++++++++++++ 1 file changed, 249 insertions(+) diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_cha= nnel.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_channel= .h index d87c9c5416d2..975924781fe6 100644 --- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_channel.h +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_channel.h @@ -10,6 +10,255 @@ #include #include "nbl_include.h" =20 +enum nbl_chan_msg_type { + NBL_CHAN_MSG_ACK, + NBL_CHAN_MSG_ADD_MACVLAN, + NBL_CHAN_MSG_DEL_MACVLAN, + NBL_CHAN_MSG_ADD_MULTI_RULE, + NBL_CHAN_MSG_DEL_MULTI_RULE, + NBL_CHAN_MSG_SETUP_MULTI_GROUP, + NBL_CHAN_MSG_REMOVE_MULTI_GROUP, + NBL_CHAN_MSG_REGISTER_NET, + NBL_CHAN_MSG_UNREGISTER_NET, + NBL_CHAN_MSG_ALLOC_TXRX_QUEUES, + NBL_CHAN_MSG_FREE_TXRX_QUEUES, + NBL_CHAN_MSG_SETUP_QUEUE, + NBL_CHAN_MSG_REMOVE_ALL_QUEUES, + NBL_CHAN_MSG_CFG_DSCH, + NBL_CHAN_MSG_SETUP_CQS, + NBL_CHAN_MSG_REMOVE_CQS, + NBL_CHAN_MSG_CFG_QDISC_MQPRIO, + NBL_CHAN_MSG_CONFIGURE_MSIX_MAP, + NBL_CHAN_MSG_DESTROY_MSIX_MAP, + NBL_CHAN_MSG_MAILBOX_ENABLE_IRQ, + NBL_CHAN_MSG_GET_GLOBAL_VECTOR, + NBL_CHAN_MSG_GET_VSI_ID, + NBL_CHAN_MSG_SET_PROSISC_MODE, + NBL_CHAN_MSG_GET_FIRMWARE_VERSION, + NBL_CHAN_MSG_GET_QUEUE_ERR_STATS, + NBL_CHAN_MSG_GET_COALESCE, + NBL_CHAN_MSG_SET_COALESCE, + NBL_CHAN_MSG_SET_SPOOF_CHECK_ADDR, + NBL_CHAN_MSG_SET_VF_SPOOF_CHECK, + NBL_CHAN_MSG_GET_RXFH_INDIR_SIZE, + NBL_CHAN_MSG_GET_RXFH_INDIR, + NBL_CHAN_MSG_GET_RXFH_RSS_KEY, + NBL_CHAN_MSG_GET_RXFH_RSS_ALG_SEL, + NBL_CHAN_MSG_GET_HW_CAPS, + NBL_CHAN_MSG_GET_HW_STATE, + NBL_CHAN_MSG_REGISTER_RDMA, + NBL_CHAN_MSG_UNREGISTER_RDMA, + NBL_CHAN_MSG_GET_REAL_HW_ADDR, + NBL_CHAN_MSG_GET_REAL_BDF, + NBL_CHAN_MSG_GRC_PROCESS, + NBL_CHAN_MSG_SET_SFP_STATE, + NBL_CHAN_MSG_SET_ETH_LOOPBACK, + NBL_CHAN_MSG_CHECK_ACTIVE_VF, + NBL_CHAN_MSG_GET_PRODUCT_FLEX_CAP, + NBL_CHAN_MSG_ALLOC_KTLS_TX_INDEX, + NBL_CHAN_MSG_FREE_KTLS_TX_INDEX, + NBL_CHAN_MSG_CFG_KTLS_TX_KEYMAT, + NBL_CHAN_MSG_ALLOC_KTLS_RX_INDEX, + NBL_CHAN_MSG_FREE_KTLS_RX_INDEX, + NBL_CHAN_MSG_CFG_KTLS_RX_KEYMAT, + NBL_CHAN_MSG_CFG_KTLS_RX_RECORD, + NBL_CHAN_MSG_ADD_KTLS_RX_FLOW, + NBL_CHAN_MSG_DEL_KTLS_RX_FLOW, + NBL_CHAN_MSG_ALLOC_IPSEC_TX_INDEX, + NBL_CHAN_MSG_FREE_IPSEC_TX_INDEX, + NBL_CHAN_MSG_ALLOC_IPSEC_RX_INDEX, + NBL_CHAN_MSG_FREE_IPSEC_RX_INDEX, + NBL_CHAN_MSG_CFG_IPSEC_TX_SAD, + NBL_CHAN_MSG_CFG_IPSEC_RX_SAD, + NBL_CHAN_MSG_ADD_IPSEC_TX_FLOW, + NBL_CHAN_MSG_DEL_IPSEC_TX_FLOW, + NBL_CHAN_MSG_ADD_IPSEC_RX_FLOW, + NBL_CHAN_MSG_DEL_IPSEC_RX_FLOW, + NBL_CHAN_MSG_NOTIFY_IPSEC_HARD_EXPIRE, + NBL_CHAN_MSG_GET_MBX_IRQ_NUM, + NBL_CHAN_MSG_CLEAR_FLOW, + NBL_CHAN_MSG_CLEAR_QUEUE, + NBL_CHAN_MSG_GET_ETH_ID, + NBL_CHAN_MSG_SET_OFFLOAD_STATUS, + NBL_CHAN_MSG_INIT_OFLD, + NBL_CHAN_MSG_INIT_CMDQ, + NBL_CHAN_MSG_DESTROY_CMDQ, + NBL_CHAN_MSG_RESET_CMDQ, + NBL_CHAN_MSG_INIT_FLOW, + NBL_CHAN_MSG_DEINIT_FLOW, + NBL_CHAN_MSG_OFFLOAD_FLOW_RULE, + NBL_CHAN_MSG_GET_ACL_SWITCH, + NBL_CHAN_MSG_GET_VSI_GLOBAL_QUEUE_ID, + NBL_CHAN_MSG_INIT_REP, + NBL_CHAN_MSG_GET_LINE_RATE_INFO, + NBL_CHAN_MSG_REGISTER_NET_REP, + NBL_CHAN_MSG_UNREGISTER_NET_REP, + NBL_CHAN_MSG_REGISTER_ETH_REP, + NBL_CHAN_MSG_UNREGISTER_ETH_REP, + NBL_CHAN_MSG_REGISTER_UPCALL_PORT, + NBL_CHAN_MSG_UNREGISTER_UPCALL_PORT, + NBL_CHAN_MSG_GET_PORT_STATE, + NBL_CHAN_MSG_SET_PORT_ADVERTISING, + NBL_CHAN_MSG_GET_MODULE_INFO, + NBL_CHAN_MSG_GET_MODULE_EEPROM, + NBL_CHAN_MSG_GET_LINK_STATE, + NBL_CHAN_MSG_NOTIFY_LINK_STATE, + NBL_CHAN_MSG_GET_QUEUE_CXT, + NBL_CHAN_MSG_CFG_LOG, + NBL_CHAN_MSG_INIT_VDPAQ, + NBL_CHAN_MSG_DESTROY_VDPAQ, + NBL_CHAN_GET_UPCALL_PORT, + NBL_CHAN_MSG_NOTIFY_ETH_REP_LINK_STATE, + NBL_CHAN_MSG_SET_ETH_MAC_ADDR, + NBL_CHAN_MSG_GET_FUNCTION_ID, + NBL_CHAN_MSG_GET_CHIP_TEMPERATURE, + NBL_CHAN_MSG_DISABLE_HW_FLOW, + NBL_CHAN_MSG_ENABLE_HW_FLOW, + NBL_CHAN_MSG_SET_UPCALL_RULE, + NBL_CHAN_MSG_UNSET_UPCALL_RULE, + NBL_CHAN_MSG_GET_REG_DUMP, + NBL_CHAN_MSG_GET_REG_DUMP_LEN, + NBL_CHAN_MSG_CFG_LAG_HASH_ALGORITHM, + NBL_CHAN_MSG_CFG_LAG_MEMBER_FWD, + NBL_CHAN_MSG_CFG_LAG_MEMBER_LIST, + NBL_CHAN_MSG_CFG_LAG_MEMBER_UP_ATTR, + NBL_CHAN_MSG_ADD_LAG_FLOW, + NBL_CHAN_MSG_DEL_LAG_FLOW, + NBL_CHAN_MSG_SWITCHDEV_INIT_CMDQ, + NBL_CHAN_MSG_SWITCHDEV_DEINIT_CMDQ, + NBL_CHAN_MSG_SET_TC_FLOW_INFO, + NBL_CHAN_MSG_UNSET_TC_FLOW_INFO, + NBL_CHAN_MSG_INIT_ACL, + NBL_CHAN_MSG_UNINIT_ACL, + NBL_CHAN_MSG_CFG_LAG_MCC, + NBL_CHAN_MSG_REGISTER_VSI2Q, + NBL_CHAN_MSG_SETUP_Q2VSI, + NBL_CHAN_MSG_REMOVE_Q2VSI, + NBL_CHAN_MSG_SETUP_RSS, + NBL_CHAN_MSG_REMOVE_RSS, + NBL_CHAN_MSG_GET_REP_QUEUE_INFO, + NBL_CHAN_MSG_CTRL_PORT_LED, + NBL_CHAN_MSG_NWAY_RESET, + NBL_CHAN_MSG_SET_INTL_SUPPRESS_LEVEL, + NBL_CHAN_MSG_GET_ETH_STATS, + NBL_CHAN_MSG_GET_MODULE_TEMPERATURE, + NBL_CHAN_MSG_GET_BOARD_INFO, + NBL_CHAN_MSG_GET_P4_USED, + NBL_CHAN_MSG_GET_VF_BASE_VSI_ID, + NBL_CHAN_MSG_ADD_LLDP_FLOW, + NBL_CHAN_MSG_DEL_LLDP_FLOW, + NBL_CHAN_MSG_CFG_ETH_BOND_INFO, + NBL_CHAN_MSG_CFG_DUPPKT_MCC, + NBL_CHAN_MSG_ADD_ND_UPCALL_FLOW, + NBL_CHAN_MSG_DEL_ND_UPCALL_FLOW, + NBL_CHAN_MSG_GET_BOARD_ID, + NBL_CHAN_MSG_SET_SHAPING_DPORT_VLD, + NBL_CHAN_MSG_SET_DPORT_FC_TH_VLD, + NBL_CHAN_MSG_REGISTER_RDMA_BOND, + NBL_CHAN_MSG_UNREGISTER_RDMA_BOND, + NBL_CHAN_MSG_RESTORE_NETDEV_QUEUE, + NBL_CHAN_MSG_RESTART_NETDEV_QUEUE, + NBL_CHAN_MSG_RESTORE_HW_QUEUE, + NBL_CHAN_MSG_KEEP_ALIVE, + NBL_CHAN_MSG_GET_BASE_MAC_ADDR, + NBL_CHAN_MSG_CFG_BOND_SHAPING, + NBL_CHAN_MSG_CFG_BGID_BACK_PRESSURE, + NBL_CHAN_MSG_ALLOC_KT_BLOCK, + NBL_CHAN_MSG_FREE_KT_BLOCK, + NBL_CHAN_MSG_GET_USER_QUEUE_INFO, + NBL_CHAN_MSG_GET_ETH_BOND_INFO, + NBL_CHAN_MSG_CLEAR_ACCEL_FLOW, + NBL_CHAN_MSG_SET_BRIDGE_MODE, + NBL_CHAN_MSG_GET_VF_FUNCTION_ID, + NBL_CHAN_MSG_NOTIFY_LINK_FORCED, + NBL_CHAN_MSG_SET_PMD_DEBUG, + NBL_CHAN_MSG_REGISTER_FUNC_MAC, + NBL_CHAN_MSG_SET_TX_RATE, + NBL_CHAN_MSG_REGISTER_FUNC_LINK_FORCED, + NBL_CHAN_MSG_GET_LINK_FORCED, + NBL_CHAN_MSG_REGISTER_FUNC_VLAN, + NBL_CHAN_MSG_GET_FD_FLOW, + NBL_CHAN_MSG_GET_FD_FLOW_CNT, + NBL_CHAN_MSG_GET_FD_FLOW_ALL, + NBL_CHAN_MSG_GET_FD_FLOW_MAX, + NBL_CHAN_MSG_REPLACE_FD_FLOW, + NBL_CHAN_MSG_REMOVE_FD_FLOW, + NBL_CHAN_MSG_CFG_FD_FLOW_STATE, + NBL_CHAN_MSG_REGISTER_FUNC_RATE, + NBL_CHAN_MSG_NOTIFY_VLAN, + NBL_CHAN_MSG_GET_XDP_QUEUE_INFO, + NBL_CHAN_MSG_STOP_ABNORMAL_SW_QUEUE, + NBL_CHAN_MSG_STOP_ABNORMAL_HW_QUEUE, + NBL_CHAN_MSG_NOTIFY_RESET_EVENT, + NBL_CHAN_MSG_ACK_RESET_EVENT, + NBL_CHAN_MSG_GET_VF_VSI_ID, + NBL_CHAN_MSG_CONFIGURE_QOS, + NBL_CHAN_MSG_GET_PFC_BUFFER_SIZE, + NBL_CHAN_MSG_SET_PFC_BUFFER_SIZE, + NBL_CHAN_MSG_GET_VF_STATS, + NBL_CHAN_MSG_REGISTER_FUNC_TRUST, + NBL_CHAN_MSG_NOTIFY_TRUST, + NBL_CHAN_CHECK_VF_IS_ACTIVE, + NBL_CHAN_MSG_GET_ETH_ABNORMAL_STATS, + NBL_CHAN_MSG_GET_ETH_CTRL_STATS, + NBL_CHAN_MSG_GET_PAUSE_STATS, + NBL_CHAN_MSG_GET_ETH_MAC_STATS, + NBL_CHAN_MSG_GET_FEC_STATS, + NBL_CHAN_MSG_CFG_MULTI_MCAST_RULE, + NBL_CHAN_MSG_GET_LINK_DOWN_COUNT, + NBL_CHAN_MSG_GET_LINK_STATUS_OPCODE, + NBL_CHAN_MSG_GET_RMON_STATS, + NBL_CHAN_MSG_REGISTER_PF_NAME, + NBL_CHAN_MSG_GET_PF_NAME, + NBL_CHAN_MSG_CONFIGURE_RDMA_BW, + NBL_CHAN_MSG_SET_RATE_LIMIT, + NBL_CHAN_MSG_SET_TC_WGT, + NBL_CHAN_MSG_REMOVE_QUEUE, + NBL_CHAN_MSG_GET_MIRROR_TABLE_ID, + NBL_CHAN_MSG_CONFIGURE_MIRROR, + NBL_CHAN_MSG_CONFIGURE_MIRROR_TABLE, + NBL_CHAN_MSG_CLEAR_MIRROR_CFG, + NBL_CHAN_MSG_MIRROR_OUTPUTPORT_NOTIFY, + NBL_CHAN_MSG_CHECK_FLOWTABLE_SPEC, + NBL_CHAN_CHECK_VF_IS_VDPA, + NBL_CHAN_MSG_GET_VDPA_VF_STATS, + NBL_CHAN_MSG_SET_RX_RATE, + NBL_CHAN_GET_UVN_PKT_DROP_STATS, + NBL_CHAN_GET_USTORE_PKT_DROP_STATS, + NBL_CHAN_GET_USTORE_TOTAL_PKT_DROP_STATS, + NBL_CHAN_MSG_SET_WOL, + NBL_CHAN_MSG_INIT_VF_MSIX_MAP, + NBL_CHAN_MSG_GET_ST_NAME, + NBL_CHAN_MSG_MTU_SET =3D 501, + NBL_CHAN_MSG_SET_RXFH_INDIR =3D 506, + NBL_CHAN_MSG_SET_RXFH_RSS_ALG_SEL =3D 508, + /* mailbox msg end */ + NBL_CHAN_MSG_MAILBOX_MAX, +}; + +struct nbl_chan_param_cfg_msix_map { + u16 num_net_msix; + u16 num_others_msix; + u16 msix_mask_en; +}; + +struct nbl_chan_param_enable_mailbox_irq { + u16 vector_id; + bool enable_msix; +}; + +struct nbl_chan_param_get_vsi_id { + u16 vsi_id; + u16 type; +}; + +struct nbl_chan_param_get_eth_id { + u16 vsi_id; + u8 eth_mode; + u8 eth_id; + u8 logic_eth_id; +}; + enum nbl_channel_type { NBL_CHAN_TYPE_MAILBOX, NBL_CHAN_TYPE_MAX --=20 2.47.3 From nobody Sun Feb 8 00:11:39 2026 Received: from out198-19.us.a.mail.aliyun.com (out198-19.us.a.mail.aliyun.com [47.90.198.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6898B273F9; Fri, 6 Feb 2026 02:18:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=47.90.198.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770344317; cv=none; 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localhost.localdomain(mailfrom:illusion.wang@nebula-matrix.com fp:SMTPD_---.gQHg4jl_1770344295 cluster:ay29) by smtp.aliyun-inc.com; Fri, 06 Feb 2026 10:18:16 +0800 From: "illusion.wang" To: dimon.zhao@nebula-matrix.com, illusion.wang@nebula-matrix.com, alvin.wang@nebula-matrix.com, sam.chen@nebula-matrix.com, netdev@vger.kernel.org Cc: andrew+netdev@lunn.ch, corbet@lwn.net, kuba@kernel.org, linux-doc@vger.kernel.org, lorenzo@kernel.org, pabeni@redhat.com, horms@kernel.org, vadim.fedorenko@linux.dev, lukas.bulwahn@redhat.com, edumazet@google.com, linux-kernel@vger.kernel.org (open list) Subject: [PATCH v4 net-next 05/11] net/nebula-matrix: add channel layer Date: Fri, 6 Feb 2026 10:15:57 +0800 Message-ID: <20260206021608.85381-6-illusion.wang@nebula-matrix.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260206021608.85381-1-illusion.wang@nebula-matrix.com> References: <20260206021608.85381-1-illusion.wang@nebula-matrix.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" a channel management layer provides structured approach to handle communication between different components and drivers. Here's a summary of its key functionalities: 1. Message Handling Framework Message Registration/Unregistration: Functions (nbl_chan_register_msg, nbl_chan_unregister_msg) allow dynamic registration of message handlers for specific message types, enabling extensible communication protocols. Message Sending/Acknowledgment: Core functions (nbl_chan_send_msg, nbl_chan_send_ack) handle message transmission, including asynchronous operations with acknowledgment (ACK) support. Received ACKs are processed via nbl_chan_recv_ack_msg. Hash-Based Handler Lookup: A hash table (handle_hash_tbl) stores message handlers for efficient O(1) lookup by message type. 2. Channel Types and Queue Management Mailbox Channel: For direct communication between PF0 and Other PF. Queue Initialization/Teardown: Functions (nbl_chan_init_queue, nbl_chan_teardown_queue) manage transmit (TX) and receive (RX) queues. Queue Configuration: Hardware-specific queue parameters (e.g., buffer sizes, entry counts) are set via nbl_chan_config_queue, with hardware interactions delegated to hw_ops. 3. Hardware Abstraction Layer (HW Ops) Hardware-Specific Operations: The nbl_hw_ops structure abstracts hardware interactions: queue configuration (config_mailbox_txq/rxq), tail pointer updates(update_mailbox_queue_tail_ptr). Signed-off-by: illusion.wang --- .../net/ethernet/nebula-matrix/nbl/Makefile | 3 +- .../nbl/nbl_channel/nbl_channel.c | 790 ++++++++++++++++++ .../nbl/nbl_channel/nbl_channel.h | 122 +++ .../nebula-matrix/nbl/nbl_common/nbl_common.c | 227 +++++ .../nebula-matrix/nbl/nbl_common/nbl_common.h | 28 + .../nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.c | 101 +++ .../nbl/nbl_include/nbl_def_channel.h | 88 ++ .../nbl/nbl_include/nbl_def_common.h | 73 ++ .../nbl/nbl_include/nbl_def_hw.h | 26 + .../nbl/nbl_include/nbl_include.h | 7 +- 10 files changed, 1463 insertions(+), 2 deletions(-) create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_common/nbl_c= ommon.c create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_common/nbl_c= ommon.h diff --git a/drivers/net/ethernet/nebula-matrix/nbl/Makefile b/drivers/net/= ethernet/nebula-matrix/nbl/Makefile index c88c49dafa0d..b93d21a99e99 100644 --- a/drivers/net/ethernet/nebula-matrix/nbl/Makefile +++ b/drivers/net/ethernet/nebula-matrix/nbl/Makefile @@ -4,7 +4,8 @@ =20 obj-$(CONFIG_NBL_CORE) :=3D nbl_core.o =20 -nbl_core-objs +=3D nbl_channel/nbl_channel.o \ +nbl_core-objs +=3D nbl_common/nbl_common.o \ + nbl_channel/nbl_channel.o \ nbl_hw/nbl_hw_leonis/nbl_hw_leonis.o \ nbl_hw/nbl_hw_leonis/nbl_resource_leonis.o \ nbl_hw/nbl_hw_leonis/nbl_hw_leonis_regs.o \ diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_channel/nbl_channel= .c b/drivers/net/ethernet/nebula-matrix/nbl/nbl_channel/nbl_channel.c index 9fc67700c581..a9cfc3295839 100644 --- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_channel/nbl_channel.c +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_channel/nbl_channel.c @@ -6,7 +6,765 @@ #include #include "nbl_channel.h" =20 +static void nbl_chan_delete_msg_handler(struct nbl_channel_mgt *chan_mgt, + u16 msg_type) +{ + u8 chan_type =3D NBL_CHAN_TYPE_MAILBOX; + struct nbl_chan_info *chan_info; + + nbl_common_free_hash_node(chan_mgt->handle_hash_tbl, &msg_type); + chan_info =3D NBL_CHAN_MGT_TO_CHAN_INFO(chan_mgt, chan_type); + if (chan_info && chan_info->clean_task) + flush_work(chan_info->clean_task); +} + +static int nbl_chan_add_msg_handler(struct nbl_channel_mgt *chan_mgt, + u16 msg_type, nbl_chan_resp func, + void *priv) +{ + struct nbl_chan_msg_node_data handler =3D { 0 }; + int ret; + + handler.func =3D func; + handler.priv =3D priv; + ret =3D nbl_common_alloc_hash_node(chan_mgt->handle_hash_tbl, &msg_type, + &handler, NULL); + + return ret; +} + +static int nbl_chan_init_msg_handler(struct nbl_channel_mgt *chan_mgt) +{ + struct nbl_common_info *common =3D chan_mgt->common; + struct nbl_hash_tbl_key tbl_key; + int ret =3D 0; + + NBL_HASH_TBL_KEY_INIT(&tbl_key, common->dev, sizeof(u16), + sizeof(struct nbl_chan_msg_node_data), + NBL_CHAN_HANDLER_TBL_BUCKET_SIZE); + + chan_mgt->handle_hash_tbl =3D nbl_common_init_hash_table(&tbl_key); + if (!chan_mgt->handle_hash_tbl) { + ret =3D -ENOMEM; + goto alloc_hashtbl_failed; + } + + return 0; + +alloc_hashtbl_failed: + return ret; +} + +static void nbl_chan_remove_msg_handler(struct nbl_channel_mgt *chan_mgt) +{ + nbl_common_remove_hash_table(chan_mgt->handle_hash_tbl, NULL); + + chan_mgt->handle_hash_tbl =3D NULL; +} + +static void nbl_chan_init_queue_param(struct nbl_chan_info *chan_info, + u16 num_txq_entries, u16 num_rxq_entries, + u16 txq_buf_size, u16 rxq_buf_size) +{ + spin_lock_init(&chan_info->txq_lock); + chan_info->num_txq_entries =3D num_txq_entries; + chan_info->num_rxq_entries =3D num_rxq_entries; + chan_info->txq_buf_size =3D txq_buf_size; + chan_info->rxq_buf_size =3D rxq_buf_size; +} + +static int nbl_chan_init_tx_queue(struct nbl_common_info *common, + struct nbl_chan_info *chan_info) +{ + struct nbl_chan_ring *txq =3D &chan_info->txq; + struct device *dev =3D common->dev; + size_t size =3D + chan_info->num_txq_entries * sizeof(struct nbl_chan_tx_desc); + + txq->desc =3D dmam_alloc_coherent(dev, size, &txq->dma, + GFP_KERNEL | __GFP_ZERO); + if (!txq->desc) + return -ENOMEM; + + chan_info->wait =3D devm_kcalloc(dev, chan_info->num_txq_entries, + sizeof(struct nbl_chan_waitqueue_head), + GFP_KERNEL); + if (!chan_info->wait) + goto req_wait_queue_failed; + + txq->buf =3D devm_kcalloc(dev, chan_info->num_txq_entries, + sizeof(struct nbl_chan_buf), GFP_KERNEL); + if (!txq->buf) + goto req_num_txq_entries; + + return 0; + +req_num_txq_entries: +req_wait_queue_failed: + return -ENOMEM; +} + +static int nbl_chan_init_rx_queue(struct nbl_common_info *common, + struct nbl_chan_info *chan_info) +{ + struct nbl_chan_ring *rxq =3D &chan_info->rxq; + struct device *dev =3D common->dev; + size_t size =3D + chan_info->num_rxq_entries * sizeof(struct nbl_chan_rx_desc); + + rxq->desc =3D dmam_alloc_coherent(dev, size, &rxq->dma, + GFP_KERNEL | __GFP_ZERO); + if (!rxq->desc) { + dev_err(dev, + "Allocate DMA for chan rx descriptor ring failed\n"); + return -ENOMEM; + } + + rxq->buf =3D devm_kcalloc(dev, chan_info->num_rxq_entries, + sizeof(struct nbl_chan_buf), GFP_KERNEL); + if (!rxq->buf) + return -ENOMEM; + + return 0; +} + +static int nbl_chan_init_queue(struct nbl_common_info *common, + struct nbl_chan_info *chan_info) +{ + int err; + + err =3D nbl_chan_init_tx_queue(common, chan_info); + if (err) + return err; + + err =3D nbl_chan_init_rx_queue(common, chan_info); + if (err) + goto setup_rx_queue_err; + + return 0; + +setup_rx_queue_err: + return err; +} + +static void nbl_chan_config_queue(struct nbl_channel_mgt *chan_mgt, + struct nbl_chan_info *chan_info, bool tx) +{ + struct nbl_hw_ops *hw_ops =3D chan_mgt->hw_ops_tbl->ops; + struct nbl_hw_mgt *p =3D chan_mgt->hw_ops_tbl->priv; + int size_bwid =3D ilog2(chan_info->num_rxq_entries); + struct nbl_chan_ring *ring; + dma_addr_t dma_addr; + + if (tx) + ring =3D &chan_info->txq; + else + ring =3D &chan_info->rxq; + dma_addr =3D ring->dma; + if (tx) + hw_ops->config_mailbox_txq(p, dma_addr, size_bwid); + else + hw_ops->config_mailbox_rxq(p, dma_addr, size_bwid); +} + +static int nbl_chan_alloc_all_tx_bufs(struct nbl_channel_mgt *chan_mgt, + struct nbl_chan_info *chan_info) +{ + struct nbl_chan_ring *txq =3D &chan_info->txq; + struct device *dev =3D chan_mgt->common->dev; + struct nbl_chan_buf *buf; + u16 i; + + for (i =3D 0; i < chan_info->num_txq_entries; i++) { + buf =3D &txq->buf[i]; + buf->va =3D dmam_alloc_coherent(dev, chan_info->txq_buf_size, + &buf->pa, + GFP_KERNEL | __GFP_ZERO); + if (!buf->va) { + dev_err(dev, + "Allocate buffer for chan tx queue failed\n"); + goto err; + } + } + + txq->next_to_clean =3D 0; + txq->next_to_use =3D 0; + txq->tail_ptr =3D 0; + + return 0; +err: + return -ENOMEM; +} + +static int +nbl_chan_cfg_mailbox_qinfo_map_table(struct nbl_channel_mgt *chan_mgt) +{ + struct nbl_hw_ops *hw_ops =3D chan_mgt->hw_ops_tbl->ops; + struct nbl_common_info *common =3D chan_mgt->common; + struct nbl_hw_mgt *p =3D chan_mgt->hw_ops_tbl->priv; + u16 func_id; + u32 pf_mask; + + pf_mask =3D hw_ops->get_host_pf_mask(p); + for (func_id =3D 0; func_id < NBL_MAX_PF; func_id++) { + if (!(pf_mask & (1 << func_id))) + hw_ops->cfg_mailbox_qinfo(p, func_id, common->hw_bus, + common->devid, + common->function + func_id); + } + + return 0; +} + +static int nbl_chan_cfg_qinfo_map_table(struct nbl_channel_mgt *chan_mgt, + u8 chan_type) +{ + return nbl_chan_cfg_mailbox_qinfo_map_table(chan_mgt); +} + +#define NBL_UPDATE_QUEUE_TAIL_PTR(chan_info, hw_ops, chan_mgt, tail_ptr, q= id)\ +do { \ + (void)(chan_info); \ + typeof(hw_ops) _hw_ops =3D (hw_ops); \ + typeof(chan_mgt) _chan_mgt =3D (chan_mgt); \ + typeof(tail_ptr) _tail_ptr =3D (tail_ptr); \ + typeof(qid) _qid =3D (qid); \ + (_hw_ops)->update_mailbox_queue_tail_ptr( \ + _chan_mgt->hw_ops_tbl->priv, _tail_ptr, _qid); \ +} while (0) + +static int nbl_chan_alloc_all_rx_bufs(struct nbl_channel_mgt *chan_mgt, + struct nbl_chan_info *chan_info) +{ + struct nbl_hw_ops *hw_ops =3D chan_mgt->hw_ops_tbl->ops; + struct nbl_chan_ring *rxq =3D &chan_info->rxq; + struct device *dev =3D chan_mgt->common->dev; + struct nbl_chan_rx_desc *desc; + struct nbl_chan_buf *buf; + u32 retry_times =3D 0; + u16 i; + + for (i =3D 0; i < chan_info->num_rxq_entries; i++) { + buf =3D &rxq->buf[i]; + buf->va =3D dmam_alloc_coherent(dev, chan_info->rxq_buf_size, + &buf->pa, + GFP_KERNEL | __GFP_ZERO); + if (!buf->va) { + dev_err(dev, + "Allocate buffer for chan rx queue failed\n"); + goto err; + } + } + + desc =3D rxq->desc; + for (i =3D 0; i < chan_info->num_rxq_entries - 1; i++) { + buf =3D &rxq->buf[i]; + desc[i].flags =3D NBL_CHAN_RX_DESC_AVAIL; + desc[i].buf_addr =3D buf->pa; + desc[i].buf_len =3D chan_info->rxq_buf_size; + } + + rxq->next_to_clean =3D 0; + rxq->next_to_use =3D chan_info->num_rxq_entries - 1; + rxq->tail_ptr =3D chan_info->num_rxq_entries - 1; + + /* mb for notify */ + mb(); + + NBL_UPDATE_QUEUE_TAIL_PTR(chan_info, hw_ops, chan_mgt, rxq->tail_ptr, + NBL_MB_RX_QID); + + for (retry_times =3D 0; retry_times < 3; retry_times++) { + NBL_UPDATE_QUEUE_TAIL_PTR(chan_info, hw_ops, chan_mgt, + rxq->tail_ptr, NBL_MB_RX_QID); + usleep_range(NBL_CHAN_TX_WAIT_US * 50, + NBL_CHAN_TX_WAIT_US * 60); + } + + return 0; +err: + return -ENOMEM; +} + +static int nbl_chan_alloc_all_bufs(struct nbl_channel_mgt *chan_mgt, + struct nbl_chan_info *chan_info) +{ + int err; + + err =3D nbl_chan_alloc_all_tx_bufs(chan_mgt, chan_info); + if (err) + return err; + err =3D nbl_chan_alloc_all_rx_bufs(chan_mgt, chan_info); + if (err) + goto alloc_rx_bufs_err; + + return 0; + +alloc_rx_bufs_err: + return err; +} + +static void nbl_chan_stop_queue(struct nbl_channel_mgt *chan_mgt, + struct nbl_chan_info *chan_info) +{ + struct nbl_hw_ops *hw_ops =3D chan_mgt->hw_ops_tbl->ops; + + hw_ops->stop_mailbox_rxq(chan_mgt->hw_ops_tbl->priv); + hw_ops->stop_mailbox_txq(chan_mgt->hw_ops_tbl->priv); +} + +static int nbl_chan_teardown_queue(struct nbl_channel_mgt *chan_mgt, + u8 chan_type) +{ + struct nbl_chan_info *chan_info =3D + NBL_CHAN_MGT_TO_CHAN_INFO(chan_mgt, chan_type); + + nbl_chan_stop_queue(chan_mgt, chan_info); + return 0; +} + +static int nbl_chan_setup_queue(struct nbl_channel_mgt *chan_mgt, u8 chan_= type) +{ + struct nbl_common_info *common =3D chan_mgt->common; + struct nbl_chan_info *chan_info =3D + NBL_CHAN_MGT_TO_CHAN_INFO(chan_mgt, chan_type); + int err; + + nbl_chan_init_queue_param(chan_info, NBL_CHAN_QUEUE_LEN, + NBL_CHAN_QUEUE_LEN, NBL_CHAN_BUF_LEN, + NBL_CHAN_BUF_LEN); + err =3D nbl_chan_init_queue(common, chan_info); + if (err) + return err; + + nbl_chan_config_queue(chan_mgt, chan_info, true); /* tx */ + nbl_chan_config_queue(chan_mgt, chan_info, false); /* rx */ + + err =3D nbl_chan_alloc_all_bufs(chan_mgt, chan_info); + if (err) + goto chan_q_setup_fail; + + return 0; + +chan_q_setup_fail: + nbl_chan_teardown_queue(chan_mgt, chan_type); + return err; +} + +static int nbl_chan_update_txqueue(struct nbl_channel_mgt *chan_mgt, + struct nbl_chan_info *chan_info, + struct nbl_chan_tx_param *param) +{ + struct nbl_chan_ring *txq =3D &chan_info->txq; + struct nbl_chan_tx_desc *tx_desc =3D + NBL_CHAN_TX_RING_TO_DESC(txq, txq->next_to_use); + struct nbl_chan_buf *tx_buf =3D + NBL_CHAN_TX_RING_TO_BUF(txq, txq->next_to_use); + + if (param->arg_len > NBL_CHAN_BUF_LEN - sizeof(*tx_desc)) + return -EINVAL; + + tx_desc->dstid =3D param->dstid; + tx_desc->msg_type =3D param->msg_type; + tx_desc->msgid =3D param->msgid; + + if (param->arg_len > NBL_CHAN_TX_DESC_EMBEDDED_DATA_LEN) { + memcpy(tx_buf->va, param->arg, param->arg_len); + tx_desc->buf_addr =3D tx_buf->pa; + tx_desc->buf_len =3D param->arg_len; + tx_desc->data_len =3D 0; + } else { + memcpy(tx_desc->data, param->arg, param->arg_len); + tx_desc->buf_len =3D 0; + tx_desc->data_len =3D param->arg_len; + } + tx_desc->flags =3D NBL_CHAN_TX_DESC_AVAIL; + + /* wmb */ + wmb(); + txq->next_to_use =3D + NBL_NEXT_ID(txq->next_to_use, chan_info->num_txq_entries - 1); + txq->tail_ptr++; + + return 0; +} + +static int nbl_chan_kick_tx_ring(struct nbl_channel_mgt *chan_mgt, + struct nbl_chan_info *chan_info) +{ + struct nbl_hw_ops *hw_ops =3D chan_mgt->hw_ops_tbl->ops; + struct nbl_chan_ring *txq =3D &chan_info->txq; + struct device *dev =3D chan_mgt->common->dev; + struct nbl_chan_tx_desc *tx_desc; + int i =3D 0; + + /* mb for tx notify */ + mb(); + + NBL_UPDATE_QUEUE_TAIL_PTR(chan_info, hw_ops, chan_mgt, txq->tail_ptr, + NBL_MB_TX_QID); + + tx_desc =3D NBL_CHAN_TX_RING_TO_DESC(txq, txq->next_to_clean); + + while (!(tx_desc->flags & NBL_CHAN_TX_DESC_USED)) { + udelay(NBL_CHAN_TX_WAIT_US); + i++; + + if (!(i % NBL_CHAN_TX_REKICK_WAIT_TIMES)) + NBL_UPDATE_QUEUE_TAIL_PTR(chan_info, hw_ops, chan_mgt, + txq->tail_ptr, NBL_MB_TX_QID); + + if (i =3D=3D NBL_CHAN_TX_WAIT_TIMES) { + dev_err(dev, "chan send message type: %d timeout\n", + tx_desc->msg_type); + return -EAGAIN; + } + } + + txq->next_to_clean =3D txq->next_to_use; + return 0; +} + +static void nbl_chan_recv_ack_msg(void *priv, u16 srcid, u16 msgid, void *= data, + u32 data_len) +{ + struct nbl_channel_mgt *chan_mgt =3D (struct nbl_channel_mgt *)priv; + struct nbl_chan_info *chan_info =3D NBL_CHAN_MGT_TO_MBX(chan_mgt); + struct nbl_chan_waitqueue_head *wait_head =3D NULL; + union nbl_chan_msg_id ack_msgid =3D { { 0 } }; + u32 *payload =3D (u32 *)data; + u32 ack_datalen =3D 0; + u32 copy_len =3D 0; + + ack_datalen =3D data_len - 3 * sizeof(u32); + ack_msgid.id =3D *(u16 *)(payload + 1); + wait_head =3D &chan_info->wait[ack_msgid.info.loc]; + wait_head->ack_err =3D *(payload + 2); + + copy_len =3D min_t(u32, wait_head->ack_data_len, ack_datalen); + if (wait_head->ack_err >=3D 0 && copy_len > 0) + memcpy((char *)wait_head->ack_data, payload + 3, copy_len); + wait_head->ack_data_len =3D (u16)copy_len; + + /* wmb */ + wmb(); + wait_head->acked =3D 1; + if (wait_head->need_waked) + wake_up(&wait_head->wait_queue); +} + +static void nbl_chan_recv_msg(struct nbl_channel_mgt *chan_mgt, void *data, + u32 data_len) +{ + struct device *dev =3D chan_mgt->common->dev; + struct nbl_chan_msg_node_data *msg_handler; + u16 msg_type, payload_len, srcid, msgid; + struct nbl_chan_tx_desc *tx_desc; + void *payload; + + tx_desc =3D data; + msg_type =3D tx_desc->msg_type; + dev_dbg(dev, "recv msg_type: %d\n", tx_desc->msg_type); + + srcid =3D tx_desc->srcid; + msgid =3D tx_desc->msgid; + if (msg_type >=3D NBL_CHAN_MSG_MAILBOX_MAX) + return; + + if (tx_desc->data_len) { + payload =3D (void *)tx_desc->data; + payload_len =3D tx_desc->data_len; + } else { + payload =3D (void *)(tx_desc + 1); + payload_len =3D tx_desc->buf_len; + } + + msg_handler =3D + nbl_common_get_hash_node(chan_mgt->handle_hash_tbl, &msg_type); + if (msg_handler) { + msg_handler->func(msg_handler->priv, srcid, msgid, payload, + payload_len); + return; + } +} + +static void nbl_chan_advance_rx_ring(struct nbl_channel_mgt *chan_mgt, + struct nbl_chan_info *chan_info, + struct nbl_chan_ring *rxq) +{ + struct nbl_hw_ops *hw_ops =3D chan_mgt->hw_ops_tbl->ops; + struct nbl_chan_rx_desc *rx_desc; + struct nbl_chan_buf *rx_buf; + u16 next_to_use; + + next_to_use =3D rxq->next_to_use; + rx_desc =3D NBL_CHAN_RX_RING_TO_DESC(rxq, next_to_use); + rx_buf =3D NBL_CHAN_RX_RING_TO_BUF(rxq, next_to_use); + + rx_desc->flags =3D NBL_CHAN_RX_DESC_AVAIL; + rx_desc->buf_addr =3D rx_buf->pa; + rx_desc->buf_len =3D chan_info->rxq_buf_size; + + /* wmb */ + wmb(); + rxq->next_to_use++; + if (rxq->next_to_use =3D=3D chan_info->num_rxq_entries) + rxq->next_to_use =3D 0; + rxq->tail_ptr++; + + NBL_UPDATE_QUEUE_TAIL_PTR(chan_info, hw_ops, chan_mgt, rxq->tail_ptr, + NBL_MB_RX_QID); +} + +static void nbl_chan_clean_queue(struct nbl_channel_mgt *chan_mgt, + struct nbl_chan_info *chan_info) +{ + struct nbl_chan_ring *rxq =3D &chan_info->rxq; + struct device *dev =3D chan_mgt->common->dev; + struct nbl_chan_rx_desc *rx_desc; + struct nbl_chan_buf *rx_buf; + u16 next_to_clean; + + next_to_clean =3D rxq->next_to_clean; + rx_desc =3D NBL_CHAN_RX_RING_TO_DESC(rxq, next_to_clean); + rx_buf =3D NBL_CHAN_RX_RING_TO_BUF(rxq, next_to_clean); + while (rx_desc->flags & NBL_CHAN_RX_DESC_USED) { + if (!(rx_desc->flags & NBL_CHAN_RX_DESC_WRITE)) + dev_dbg(dev, + "mailbox rx flag 0x%x has no NBL_CHAN_RX_DESC_WRITE\n", + rx_desc->flags); + + dma_rmb(); + nbl_chan_recv_msg(chan_mgt, rx_buf->va, rx_desc->buf_len); + nbl_chan_advance_rx_ring(chan_mgt, chan_info, rxq); + next_to_clean++; + if (next_to_clean =3D=3D chan_info->num_rxq_entries) + next_to_clean =3D 0; + rx_desc =3D NBL_CHAN_RX_RING_TO_DESC(rxq, next_to_clean); + rx_buf =3D NBL_CHAN_RX_RING_TO_BUF(rxq, next_to_clean); + } + rxq->next_to_clean =3D next_to_clean; +} + +static void nbl_chan_clean_queue_subtask(struct nbl_channel_mgt *chan_mgt, + u8 chan_type) +{ + struct nbl_chan_info *chan_info =3D + NBL_CHAN_MGT_TO_CHAN_INFO(chan_mgt, chan_type); + + if (!test_bit(NBL_CHAN_INTERRUPT_READY, chan_info->state) || + test_bit(NBL_CHAN_RESETTING, chan_info->state)) + return; + + nbl_chan_clean_queue(chan_mgt, chan_info); +} + +static int nbl_chan_get_msg_id(struct nbl_chan_info *chan_info, + union nbl_chan_msg_id *msgid) +{ + struct nbl_chan_waitqueue_head *wait =3D NULL; + int valid_loc =3D chan_info->wait_head_index, i; + + for (i =3D 0; i < NBL_CHAN_QUEUE_LEN; i++) { + wait =3D &chan_info->wait[valid_loc]; + + if (wait->status !=3D NBL_MBX_STATUS_WAITING) { + wait->msg_index =3D NBL_NEXT_ID(wait->msg_index, + NBL_CHAN_MSG_INDEX_MAX); + msgid->info.index =3D wait->msg_index; + msgid->info.loc =3D valid_loc; + + valid_loc =3D NBL_NEXT_ID(valid_loc, + chan_info->num_txq_entries - 1); + chan_info->wait_head_index =3D valid_loc; + return 0; + } + + valid_loc =3D + NBL_NEXT_ID(valid_loc, chan_info->num_txq_entries - 1); + } + + return -ENOSPC; +} + +static int nbl_chan_send_msg(struct nbl_channel_mgt *chan_mgt, + struct nbl_chan_send_info *chan_send) +{ + struct nbl_chan_info *chan_info =3D NBL_CHAN_MGT_TO_MBX(chan_mgt); + struct nbl_common_info *common =3D chan_mgt->common; + struct nbl_chan_waitqueue_head *wait_head; + union nbl_chan_msg_id msgid =3D { { 0 } }; + struct nbl_chan_tx_param tx_param =3D { 0 }; + int i =3D NBL_CHAN_TX_WAIT_ACK_TIMES, ret; + struct device *dev =3D common->dev; + + if (test_bit(NBL_CHAN_ABNORMAL, chan_info->state)) + return -EFAULT; + + spin_lock(&chan_info->txq_lock); + + ret =3D nbl_chan_get_msg_id(chan_info, &msgid); + if (ret) { + spin_unlock(&chan_info->txq_lock); + dev_err(dev, + "Channel tx wait head full, send msgtype:%u to dstid:%u failed\n", + chan_send->msg_type, chan_send->dstid); + return ret; + } + + tx_param.msg_type =3D chan_send->msg_type; + tx_param.arg =3D chan_send->arg; + tx_param.arg_len =3D chan_send->arg_len; + tx_param.dstid =3D chan_send->dstid; + tx_param.msgid =3D msgid.id; + + ret =3D nbl_chan_update_txqueue(chan_mgt, chan_info, &tx_param); + if (ret) { + spin_unlock(&chan_info->txq_lock); + dev_err(dev, + "Channel tx queue full, send msgtype:%u to dstid:%u failed\n", + chan_send->msg_type, chan_send->dstid); + return ret; + } + + wait_head =3D &chan_info->wait[msgid.info.loc]; + init_waitqueue_head(&wait_head->wait_queue); + wait_head->acked =3D 0; + wait_head->ack_data =3D chan_send->resp; + wait_head->ack_data_len =3D chan_send->resp_len; + wait_head->msg_type =3D chan_send->msg_type; + wait_head->need_waked =3D chan_send->ack; + wait_head->msg_index =3D msgid.info.index; + wait_head->status =3D chan_send->ack ? NBL_MBX_STATUS_WAITING : + NBL_MBX_STATUS_IDLE; + + ret =3D nbl_chan_kick_tx_ring(chan_mgt, chan_info); + + spin_unlock(&chan_info->txq_lock); + + if (!chan_send->ack) + return 0; + + if (test_bit(NBL_CHAN_INTERRUPT_READY, chan_info->state)) { + ret =3D wait_event_timeout(wait_head->wait_queue, + wait_head->acked, + NBL_CHAN_ACK_WAIT_TIME); + if (!ret) { + wait_head->status =3D NBL_MBX_STATUS_TIMEOUT; + dev_err(dev, + "Channel waiting ack failed, message type: %d, msg id: %u\n", + chan_send->msg_type, msgid.id); + return -EFAULT; + } + + /* rmb for waithead ack */ + rmb(); + chan_send->ack_len =3D wait_head->ack_data_len; + wait_head->status =3D NBL_MBX_STATUS_IDLE; + return wait_head->ack_err; + } + + /*polling wait mailbox ack*/ + while (i--) { + nbl_chan_clean_queue(chan_mgt, chan_info); + + if (wait_head->acked) { + chan_send->ack_len =3D wait_head->ack_data_len; + wait_head->status =3D NBL_MBX_STATUS_IDLE; + return wait_head->ack_err; + } + usleep_range(NBL_CHAN_TX_WAIT_ACK_US_MIN, + NBL_CHAN_TX_WAIT_ACK_US_MAX); + } + + wait_head->status =3D NBL_MBX_STATUS_TIMEOUT; + dev_err(dev, + "Channel polling ack failed, message type: %d msg id: %u\n", + chan_send->msg_type, msgid.id); + return 0; +} + +static int nbl_chan_send_ack(struct nbl_channel_mgt *chan_mgt, + struct nbl_chan_ack_info *chan_ack) +{ + u32 len =3D 3 * sizeof(u32) + chan_ack->data_len; + struct nbl_chan_send_info chan_send; + u32 *tmp; + + tmp =3D kzalloc(len, GFP_ATOMIC); + if (!tmp) + return -ENOMEM; + + tmp[0] =3D chan_ack->msg_type; + tmp[1] =3D chan_ack->msgid; + tmp[2] =3D (u32)chan_ack->err; + if (chan_ack->data && chan_ack->data_len) + memcpy(&tmp[3], chan_ack->data, chan_ack->data_len); + + NBL_CHAN_SEND(chan_send, chan_ack->dstid, NBL_CHAN_MSG_ACK, tmp, len, + NULL, 0, 0); + nbl_chan_send_msg(chan_mgt, &chan_send); + kfree(tmp); + + return 0; +} + +static void nbl_chan_unregister_msg(struct nbl_channel_mgt *chan_mgt, + u16 msg_type) +{ + nbl_chan_delete_msg_handler(chan_mgt, msg_type); +} + +static int nbl_chan_register_msg(struct nbl_channel_mgt *chan_mgt, u16 msg= _type, + nbl_chan_resp func, void *callback) +{ + return nbl_chan_add_msg_handler(chan_mgt, msg_type, func, callback); +} + +static bool nbl_chan_check_queue_exist(struct nbl_channel_mgt *chan_mgt, + u8 chan_type) +{ + struct nbl_chan_info *chan_info; + + chan_info =3D NBL_CHAN_MGT_TO_CHAN_INFO(chan_mgt, chan_type); + + return chan_info ? true : false; +} + +static void nbl_chan_register_chan_task(struct nbl_channel_mgt *chan_mgt, + u8 chan_type, struct work_struct *task) +{ + struct nbl_chan_info *chan_info =3D + NBL_CHAN_MGT_TO_CHAN_INFO(chan_mgt, chan_type); + + chan_info->clean_task =3D task; +} + +static void nbl_chan_set_queue_state(struct nbl_channel_mgt *chan_mgt, + enum nbl_chan_state state, u8 chan_type, + u8 set) +{ + struct nbl_chan_info *chan_info =3D + NBL_CHAN_MGT_TO_CHAN_INFO(chan_mgt, chan_type); + + if (set) + set_bit(state, chan_info->state); + else + clear_bit(state, chan_info->state); +} + static struct nbl_channel_ops chan_ops =3D { + .send_msg =3D nbl_chan_send_msg, + .send_ack =3D nbl_chan_send_ack, + .register_msg =3D nbl_chan_register_msg, + .unregister_msg =3D nbl_chan_unregister_msg, + .cfg_chan_qinfo_map_table =3D nbl_chan_cfg_qinfo_map_table, + .check_queue_exist =3D nbl_chan_check_queue_exist, + .setup_queue =3D nbl_chan_setup_queue, + .teardown_queue =3D nbl_chan_teardown_queue, + .clean_queue_subtask =3D nbl_chan_clean_queue_subtask, + .register_chan_task =3D nbl_chan_register_chan_task, + .set_queue_state =3D nbl_chan_set_queue_state, }; =20 static int @@ -18,6 +776,7 @@ nbl_chan_setup_chan_mgt(struct nbl_adapter *adapter, struct nbl_common_info *common =3D &adapter->common; struct device *dev =3D &adapter->pdev->dev; struct nbl_chan_info *mailbox; + int ret; =20 *chan_mgt_leonis =3D devm_kzalloc(dev, sizeof(struct nbl_channel_mgt_leonis), @@ -35,16 +794,31 @@ nbl_chan_setup_chan_mgt(struct nbl_adapter *adapter, (&(*chan_mgt_leonis)->chan_mgt)->chan_info[NBL_CHAN_TYPE_MAILBOX] =3D mailbox; =20 + ret =3D nbl_chan_init_msg_handler(&(*chan_mgt_leonis)->chan_mgt); + if (ret) + goto init_chan_msg_handle; + return 0; + +init_chan_msg_handle: alloc_mailbox_fail: alloc_channel_mgt_leonis_fail: return -ENOMEM; } =20 +static void +nbl_chan_remove_chan_mgt(struct nbl_common_info *common, + struct nbl_channel_mgt_leonis **chan_mgt_leonis) +{ + nbl_chan_remove_msg_handler(&(*chan_mgt_leonis)->chan_mgt); +} + static int nbl_chan_setup_ops(struct device *dev, struct nbl_channel_ops_tbl **chan_ops_tbl, struct nbl_channel_mgt_leonis *chan_mgt) { + int ret; + *chan_ops_tbl =3D devm_kzalloc(dev, sizeof(struct nbl_channel_ops_tbl), GFP_KERNEL); if (!*chan_ops_tbl) @@ -52,7 +826,16 @@ static int nbl_chan_setup_ops(struct device *dev, =20 (*chan_ops_tbl)->ops =3D &chan_ops; (*chan_ops_tbl)->priv =3D &chan_mgt->chan_mgt; + + ret =3D nbl_chan_register_msg(&chan_mgt->chan_mgt, NBL_CHAN_MSG_ACK, + nbl_chan_recv_ack_msg, chan_mgt); + if (ret) + goto err; + return 0; + +err: + return ret; } =20 int nbl_chan_init_common(struct nbl_adapter *adap, struct nbl_init_param *= param) @@ -60,6 +843,7 @@ int nbl_chan_init_common(struct nbl_adapter *adap, struc= t nbl_init_param *param) struct nbl_channel_ops_tbl **chan_ops_tbl =3D &adap->intf.channel_ops_tbl; struct nbl_channel_mgt_leonis **chan_mgt_leonis =3D (struct nbl_channel_mgt_leonis **)&NBL_ADAP_TO_CHAN_MGT(adap); + struct nbl_common_info *common =3D &adap->common; struct device *dev =3D &adap->pdev->dev; int ret; =20 @@ -73,10 +857,16 @@ int nbl_chan_init_common(struct nbl_adapter *adap, str= uct nbl_init_param *param) return 0; =20 setup_ops_fail: + nbl_chan_remove_chan_mgt(common, chan_mgt_leonis); setup_mgt_fail: return ret; } =20 void nbl_chan_remove_common(struct nbl_adapter *adap) { + struct nbl_channel_mgt_leonis **chan_mgt_leonis =3D + (struct nbl_channel_mgt_leonis **)&NBL_ADAP_TO_CHAN_MGT(adap); + struct nbl_common_info *common =3D &adap->common; + + nbl_chan_remove_chan_mgt(common, chan_mgt_leonis); } diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_channel/nbl_channel= .h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_channel/nbl_channel.h index 717ea402b8e9..391a7ae83bf1 100644 --- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_channel/nbl_channel.h +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_channel/nbl_channel.h @@ -14,11 +14,133 @@ #define NBL_CHAN_MGT_TO_CHAN_INFO(chan_mgt, chan_type) \ ((chan_mgt)->chan_info[chan_type]) =20 +#define NBL_CHAN_TX_RING_TO_DESC(tx_ring, i) \ + (&(((struct nbl_chan_tx_desc *)((tx_ring)->desc))[i])) +#define NBL_CHAN_RX_RING_TO_DESC(rx_ring, i) \ + (&(((struct nbl_chan_rx_desc *)((rx_ring)->desc))[i])) +#define NBL_CHAN_TX_RING_TO_BUF(tx_ring, i) (&(((tx_ring)->buf)[i])) +#define NBL_CHAN_RX_RING_TO_BUF(rx_ring, i) (&(((rx_ring)->buf)[i])) + +#define NBL_CHAN_TX_WAIT_US 100 +#define NBL_CHAN_TX_REKICK_WAIT_TIMES 2000 +#define NBL_CHAN_TX_WAIT_TIMES 30000 +#define NBL_CHAN_TX_WAIT_ACK_US_MIN 100 +#define NBL_CHAN_TX_WAIT_ACK_US_MAX 120 +#define NBL_CHAN_TX_WAIT_ACK_TIMES 50000 +#define NBL_CHAN_QUEUE_LEN 256 +#define NBL_CHAN_BUF_LEN 4096 +#define NBL_CHAN_TX_DESC_EMBEDDED_DATA_LEN 16 + +#define NBL_CHAN_TX_DESC_AVAIL BIT(0) +#define NBL_CHAN_TX_DESC_USED BIT(1) +#define NBL_CHAN_RX_DESC_WRITE BIT(1) +#define NBL_CHAN_RX_DESC_AVAIL BIT(3) +#define NBL_CHAN_RX_DESC_USED BIT(4) + +#define NBL_CHAN_ACK_WAIT_TIME (3 * HZ) + +#define NBL_CHAN_HANDLER_TBL_BUCKET_SIZE 512 + +enum { + NBL_MB_RX_QID =3D 0, + NBL_MB_TX_QID =3D 1, +}; + +enum { + NBL_MBX_STATUS_IDLE =3D 0, + NBL_MBX_STATUS_WAITING, + NBL_MBX_STATUS_TIMEOUT =3D -1, +}; + +struct nbl_chan_tx_param { + enum nbl_chan_msg_type msg_type; + void *arg; + size_t arg_len; + u16 dstid; + u16 msgid; +}; + +struct nbl_chan_buf { + void *va; + dma_addr_t pa; + size_t size; +}; + +struct nbl_chan_tx_desc { + u16 flags; + u16 srcid; + u16 dstid; + u16 data_len; + u16 buf_len; + u64 buf_addr; + u16 msg_type; + u8 data[16]; + u16 msgid; + u8 rsv[26]; +} __packed; + +struct nbl_chan_rx_desc { + u16 flags; + u32 buf_len; + u16 buf_id; + u64 buf_addr; +} __packed; + +struct nbl_chan_ring { + void *desc; + struct nbl_chan_buf *buf; + u16 next_to_use; + u16 tail_ptr; + u16 next_to_clean; + dma_addr_t dma; +}; + +#define NBL_CHAN_MSG_INDEX_MAX 63 + +union nbl_chan_msg_id { + struct nbl_chan_msg_id_info { + u16 index : 6; + u16 loc : 10; + } info; + u16 id; +}; + +struct nbl_chan_waitqueue_head { + struct wait_queue_head wait_queue; + char *ack_data; + int acked; + int ack_err; + u16 ack_data_len; + u16 need_waked; + u16 msg_type; + u8 status; + u8 msg_index; +}; + struct nbl_chan_info { + struct nbl_chan_ring txq; + struct nbl_chan_ring rxq; + struct nbl_chan_waitqueue_head *wait; + /* spinlock_t */ + spinlock_t txq_lock; + struct work_struct *clean_task; + u16 wait_head_index; + u16 num_txq_entries; + u16 num_rxq_entries; + u16 txq_buf_size; + u16 rxq_buf_size; + u16 txq_reset_times; + u16 rxq_reset_times; + DECLARE_BITMAP(state, NBL_CHAN_STATE_NBITS); u8 chan_type; =20 }; =20 +struct nbl_chan_msg_node_data { + nbl_chan_resp func; + void *priv; +}; + struct nbl_channel_mgt { struct nbl_common_info *common; struct nbl_hw_ops_tbl *hw_ops_tbl; diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_common/nbl_common.c= b/drivers/net/ethernet/nebula-matrix/nbl/nbl_common/nbl_common.c new file mode 100644 index 000000000000..f7175275a6b7 --- /dev/null +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_common/nbl_common.c @@ -0,0 +1,227 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 Nebula Matrix Limited. + * Author: + */ + +#include "nbl_common.h" + +struct nbl_common_wq_mgt { + struct workqueue_struct *ctrl_dev_wq; +}; + +static struct nbl_common_wq_mgt *wq_mgt; + +void nbl_common_queue_work(struct work_struct *task) +{ + queue_work(wq_mgt->ctrl_dev_wq, task); +} + +void nbl_common_destroy_wq(void) +{ + destroy_workqueue(wq_mgt->ctrl_dev_wq); + kfree(wq_mgt); +} + +int nbl_common_create_wq(void) +{ + wq_mgt =3D kzalloc(sizeof(*wq_mgt), GFP_KERNEL); + if (!wq_mgt) + return -ENOMEM; + + wq_mgt->ctrl_dev_wq =3D alloc_workqueue("%s", WQ_MEM_RECLAIM | WQ_UNBOUND, + 0, "nbl_ctrldev_wq"); + if (!wq_mgt->ctrl_dev_wq) { + pr_err("Failed to create workqueue nbl_ctrldev_wq\n"); + goto alloc_ctrl_dev_wq_failed; + } + + return 0; +alloc_ctrl_dev_wq_failed: + kfree(wq_mgt); + return -ENOMEM; +} + +u32 nbl_common_pf_id_subtraction_mgtpf_id(struct nbl_common_info *common, + u32 pf_id) +{ + u32 diff =3D U32_MAX; + + if (pf_id >=3D common->mgt_pf) + diff =3D pf_id - common->mgt_pf; + + return diff; +} + +static u32 nbl_common_calc_hash_key(void *key, u32 key_size, u32 bucket_si= ze) +{ + u32 value =3D 0; + u32 hash_val; + u32 i; + + /* if bucket size little than 1, the hash value always 0 */ + if (bucket_size =3D=3D NBL_HASH_TBL_LIST_BUCKET_SIZE) + return 0; + + for (i =3D 0; i < key_size; i++) + value +=3D *((u8 *)key + i); + + hash_val =3D __hash_32(value); + + return hash_val % bucket_size; +} + +/* + * alloc a hash table + * the table support multi thread + */ +struct nbl_hash_tbl_mgt * +nbl_common_init_hash_table(struct nbl_hash_tbl_key *key) +{ + struct nbl_hash_tbl_mgt *tbl_mgt; + int bucket_size; + int i; + + tbl_mgt =3D devm_kzalloc(key->dev, sizeof(struct nbl_hash_tbl_mgt), + GFP_KERNEL); + if (!tbl_mgt) + return NULL; + + bucket_size =3D key->bucket_size; + tbl_mgt->hash =3D devm_kcalloc(key->dev, bucket_size, + sizeof(struct hlist_head), GFP_KERNEL); + if (!tbl_mgt->hash) + goto alloc_hash_failed; + + for (i =3D 0; i < bucket_size; i++) + INIT_HLIST_HEAD(tbl_mgt->hash + i); + + memcpy(&tbl_mgt->tbl_key, key, sizeof(struct nbl_hash_tbl_key)); + + return tbl_mgt; + +alloc_hash_failed: + return NULL; +} + +/* + * alloc a hash node, and add to hlist_head + */ +int nbl_common_alloc_hash_node(struct nbl_hash_tbl_mgt *tbl_mgt, void *key, + void *data, void **out_data) +{ + struct nbl_hash_entry_node *hash_node; + u16 data_size; + u32 hash_val; + u16 key_size; + + hash_node =3D devm_kzalloc(tbl_mgt->tbl_key.dev, + sizeof(struct nbl_hash_entry_node), + GFP_KERNEL); + if (!hash_node) + return -1; + + key_size =3D tbl_mgt->tbl_key.key_size; + hash_node->key =3D + devm_kzalloc(tbl_mgt->tbl_key.dev, key_size, GFP_KERNEL); + if (!hash_node->key) + goto alloc_key_failed; + + data_size =3D tbl_mgt->tbl_key.data_size; + hash_node->data =3D + devm_kzalloc(tbl_mgt->tbl_key.dev, data_size, GFP_KERNEL); + if (!hash_node->data) + goto alloc_data_failed; + + memcpy(hash_node->key, key, key_size); + memcpy(hash_node->data, data, data_size); + + hash_val =3D nbl_common_calc_hash_key(key, key_size, + tbl_mgt->tbl_key.bucket_size); + + hlist_add_head(&hash_node->node, tbl_mgt->hash + hash_val); + tbl_mgt->node_num++; + if (out_data) + *out_data =3D hash_node->data; + + return 0; + +alloc_data_failed: +alloc_key_failed: + return -1; +} + +/* + * get a hash node, return the data if node exist + */ +void *nbl_common_get_hash_node(struct nbl_hash_tbl_mgt *tbl_mgt, void *key) +{ + struct nbl_hash_entry_node *hash_node; + struct hlist_head *head; + void *data =3D NULL; + u32 hash_val; + u16 key_size; + + key_size =3D tbl_mgt->tbl_key.key_size; + hash_val =3D nbl_common_calc_hash_key(key, key_size, + tbl_mgt->tbl_key.bucket_size); + head =3D tbl_mgt->hash + hash_val; + + hlist_for_each_entry(hash_node, head, node) + if (!memcmp(hash_node->key, key, key_size)) { + data =3D hash_node->data; + break; + } + + return data; +} + +static void nbl_common_remove_hash_node(struct nbl_hash_tbl_mgt *tbl_mgt, + struct nbl_hash_entry_node *hash_node) +{ + hlist_del(&hash_node->node); + tbl_mgt->node_num--; +} + +/* + * free a hash node + */ +void nbl_common_free_hash_node(struct nbl_hash_tbl_mgt *tbl_mgt, void *key) +{ + struct nbl_hash_entry_node *hash_node; + struct hlist_head *head; + u32 hash_val; + u16 key_size; + + key_size =3D tbl_mgt->tbl_key.key_size; + hash_val =3D nbl_common_calc_hash_key(key, key_size, + tbl_mgt->tbl_key.bucket_size); + head =3D tbl_mgt->hash + hash_val; + + hlist_for_each_entry(hash_node, head, node) + if (!memcmp(hash_node->key, key, key_size)) + break; + + if (hash_node) + nbl_common_remove_hash_node(tbl_mgt, hash_node); +} + +void nbl_common_remove_hash_table(struct nbl_hash_tbl_mgt *tbl_mgt, + struct nbl_hash_tbl_del_key *key) +{ + struct nbl_hash_entry_node *hash_node; + struct hlist_node *safe_node; + struct hlist_head *head; + u32 i; + + for (i =3D 0; i < tbl_mgt->tbl_key.bucket_size; i++) { + head =3D tbl_mgt->hash + i; + hlist_for_each_entry_safe(hash_node, safe_node, head, node) { + if (key && key->action_func) + key->action_func(key->action_priv, + hash_node->key, + hash_node->data); + nbl_common_remove_hash_node(tbl_mgt, hash_node); + } + } +} diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_common/nbl_common.h= b/drivers/net/ethernet/nebula-matrix/nbl/nbl_common/nbl_common.h new file mode 100644 index 000000000000..c6a43db41d83 --- /dev/null +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_common/nbl_common.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0*/ +/* + * Copyright (c) 2025 Nebula Matrix Limited. + * Author: + */ + +#ifndef _NBL_COMMON_H_ +#define _NBL_COMMON_H_ + +#include "nbl_def_common.h" + +/* list only need one bucket size */ +#define NBL_HASH_TBL_LIST_BUCKET_SIZE 1 + +struct nbl_hash_tbl_mgt { + struct nbl_hash_tbl_key tbl_key; + struct hlist_head *hash; + u16 node_num; +}; + +/* it used for y_axis no necessay */ +struct nbl_hash_entry_node { + struct hlist_node node; + void *key; + void *data; +}; + +#endif diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nb= l_hw_leonis.c b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis= /nbl_hw_leonis.c index 1ff5710cd955..307e71526143 100644 --- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_le= onis.c +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_le= onis.c @@ -6,7 +6,108 @@ =20 #include "nbl_hw_leonis.h" =20 +static void nbl_hw_update_mailbox_queue_tail_ptr(struct nbl_hw_mgt *hw_mgt, + u16 tail_ptr, u8 txrx) +{ + /* local_qid 0 and 1 denote rx and tx queue respectively */ + u32 local_qid =3D txrx; + u32 value =3D ((u32)tail_ptr << 16) | local_qid; + + /* wmb for doorbell */ + wmb(); + nbl_mbx_wr32(hw_mgt, NBL_MAILBOX_NOTIFY_ADDR, value); +} + +static void nbl_hw_config_mailbox_rxq(struct nbl_hw_mgt *hw_mgt, + dma_addr_t dma_addr, int size_bwid) +{ + struct nbl_mailbox_qinfo_cfg_table qinfo_cfg_rx_table =3D { 0 }; + + qinfo_cfg_rx_table.queue_rst =3D 1; + nbl_hw_write_mbx_regs(hw_mgt, NBL_MAILBOX_QINFO_CFG_RX_TABLE_ADDR, + (u8 *)&qinfo_cfg_rx_table, + sizeof(qinfo_cfg_rx_table)); + + qinfo_cfg_rx_table.queue_base_addr_l =3D (u32)(dma_addr & 0xFFFFFFFF); + qinfo_cfg_rx_table.queue_base_addr_h =3D (u32)(dma_addr >> 32); + qinfo_cfg_rx_table.queue_size_bwind =3D (u32)size_bwid; + qinfo_cfg_rx_table.queue_rst =3D 0; + qinfo_cfg_rx_table.queue_en =3D 1; + nbl_hw_write_mbx_regs(hw_mgt, NBL_MAILBOX_QINFO_CFG_RX_TABLE_ADDR, + (u8 *)&qinfo_cfg_rx_table, + sizeof(qinfo_cfg_rx_table)); +} + +static void nbl_hw_config_mailbox_txq(struct nbl_hw_mgt *hw_mgt, + dma_addr_t dma_addr, int size_bwid) +{ + struct nbl_mailbox_qinfo_cfg_table qinfo_cfg_tx_table =3D { 0 }; + + qinfo_cfg_tx_table.queue_rst =3D 1; + nbl_hw_write_mbx_regs(hw_mgt, NBL_MAILBOX_QINFO_CFG_TX_TABLE_ADDR, + (u8 *)&qinfo_cfg_tx_table, + sizeof(qinfo_cfg_tx_table)); + + qinfo_cfg_tx_table.queue_base_addr_l =3D (u32)(dma_addr & 0xFFFFFFFF); + qinfo_cfg_tx_table.queue_base_addr_h =3D (u32)(dma_addr >> 32); + qinfo_cfg_tx_table.queue_size_bwind =3D (u32)size_bwid; + qinfo_cfg_tx_table.queue_rst =3D 0; + qinfo_cfg_tx_table.queue_en =3D 1; + nbl_hw_write_mbx_regs(hw_mgt, NBL_MAILBOX_QINFO_CFG_TX_TABLE_ADDR, + (u8 *)&qinfo_cfg_tx_table, + sizeof(qinfo_cfg_tx_table)); +} + +static void nbl_hw_stop_mailbox_rxq(struct nbl_hw_mgt *hw_mgt) +{ + struct nbl_mailbox_qinfo_cfg_table qinfo_cfg_rx_table =3D { 0 }; + + nbl_hw_write_mbx_regs(hw_mgt, NBL_MAILBOX_QINFO_CFG_RX_TABLE_ADDR, + (u8 *)&qinfo_cfg_rx_table, + sizeof(qinfo_cfg_rx_table)); +} + +static void nbl_hw_stop_mailbox_txq(struct nbl_hw_mgt *hw_mgt) +{ + struct nbl_mailbox_qinfo_cfg_table qinfo_cfg_tx_table =3D { 0 }; + + nbl_hw_write_mbx_regs(hw_mgt, NBL_MAILBOX_QINFO_CFG_TX_TABLE_ADDR, + (u8 *)&qinfo_cfg_tx_table, + sizeof(qinfo_cfg_tx_table)); +} + +static u32 nbl_hw_get_host_pf_mask(struct nbl_hw_mgt *hw_mgt) +{ + u32 data; + + nbl_hw_rd_regs(hw_mgt, NBL_PCIE_HOST_K_PF_MASK_REG, (u8 *)&data, + sizeof(data)); + return data; +} + +static void nbl_hw_cfg_mailbox_qinfo(struct nbl_hw_mgt *hw_mgt, u16 func_i= d, + u16 bus, u16 devid, u16 function) +{ + struct nbl_mailbox_qinfo_map_table mb_qinfo_map; + + memset(&mb_qinfo_map, 0, sizeof(mb_qinfo_map)); + mb_qinfo_map.function =3D function; + mb_qinfo_map.devid =3D devid; + mb_qinfo_map.bus =3D bus; + mb_qinfo_map.msix_idx_valid =3D 0; + nbl_hw_wr_regs(hw_mgt, NBL_MAILBOX_QINFO_MAP_REG_ARR(func_id), + (u8 *)&mb_qinfo_map, sizeof(mb_qinfo_map)); +} + static struct nbl_hw_ops hw_ops =3D { + .update_mailbox_queue_tail_ptr =3D nbl_hw_update_mailbox_queue_tail_ptr, + .config_mailbox_rxq =3D nbl_hw_config_mailbox_rxq, + .config_mailbox_txq =3D nbl_hw_config_mailbox_txq, + .stop_mailbox_rxq =3D nbl_hw_stop_mailbox_rxq, + .stop_mailbox_txq =3D nbl_hw_stop_mailbox_txq, + .get_host_pf_mask =3D nbl_hw_get_host_pf_mask, + .cfg_mailbox_qinfo =3D nbl_hw_cfg_mailbox_qinfo, + }; =20 /* Structure starts here, adding an op should not modify anything below */ diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_cha= nnel.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_channel= .h index 975924781fe6..61d6038e22bc 100644 --- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_channel.h +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_channel.h @@ -9,6 +9,38 @@ =20 #include #include "nbl_include.h" +struct nbl_channel_mgt; +#define NBL_CHAN_SEND(chan_send, dst_id, mesg_type, argument, arg_length,\ + response, resp_length, need_ack) \ +do { \ + typeof(chan_send) *__chan_send =3D &(chan_send); \ + __chan_send->dstid =3D (dst_id); \ + __chan_send->msg_type =3D (mesg_type); \ + __chan_send->arg =3D (argument); \ + __chan_send->arg_len =3D (arg_length); \ + __chan_send->resp =3D (response); \ + __chan_send->resp_len =3D (resp_length); \ + __chan_send->ack =3D (need_ack); \ +} while (0) + +#define NBL_CHAN_ACK(chan_ack, dst_id, mesg_type, msg_id, err_code, ack_da= ta, \ + data_length) \ +do { \ + typeof(chan_ack) *__chan_ack =3D &(chan_ack); \ + __chan_ack->dstid =3D (dst_id); \ + __chan_ack->msg_type =3D (mesg_type); \ + __chan_ack->msgid =3D (msg_id); \ + __chan_ack->err =3D (err_code); \ + __chan_ack->data =3D (ack_data); \ + __chan_ack->data_len =3D (data_length); \ +} while (0) + +typedef void (*nbl_chan_resp)(void *, u16, u16, void *, u32); + +enum { + NBL_CHAN_RESP_OK, + NBL_CHAN_RESP_ERR, +}; =20 enum nbl_chan_msg_type { NBL_CHAN_MSG_ACK, @@ -236,6 +268,15 @@ enum nbl_chan_msg_type { NBL_CHAN_MSG_MAILBOX_MAX, }; =20 +#define NBL_CHANNEL_FREEZE_FAILED_CNT 3 + +enum nbl_chan_state { + NBL_CHAN_INTERRUPT_READY, + NBL_CHAN_RESETTING, + NBL_CHAN_ABNORMAL, + NBL_CHAN_STATE_NBITS +}; + struct nbl_chan_param_cfg_msix_map { u16 num_net_msix; u16 num_others_msix; @@ -259,12 +300,59 @@ struct nbl_chan_param_get_eth_id { u8 logic_eth_id; }; =20 +struct nbl_board_port_info { + u8 eth_num; + u8 eth_speed; + u8 p4_version; + u8 rsv[5]; +}; + +struct nbl_chan_send_info { + void *arg; + size_t arg_len; + void *resp; + size_t resp_len; + u16 dstid; + u16 msg_type; + u16 ack; + u16 ack_len; +}; + +struct nbl_chan_ack_info { + void *data; + int err; + u32 data_len; + u16 dstid; + u16 msg_type; + u16 msgid; +}; + enum nbl_channel_type { NBL_CHAN_TYPE_MAILBOX, NBL_CHAN_TYPE_MAX }; =20 struct nbl_channel_ops { + int (*send_msg)(struct nbl_channel_mgt *chan_mgt, + struct nbl_chan_send_info *chan_send); + int (*send_ack)(struct nbl_channel_mgt *chan_mgt, + struct nbl_chan_ack_info *chan_ack); + int (*register_msg)(struct nbl_channel_mgt *chan_mgt, u16 msg_type, + nbl_chan_resp func, void *callback_priv); + void (*unregister_msg)(struct nbl_channel_mgt *chan_mgt, u16 msg_type); + int (*cfg_chan_qinfo_map_table)(struct nbl_channel_mgt *chan_mgt, + u8 chan_type); + bool (*check_queue_exist)(struct nbl_channel_mgt *chan_mgt, + u8 chan_type); + int (*setup_queue)(struct nbl_channel_mgt *chan_mgt, u8 chan_type); + int (*teardown_queue)(struct nbl_channel_mgt *chan_mgt, u8 chan_type); + void (*clean_queue_subtask)(struct nbl_channel_mgt *chan_mgt, + u8 chan_type); + void (*register_chan_task)(struct nbl_channel_mgt *chan_mgt, + u8 chan_type, struct work_struct *task); + void (*set_queue_state)(struct nbl_channel_mgt *chan_mgt, + enum nbl_chan_state state, u8 chan_type, + u8 set); }; =20 struct nbl_channel_ops_tbl { diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_com= mon.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_common.h index b98bbc726308..fa53a0019400 100644 --- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_common.h +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_common.h @@ -8,6 +8,7 @@ #define _NBL_DEF_COMMON_H_ =20 #include "nbl_include.h" +struct nbl_hash_tbl_mgt; =20 struct nbl_common_info { struct pci_dev *pdev; @@ -30,4 +31,76 @@ struct nbl_common_info { u8 is_ctrl; }; =20 +struct nbl_hash_tbl_key { + struct device *dev; + u16 key_size; + u16 data_size; /* no include key or node member */ + u16 bucket_size; + u16 resv; +}; + +#define NBL_HASH_TBL_KEY_INIT(key, dev_arg, key_size_arg, data_size_arg,\ + bucket_size_arg) \ +do { \ + typeof(key) __key =3D key; \ + __key->dev =3D dev_arg; \ + __key->key_size =3D key_size_arg; \ + __key->data_size =3D data_size_arg; \ + __key->bucket_size =3D bucket_size_arg; \ + __key->resv =3D 0; \ +} while (0) + +enum nbl_hash_tbl_op_type { + NBL_HASH_TBL_OP_SHOW =3D 0, + NBL_HASH_TBL_OP_DELETE, +}; + +struct nbl_hash_tbl_del_key { + void *action_priv; + void (*action_func)(void *priv, void *key, void *data); +}; + +#define NBL_HASH_TBL_DEL_KEY_INIT(key, priv_arg, act_func_arg) \ +do { \ + typeof(key) __key =3D key; \ + __key->action_priv =3D priv_arg; \ + __key->action_func =3D act_func_arg; \ +} while (0) + +struct nbl_hash_tbl_scan_key { + enum nbl_hash_tbl_op_type op_type; + void *match_condition; + /* match ret value must be 0 if the node accord with the condition */ + int (*match_func)(void *condition, void *key, void *data); + void *action_priv; + void (*action_func)(void *priv, void *key, void *data); +}; + +#define NBL_HASH_TBL_SCAN_KEY_INIT(key, op_type_arg, con_arg, match_func_a= rg,\ + priv_arg, act_func_arg) \ +do { \ + typeof(key) __key =3D key; \ + __key->op_type =3D op_type_arg; \ + __key->match_condition =3D con_arg; \ + __key->match_func =3D match_func_arg; \ + __key->action_priv =3D priv_arg; \ + __key->action_func =3D act_func_arg; \ +} while (0) + +void nbl_common_queue_work(struct work_struct *task); + +void nbl_common_destroy_wq(void); +int nbl_common_create_wq(void); +u32 nbl_common_pf_id_subtraction_mgtpf_id(struct nbl_common_info *common, + u32 pf_id); + +struct nbl_hash_tbl_mgt * +nbl_common_init_hash_table(struct nbl_hash_tbl_key *key); +void nbl_common_remove_hash_table(struct nbl_hash_tbl_mgt *tbl_mgt, + struct nbl_hash_tbl_del_key *key); +int nbl_common_alloc_hash_node(struct nbl_hash_tbl_mgt *tbl_mgt, void *key, + void *data, void **out_data); +void *nbl_common_get_hash_node(struct nbl_hash_tbl_mgt *tbl_mgt, void *key= ); +void nbl_common_free_hash_node(struct nbl_hash_tbl_mgt *tbl_mgt, void *key= ); + #endif diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_hw.= h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_hw.h index 80ebddec55f8..80b152cad1b0 100644 --- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_hw.h +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_hw.h @@ -10,6 +10,32 @@ #include "nbl_include.h" struct nbl_hw_mgt; struct nbl_hw_ops { + void (*configure_msix_map)(struct nbl_hw_mgt *hw_mgt, u16 func_id, + bool valid, dma_addr_t dma_addr, u8 bus, + u8 devid, u8 function); + void (*configure_msix_info)(struct nbl_hw_mgt *hw_mgt, u16 func_id, + bool valid, u16 interrupt_id, u8 bus, + u8 devid, u8 function, + bool net_msix_mask_en); + void (*update_mailbox_queue_tail_ptr)(struct nbl_hw_mgt *hw_mgt, + u16 tail_ptr, u8 txrx); + void (*config_mailbox_rxq)(struct nbl_hw_mgt *hw_mgt, + dma_addr_t dma_addr, int size_bwid); + void (*config_mailbox_txq)(struct nbl_hw_mgt *hw_mgt, + dma_addr_t dma_addr, int size_bwid); + void (*stop_mailbox_rxq)(struct nbl_hw_mgt *hw_mgt); + void (*stop_mailbox_txq)(struct nbl_hw_mgt *hw_mgt); + u32 (*get_host_pf_mask)(struct nbl_hw_mgt *hw_mgt); + u32 (*get_real_bus)(struct nbl_hw_mgt *hw_mgt); + + void (*cfg_mailbox_qinfo)(struct nbl_hw_mgt *hw_mgt, u16 func_id, + u16 bus, u16 devid, u16 function); + void (*enable_mailbox_irq)(struct nbl_hw_mgt *hw_mgt, u16 func_id, + bool enable_msix, u16 global_vec_id); + u32 (*get_fw_eth_num)(struct nbl_hw_mgt *hw_mgt); + u32 (*get_fw_eth_map)(struct nbl_hw_mgt *hw_mgt); + void (*get_board_info)(struct nbl_hw_mgt *hw_mgt, + struct nbl_board_port_info *board); }; =20 struct nbl_hw_ops_tbl { diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_include= .h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_include.h index f58b4dbb0aab..f56df4008660 100644 --- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_include.h +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_include.h @@ -11,7 +11,12 @@ #include /* ------ Basic definitions ------- */ #define NBL_DRIVER_NAME "nbl_core" - +#define NBL_MAX_PF 8 +#define NBL_NEXT_ID(id, max) \ + ({ \ + typeof(id) _id =3D (id); \ + ((_id) =3D=3D (max) ? 0 : (_id) + 1); \ + }) enum nbl_product_type { NBL_LEONIS_TYPE, NBL_PRODUCT_MAX, --=20 2.47.3 From nobody Sun Feb 8 00:11:39 2026 Received: from out198-19.us.a.mail.aliyun.com (out198-19.us.a.mail.aliyun.com [47.90.198.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 66B8A266B72; Fri, 6 Feb 2026 02:34:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=47.90.198.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770345256; cv=none; b=ZT+t8bgGIYy3fqMMVfV5gHPhAQDbZ43UaK8TlCH3mjcmdJrc4378J+HNO2JKKgJjKTmHEwkxy5QXKXhfN+b8u9xr/D52cekU5OuKssPf4XHJdYzEecp6wm+0Nim1LMAC71RLfC+Q1wu6abVsuEaKZp5NFbWycWcwIdUI1fw1ufY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770345256; c=relaxed/simple; bh=E8wzhAvDe96e9qiyqdHOG3KH4CmIOxPxaNywKjezwuU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=h9V07IknjE0eJTx5euxU+EzAm3UyCsWnIDPW0G80l7tQa3jMo8XNCSIEeyDUL6QJg76FS1J56zm27punwE/JtieuIy57A2j/u/pUGqjlbzaflGJPUcVfdiW2xWTEJAqrMPBXcKVLYJ6Ue6n82PDuQiN4vYC9VHzvlApQ1mPcGX8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=nebula-matrix.com; spf=pass smtp.mailfrom=nebula-matrix.com; arc=none smtp.client-ip=47.90.198.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=nebula-matrix.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nebula-matrix.com Received: from localhost.localdomain(mailfrom:illusion.wang@nebula-matrix.com fp:SMTPD_---.gQHg4lW_1770344296 cluster:ay29) by smtp.aliyun-inc.com; Fri, 06 Feb 2026 10:18:17 +0800 From: "illusion.wang" To: dimon.zhao@nebula-matrix.com, illusion.wang@nebula-matrix.com, alvin.wang@nebula-matrix.com, sam.chen@nebula-matrix.com, netdev@vger.kernel.org Cc: andrew+netdev@lunn.ch, corbet@lwn.net, kuba@kernel.org, linux-doc@vger.kernel.org, lorenzo@kernel.org, pabeni@redhat.com, horms@kernel.org, vadim.fedorenko@linux.dev, lukas.bulwahn@redhat.com, edumazet@google.com, linux-kernel@vger.kernel.org (open list) Subject: [PATCH v4 net-next 06/11] net/nebula-matrix: add common resource implementation Date: Fri, 6 Feb 2026 10:15:58 +0800 Message-ID: <20260206021608.85381-7-illusion.wang@nebula-matrix.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260206021608.85381-1-illusion.wang@nebula-matrix.com> References: <20260206021608.85381-1-illusion.wang@nebula-matrix.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The Resource layer processes the entries/data of various modules within the processing chip to accomplish specific entry management operations, this describes the module business capabilities of the chip and the data it manages. The resource layer comprises the following sub-modules: common,=C2=A0 interrupt, and vsi(txrx,queue not contained this time) This patch provides the common part, including the conversion relationships among vsi_id, func_id, eth_id, and pf_id. These relationships may be utilized in the upper layer or the resource layer. Signed-off-by: illusion.wang --- .../net/ethernet/nebula-matrix/nbl/Makefile | 1 + .../nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.c | 43 ++++ .../nbl_hw_leonis/nbl_resource_leonis.c | 183 ++++++++++++++++++ .../nbl_hw_leonis/nbl_resource_leonis.h | 1 - .../nebula-matrix/nbl/nbl_hw/nbl_resource.c | 142 ++++++++++++++ .../nebula-matrix/nbl/nbl_hw/nbl_resource.h | 64 ++++++ .../nbl/nbl_include/nbl_def_common.h | 16 ++ .../nbl/nbl_include/nbl_def_resource.h | 13 ++ .../nbl/nbl_include/nbl_include.h | 7 + 9 files changed, 469 insertions(+), 1 deletion(-) create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_resou= rce.c diff --git a/drivers/net/ethernet/nebula-matrix/nbl/Makefile b/drivers/net/= ethernet/nebula-matrix/nbl/Makefile index b93d21a99e99..db391bf70b20 100644 --- a/drivers/net/ethernet/nebula-matrix/nbl/Makefile +++ b/drivers/net/ethernet/nebula-matrix/nbl/Makefile @@ -9,6 +9,7 @@ nbl_core-objs +=3D nbl_common/nbl_common.o \ nbl_hw/nbl_hw_leonis/nbl_hw_leonis.o \ nbl_hw/nbl_hw_leonis/nbl_resource_leonis.o \ nbl_hw/nbl_hw_leonis/nbl_hw_leonis_regs.o \ + nbl_hw/nbl_resource.o \ nbl_core/nbl_dispatch.o \ nbl_core/nbl_dev.o \ nbl_main.o diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nb= l_hw_leonis.c b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis= /nbl_hw_leonis.c index 307e71526143..867eea831c10 100644 --- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_le= onis.c +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_le= onis.c @@ -85,6 +85,14 @@ static u32 nbl_hw_get_host_pf_mask(struct nbl_hw_mgt *hw= _mgt) return data; } =20 +static u32 nbl_hw_get_real_bus(struct nbl_hw_mgt *hw_mgt) +{ + u32 data; + + data =3D nbl_hw_rd32(hw_mgt, NBL_PCIE_HOST_TL_CFG_BUSDEV); + return data >> 5; +} + static void nbl_hw_cfg_mailbox_qinfo(struct nbl_hw_mgt *hw_mgt, u16 func_i= d, u16 bus, u16 devid, u16 function) { @@ -99,6 +107,36 @@ static void nbl_hw_cfg_mailbox_qinfo(struct nbl_hw_mgt = *hw_mgt, u16 func_id, (u8 *)&mb_qinfo_map, sizeof(mb_qinfo_map)); } =20 +static void nbl_hw_get_board_info(struct nbl_hw_mgt *hw_mgt, + struct nbl_board_port_info *board_info) +{ + union nbl_fw_board_cfg_dw3 dw3 =3D { .info =3D { 0 } }; + + nbl_hw_read_mbx_regs(hw_mgt, NBL_FW_BOARD_DW3_OFFSET, (u8 *)&dw3, + sizeof(dw3)); + board_info->eth_num =3D dw3.info.port_num; + board_info->eth_speed =3D dw3.info.port_speed; + board_info->p4_version =3D dw3.info.p4_version; +} + +static u32 nbl_hw_get_fw_eth_num(struct nbl_hw_mgt *hw_mgt) +{ + union nbl_fw_board_cfg_dw3 dw3 =3D { .info =3D { 0 } }; + + nbl_hw_read_mbx_regs(hw_mgt, NBL_FW_BOARD_DW3_OFFSET, (u8 *)&dw3, + sizeof(dw3)); + return dw3.info.port_num; +} + +static u32 nbl_hw_get_fw_eth_map(struct nbl_hw_mgt *hw_mgt) +{ + union nbl_fw_board_cfg_dw6 dw6 =3D { .info =3D { 0 } }; + + nbl_hw_read_mbx_regs(hw_mgt, NBL_FW_BOARD_DW6_OFFSET, (u8 *)&dw6, + sizeof(dw6)); + return dw6.info.eth_bitmap; +} + static struct nbl_hw_ops hw_ops =3D { .update_mailbox_queue_tail_ptr =3D nbl_hw_update_mailbox_queue_tail_ptr, .config_mailbox_rxq =3D nbl_hw_config_mailbox_rxq, @@ -106,8 +144,13 @@ static struct nbl_hw_ops hw_ops =3D { .stop_mailbox_rxq =3D nbl_hw_stop_mailbox_rxq, .stop_mailbox_txq =3D nbl_hw_stop_mailbox_txq, .get_host_pf_mask =3D nbl_hw_get_host_pf_mask, + .get_real_bus =3D nbl_hw_get_real_bus, + .cfg_mailbox_qinfo =3D nbl_hw_cfg_mailbox_qinfo, =20 + .get_fw_eth_num =3D nbl_hw_get_fw_eth_num, + .get_fw_eth_map =3D nbl_hw_get_fw_eth_map, + .get_board_info =3D nbl_hw_get_board_info, }; =20 /* Structure starts here, adding an op should not modify anything below */ diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nb= l_resource_leonis.c b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_= leonis/nbl_resource_leonis.c index bd395e607f5f..f3753771a299 100644 --- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_resou= rce_leonis.c +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_resou= rce_leonis.c @@ -6,7 +6,32 @@ =20 #include "nbl_resource_leonis.h" =20 +static u16 nbl_res_get_vsi_id(struct nbl_resource_mgt *res_mgt, u16 func_i= d, + u16 type) +{ + return nbl_res_func_id_to_vsi_id(res_mgt, func_id, type); +} + +static void nbl_res_get_eth_id(struct nbl_resource_mgt *res_mgt, u16 vsi_i= d, + u8 *eth_mode, u8 *eth_id, u8 *logic_eth_id) +{ + struct nbl_eth_info *eth_info =3D NBL_RES_MGT_TO_ETH_INFO(res_mgt); + u16 pf_id =3D nbl_res_vsi_id_to_pf_id(res_mgt, vsi_id); + + *eth_mode =3D eth_info->eth_num; + if (pf_id < eth_info->eth_num) { + *eth_id =3D eth_info->eth_id[pf_id]; + *logic_eth_id =3D pf_id; + /* if pf_id > eth_num, use eth_id 0 */ + } else { + *eth_id =3D eth_info->eth_id[0]; + *logic_eth_id =3D 0; + } +} + static struct nbl_resource_ops res_ops =3D { + .get_vsi_id =3D nbl_res_get_vsi_id, + .get_eth_id =3D nbl_res_get_eth_id, }; =20 static int @@ -47,10 +72,167 @@ static int nbl_res_setup_ops(struct device *dev, return 0; } =20 +static int nbl_res_ctrl_dev_setup_eth_info(struct nbl_resource_mgt *res_mg= t) +{ + struct nbl_hw_ops *hw_ops =3D res_mgt->hw_ops_tbl->ops; + struct device *dev =3D res_mgt->common->dev; + struct nbl_eth_info *eth_info; + u32 eth_bitmap, eth_id; + u32 eth_num =3D 0; + int i; + + eth_info =3D devm_kzalloc(dev, sizeof(struct nbl_eth_info), GFP_KERNEL); + if (!eth_info) + return -ENOMEM; + + res_mgt->resource_info->eth_info =3D eth_info; + + eth_info->eth_num =3D + (u8)hw_ops->get_fw_eth_num(res_mgt->hw_ops_tbl->priv); + eth_bitmap =3D hw_ops->get_fw_eth_map(res_mgt->hw_ops_tbl->priv); + /* for 2 eth port board, the eth_id is 0, 2 */ + for (i =3D 0; i < NBL_MAX_ETHERNET; i++) { + if ((1 << i) & eth_bitmap) { + set_bit(i, eth_info->eth_bitmap); + eth_info->eth_id[eth_num] =3D i; + eth_info->logic_eth_id[i] =3D eth_num; + eth_num++; + } + } + + for (i =3D 0; i < NBL_RES_MGT_TO_PF_NUM(res_mgt); i++) { + /* if pf_id <=3D eth_num, the pf relate corresponding eth_id*/ + if (i < eth_num) { + eth_id =3D eth_info->eth_id[i]; + eth_info->pf_bitmap[eth_id] |=3D BIT(i); + } + /* if pf_id > eth_num, the pf relate eth 0*/ + else + eth_info->pf_bitmap[0] |=3D BIT(i); + } + + return 0; +} + +static int nbl_res_ctrl_dev_sriov_info_init(struct nbl_resource_mgt *res_m= gt) +{ + struct nbl_hw_ops *hw_ops =3D res_mgt->hw_ops_tbl->ops; + struct nbl_hw_mgt *p =3D res_mgt->hw_ops_tbl->priv; + struct nbl_common_info *common =3D res_mgt->common; + struct nbl_sriov_info *sriov_info; + struct device *dev =3D common->dev; + u16 func_id, function; + + sriov_info =3D devm_kcalloc(dev, NBL_RES_MGT_TO_PF_NUM(res_mgt), + sizeof(struct nbl_sriov_info), GFP_KERNEL); + if (!sriov_info) + return -ENOMEM; + + res_mgt->resource_info->sriov_info =3D sriov_info; + + for (func_id =3D 0; func_id < NBL_RES_MGT_TO_PF_NUM(res_mgt); func_id++) { + sriov_info =3D &NBL_RES_MGT_TO_SRIOV_INFO(res_mgt)[func_id]; + function =3D common->function + func_id; + + common->hw_bus =3D (u8)hw_ops->get_real_bus(p); + sriov_info->bdf =3D PCI_DEVID(common->hw_bus, + PCI_DEVFN(common->devid, function)); + } + return 0; +} + +static int nbl_res_ctrl_dev_vsi_info_init(struct nbl_resource_mgt *res_mgt) +{ + struct nbl_eth_info *eth_info =3D NBL_RES_MGT_TO_ETH_INFO(res_mgt); + struct nbl_common_info *common =3D res_mgt->common; + struct device *dev =3D common->dev; + struct nbl_vsi_info *vsi_info; + int i; + + vsi_info =3D devm_kcalloc(dev, NBL_RES_MGT_TO_PF_NUM(res_mgt), + sizeof(struct nbl_vsi_info), GFP_KERNEL); + if (!vsi_info) + return -ENOMEM; + + res_mgt->resource_info->vsi_info =3D vsi_info; + /* + * case 1 two port(2pf) + * pf0,pf1(NBL_VSI_SERV_PF_DATA_TYPE) vsi is 0,512 + + * case 2 four port(4pf) + * pf0,pf1,pf2,pf3(NBL_VSI_SERV_PF_DATA_TYPE) vsi is 0,256,512,768 + + */ + + vsi_info->num =3D eth_info->eth_num; + for (i =3D 0; i < vsi_info->num; i++) { + vsi_info->serv_info[i][NBL_VSI_SERV_PF_DATA_TYPE].base_id =3D + i * NBL_VSI_ID_GAP(vsi_info->num); + vsi_info->serv_info[i][NBL_VSI_SERV_PF_DATA_TYPE].num =3D 1; + } + return 0; +} + +static int nbl_res_init_pf_num(struct nbl_resource_mgt *res_mgt) +{ + struct nbl_hw_ops *hw_ops =3D res_mgt->hw_ops_tbl->ops; + u32 pf_num =3D 0; + u32 pf_mask; + int i; + + pf_mask =3D hw_ops->get_host_pf_mask(res_mgt->hw_ops_tbl->priv); + for (i =3D 0; i < NBL_MAX_PF; i++) { + if (!(pf_mask & (1 << i))) + pf_num++; + else + break; + } + + res_mgt->resource_info->max_pf =3D pf_num; + + if (!pf_num) + return -1; + + return 0; +} + +static void nbl_res_init_board_info(struct nbl_resource_mgt *res_mgt) +{ + struct nbl_hw_ops *hw_ops =3D res_mgt->hw_ops_tbl->ops; + + hw_ops->get_board_info(res_mgt->hw_ops_tbl->priv, + &res_mgt->resource_info->board_info); +} + static int nbl_res_start(struct nbl_resource_mgt_leonis *res_mgt_leonis, struct nbl_func_caps caps) { + struct nbl_resource_mgt *res_mgt =3D &res_mgt_leonis->res_mgt; + int ret =3D 0; + + if (caps.has_ctrl) { + nbl_res_init_board_info(res_mgt); + + ret =3D nbl_res_init_pf_num(res_mgt); + if (ret) + return ret; + + ret =3D nbl_res_ctrl_dev_sriov_info_init(res_mgt); + if (ret) + return ret; + + ret =3D nbl_res_ctrl_dev_setup_eth_info(res_mgt); + if (ret) + goto start_fail; + + ret =3D nbl_res_ctrl_dev_vsi_info_init(res_mgt); + if (ret) + goto start_fail; + } return 0; + +start_fail: + return ret; } =20 int nbl_res_init_leonis(struct nbl_adapter *adap, struct nbl_init_param *p= aram) @@ -63,6 +245,7 @@ int nbl_res_init_leonis(struct nbl_adapter *adap, struct= nbl_init_param *param) struct nbl_resource_mgt_leonis **mgt =3D (struct nbl_resource_mgt_leonis **)&NBL_ADAP_TO_RES_MGT(adap); struct device *dev =3D &adap->pdev->dev; + int ret =3D 0; =20 ret =3D nbl_res_setup_res_mgt(common, mgt); diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nb= l_resource_leonis.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_= leonis/nbl_resource_leonis.h index 80925ff9e680..1d42850ee99d 100644 --- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_resou= rce_leonis.h +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_resou= rce_leonis.h @@ -8,5 +8,4 @@ #define _NBL_RESOURCE_LEONIS_H_ =20 #include "nbl_resource.h" - #endif diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_resource.c b= /drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_resource.c new file mode 100644 index 000000000000..cd48e3f152de --- /dev/null +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_resource.c @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 Nebula Matrix Limited. + * Author: + */ + +#include "nbl_resource.h" + +static u16 pfvfid_to_vsi_id(struct nbl_resource_mgt *res_mgt, int pfid, + int vfid, u16 type) +{ + struct nbl_vsi_info *vsi_info =3D NBL_RES_MGT_TO_VSI_INFO(res_mgt); + enum nbl_vsi_serv_type dst_type =3D NBL_VSI_SERV_PF_DATA_TYPE; + struct nbl_common_info *common =3D res_mgt->common; + u16 vsi_id =3D U16_MAX; + int diff; + + diff =3D nbl_common_pf_id_subtraction_mgtpf_id(common, pfid); + if (vfid =3D=3D U32_MAX || vfid =3D=3D U16_MAX) { + if (diff < vsi_info->num) { + nbl_res_pf_dev_vsi_type_to_hw_vsi_type(type, &dst_type); + vsi_id =3D vsi_info->serv_info[diff][dst_type].base_id; + } + } + + if (vsi_id =3D=3D U16_MAX) + pr_err("convert pfid-vfid %d-%d to vsi_id(%d) failed!\n", pfid, + vfid, type); + + return vsi_id; +} + +static u16 func_id_to_vsi_id(struct nbl_resource_mgt *res_mgt, u16 func_id, + u16 type) +{ + int pfid =3D U32_MAX; + int vfid =3D U32_MAX; + + nbl_res_func_id_to_pfvfid(res_mgt, func_id, &pfid, &vfid); + return nbl_res_pfvfid_to_vsi_id(res_mgt, pfid, vfid, type); +} + +static int vsi_id_to_pf_id(struct nbl_resource_mgt *res_mgt, u16 vsi_id) +{ + struct nbl_vsi_info *vsi_info =3D NBL_RES_MGT_TO_VSI_INFO(res_mgt); + struct nbl_common_info *common =3D res_mgt->common; + bool vsi_find =3D false; + u32 pf_id =3D U32_MAX; + int i, j; + + for (i =3D 0; i < vsi_info->num; i++) { + for (j =3D 0; j < NBL_VSI_SERV_MAX_TYPE; j++) + if (vsi_id >=3D vsi_info->serv_info[i][j].base_id && + (vsi_id < vsi_info->serv_info[i][j].base_id + + vsi_info->serv_info[i][j].num)) { + vsi_find =3D true; + break; + } + + if (vsi_find) + break; + } + + if (vsi_find) { + /* if pf_id < eth_num */ + if (j >=3D NBL_VSI_SERV_PF_DATA_TYPE && + j <=3D NBL_VSI_SERV_PF_DATA_TYPE) + pf_id =3D i + common->mgt_pf; + } + + return pf_id; +} + +static int func_id_to_pfvfid(struct nbl_resource_mgt *res_mgt, u16 func_id, + int *pfid, int *vfid) +{ + if (func_id < NBL_RES_MGT_TO_PF_NUM(res_mgt)) { + *pfid =3D func_id; + *vfid =3D U32_MAX; + return 0; + } + return U32_MAX; +} + +static int func_id_to_bdf(struct nbl_resource_mgt *res_mgt, u16 func_id, + u8 *bus, u8 *dev, u8 *function) +{ + struct nbl_common_info *common =3D res_mgt->common; + struct nbl_sriov_info *sriov_info; + int pfid =3D U32_MAX; + int vfid =3D U32_MAX; + u8 pf_bus, devfn; + int diff; + + if (nbl_res_func_id_to_pfvfid(res_mgt, func_id, &pfid, &vfid)) + return U32_MAX; + + diff =3D nbl_common_pf_id_subtraction_mgtpf_id(common, pfid); + sriov_info =3D NBL_RES_MGT_TO_SRIOV_INFO(res_mgt) + diff; + pf_bus =3D PCI_BUS_NUM(sriov_info->bdf); + devfn =3D sriov_info->bdf & 0xff; + *bus =3D pf_bus; + *dev =3D PCI_SLOT(devfn); + *function =3D PCI_FUNC(devfn); + return 0; +} + +int nbl_res_func_id_to_pfvfid(struct nbl_resource_mgt *res_mgt, u16 func_i= d, + int *pfid, int *vfid) +{ + return func_id_to_pfvfid(res_mgt, func_id, pfid, vfid); +} + +u16 nbl_res_pfvfid_to_vsi_id(struct nbl_resource_mgt *res_mgt, int pfid, + int vfid, u16 type) +{ + return pfvfid_to_vsi_id(res_mgt, pfid, vfid, type); +} + +int nbl_res_func_id_to_bdf(struct nbl_resource_mgt *res_mgt, u16 func_id, + u8 *bus, u8 *dev, u8 *function) +{ + return func_id_to_bdf(res_mgt, func_id, bus, dev, function); +} + +int nbl_res_vsi_id_to_pf_id(struct nbl_resource_mgt *res_mgt, u16 vsi_id) +{ + return vsi_id_to_pf_id(res_mgt, vsi_id); +} + +u16 nbl_res_func_id_to_vsi_id(struct nbl_resource_mgt *res_mgt, u16 func_i= d, + u16 type) +{ + return func_id_to_vsi_id(res_mgt, func_id, type); +} + +void nbl_res_pf_dev_vsi_type_to_hw_vsi_type(u16 src_type, + enum nbl_vsi_serv_type *dst_type) +{ + if (src_type =3D=3D NBL_VSI_DATA) + *dst_type =3D NBL_VSI_SERV_PF_DATA_TYPE; +} diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_resource.h b= /drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_resource.h index 8429eb263862..9c4595f9463c 100644 --- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_resource.h +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_resource.h @@ -8,8 +8,60 @@ #define _NBL_RESOURCE_H_ =20 #include "nbl_core.h" +#include "nbl_hw.h" + +struct nbl_resource_mgt; + +#define NBL_RES_MGT_TO_RES_INFO(res_mgt) ((res_mgt)->resource_info) +#define NBL_RES_MGT_TO_SRIOV_INFO(res_mgt) \ + (NBL_RES_MGT_TO_RES_INFO(res_mgt)->sriov_info) +#define NBL_RES_MGT_TO_ETH_INFO(res_mgt) \ + (NBL_RES_MGT_TO_RES_INFO(res_mgt)->eth_info) +#define NBL_RES_MGT_TO_VSI_INFO(res_mgt) \ + (NBL_RES_MGT_TO_RES_INFO(res_mgt)->vsi_info) +#define NBL_RES_MGT_TO_PF_NUM(res_mgt) \ + (NBL_RES_MGT_TO_RES_INFO(res_mgt)->max_pf) + +/* --------- INFO ---------- */ +struct nbl_sriov_info { + unsigned int bdf; +}; + +struct nbl_eth_info { + DECLARE_BITMAP(eth_bitmap, NBL_MAX_ETHERNET); + u8 pf_bitmap[NBL_MAX_ETHERNET]; + u8 eth_num; + u8 resv[3]; + u8 eth_id[NBL_MAX_PF]; + u8 logic_eth_id[NBL_MAX_PF]; +}; + +enum nbl_vsi_serv_type { + NBL_VSI_SERV_PF_DATA_TYPE, + NBL_VSI_SERV_MAX_TYPE, +}; + +struct nbl_vsi_serv_info { + u16 base_id; + u16 num; +}; + +struct nbl_vsi_info { + u16 num; + struct nbl_vsi_serv_info serv_info[NBL_MAX_ETHERNET] + [NBL_VSI_SERV_MAX_TYPE]; +}; =20 struct nbl_resource_info { + /* ctrl-dev owned pfs */ + DECLARE_BITMAP(func_bitmap, NBL_MAX_FUNC); + struct nbl_sriov_info *sriov_info; + struct nbl_eth_info *eth_info; + struct nbl_vsi_info *vsi_info; + u32 base_qid; + u32 max_vf_num; + u8 max_pf; + struct nbl_board_port_info board_info; }; =20 struct nbl_resource_mgt { @@ -27,4 +79,16 @@ struct nbl_resource_mgt { struct nbl_resource_mgt_leonis { struct nbl_resource_mgt res_mgt; }; + +int nbl_res_vsi_id_to_pf_id(struct nbl_resource_mgt *res_mgt, u16 vsi_id); +u16 nbl_res_pfvfid_to_vsi_id(struct nbl_resource_mgt *res_mgt, int pfid, + int vfid, u16 type); +u16 nbl_res_func_id_to_vsi_id(struct nbl_resource_mgt *res_mgt, u16 func_i= d, + u16 type); +int nbl_res_func_id_to_pfvfid(struct nbl_resource_mgt *res_mgt, u16 func_i= d, + int *pfid, int *vfid); +int nbl_res_func_id_to_bdf(struct nbl_resource_mgt *res_mgt, u16 func_id, + u8 *bus, u8 *dev, u8 *function); +void nbl_res_pf_dev_vsi_type_to_hw_vsi_type(u16 src_type, + enum nbl_vsi_serv_type *dst_type); #endif diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_com= mon.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_common.h index fa53a0019400..eca4b7b901a6 100644 --- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_common.h +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_common.h @@ -9,6 +9,22 @@ =20 #include "nbl_include.h" struct nbl_hash_tbl_mgt; +#define NBL_ONE_ETHERNET_PORT (1) +#define NBL_TWO_ETHERNET_PORT (2) +#define NBL_FOUR_ETHERNET_PORT (4) +#define NBL_DEFAULT_VSI_ID_GAP (1024) +#define NBL_TWO_ETHERNET_VSI_ID_GAP (512) +#define NBL_FOUR_ETHERNET_VSI_ID_GAP (256) + +#define NBL_VSI_ID_GAP(m) \ + ({ \ + typeof(m) _m =3D (m); \ + _m =3D=3D NBL_FOUR_ETHERNET_PORT ? \ + NBL_FOUR_ETHERNET_VSI_ID_GAP : \ + (_m =3D=3D NBL_TWO_ETHERNET_PORT ? \ + NBL_TWO_ETHERNET_VSI_ID_GAP : \ + NBL_DEFAULT_VSI_ID_GAP); \ + }) =20 struct nbl_common_info { struct pci_dev *pdev; diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_res= ource.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_resour= ce.h index 74a6a7ee9af9..b6f7ca1faa34 100644 --- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_resource.h +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_resource.h @@ -11,6 +11,19 @@ struct nbl_resource_mgt; =20 struct nbl_resource_ops { + int (*init_chip_module)(struct nbl_resource_mgt *res_mgt); + void (*deinit_chip_module)(struct nbl_resource_mgt *res_mgt); + + int (*configure_msix_map)(struct nbl_resource_mgt *res_mgt, u16 func_id, + u16 num_net_msix, u16 num_others_msix, + bool net_msix_mask_en); + int (*destroy_msix_map)(struct nbl_resource_mgt *res_mgt, u16 func_id); + int (*enable_mailbox_irq)(struct nbl_resource_mgt *res_mgt, u16 func_id, + u16 vector_id, bool enable_msix); + u16 (*get_vsi_id)(struct nbl_resource_mgt *res_mgt, u16 func_id, + u16 type); + void (*get_eth_id)(struct nbl_resource_mgt *res_mgt, u16 vsi_id, + u8 *eth_mode, u8 *eth_id, u8 *logic_eth_id); }; =20 struct nbl_resource_ops_tbl { diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_include= .h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_include.h index f56df4008660..659f8fb84406 100644 --- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_include.h +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_include.h @@ -11,17 +11,24 @@ #include /* ------ Basic definitions ------- */ #define NBL_DRIVER_NAME "nbl_core" + #define NBL_MAX_PF 8 #define NBL_NEXT_ID(id, max) \ ({ \ typeof(id) _id =3D (id); \ ((_id) =3D=3D (max) ? 0 : (_id) + 1); \ }) +#define NBL_MAX_FUNC (520) enum nbl_product_type { NBL_LEONIS_TYPE, NBL_PRODUCT_MAX, }; =20 +enum { + NBL_VSI_DATA =3D 0, + NBL_VSI_MAX, +}; + struct nbl_func_caps { u32 has_ctrl:1; u32 has_net:1; --=20 2.47.3 From nobody Sun Feb 8 00:11:39 2026 Received: from out198-27.us.a.mail.aliyun.com (out198-27.us.a.mail.aliyun.com [47.90.198.27]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0AD7725C704; Fri, 6 Feb 2026 02:34:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=47.90.198.27 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770345256; cv=none; b=E9+65OEEo0lLYmdcAe5nzO59wORo/fqm8Dd6rQXfyK9IFzWsMA5XN/w0dp+9JJOZIhH7hyfv+73e7YmBqpgGHMl5d15KJ2lMQy5H+tRiKhW3vRKSKtrjVMhMNwmtglGZJcbfXSx8GRistuD8m+QDbboc9QoC9e8mZFsshtYauoQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770345256; c=relaxed/simple; bh=mB/VQeTopRG+EcgiZRTx6T1rufagGKTNUPSh9htKOzU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=AWvGxFtdtuGRis0nMqrRbzJB8J4JrvLDsd4Yzpk7b/nQkUZK+LgtPnk3IxjaXSbRdQig8Et43dbr9A7c2v7yRs+jp0mErAIyH61E0t/4Hs46+3YibnQcm0KvjWyjZoB9sIpjRp5Y21HzEHISNq6HaFcFM47okd0il2HYTJKzR88= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=nebula-matrix.com; spf=pass smtp.mailfrom=nebula-matrix.com; arc=none smtp.client-ip=47.90.198.27 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=nebula-matrix.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nebula-matrix.com Received: from localhost.localdomain(mailfrom:illusion.wang@nebula-matrix.com fp:SMTPD_---.gQHg4nQ_1770344297 cluster:ay29) by smtp.aliyun-inc.com; Fri, 06 Feb 2026 10:18:18 +0800 From: "illusion.wang" To: dimon.zhao@nebula-matrix.com, illusion.wang@nebula-matrix.com, alvin.wang@nebula-matrix.com, sam.chen@nebula-matrix.com, netdev@vger.kernel.org Cc: andrew+netdev@lunn.ch, corbet@lwn.net, kuba@kernel.org, linux-doc@vger.kernel.org, lorenzo@kernel.org, pabeni@redhat.com, horms@kernel.org, vadim.fedorenko@linux.dev, lukas.bulwahn@redhat.com, edumazet@google.com, linux-kernel@vger.kernel.org (open list) Subject: [PATCH v4 net-next 07/11] net/nebula-matrix: add intr resource implementation Date: Fri, 6 Feb 2026 10:15:59 +0800 Message-ID: <20260206021608.85381-8-illusion.wang@nebula-matrix.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260206021608.85381-1-illusion.wang@nebula-matrix.com> References: <20260206021608.85381-1-illusion.wang@nebula-matrix.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MSI-X Interrupt Configuration:=C2=A0 Dynamically allocate and manage MSI-X interrupt vectors, including network interrupts and other types of interrupts. Interrupt Mapping Table Management: Maintain the MSI-X mapping table (msix_map_table) to establish interrupt associations between hardware and software. Interrupt Enabling/Disabling: Support enabling or disabling specific interrupts through hardware operations. Interrupt Information Query: Provide interfaces to obtain the hardware register addresses and data of interrupts. Signed-off-by: illusion.wang --- .../net/ethernet/nebula-matrix/nbl/Makefile | 1 + .../nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.c | 71 ++++++ .../nbl_hw_leonis/nbl_resource_leonis.c | 17 ++ .../nebula-matrix/nbl/nbl_hw/nbl_interrupt.c | 233 ++++++++++++++++++ .../nebula-matrix/nbl/nbl_hw/nbl_interrupt.h | 13 + .../nebula-matrix/nbl/nbl_hw/nbl_resource.h | 33 +++ .../nbl/nbl_include/nbl_include.h | 6 +- 7 files changed, 373 insertions(+), 1 deletion(-) create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_inter= rupt.c create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_inter= rupt.h diff --git a/drivers/net/ethernet/nebula-matrix/nbl/Makefile b/drivers/net/= ethernet/nebula-matrix/nbl/Makefile index db391bf70b20..2d1ac72352bd 100644 --- a/drivers/net/ethernet/nebula-matrix/nbl/Makefile +++ b/drivers/net/ethernet/nebula-matrix/nbl/Makefile @@ -10,6 +10,7 @@ nbl_core-objs +=3D nbl_common/nbl_common.o \ nbl_hw/nbl_hw_leonis/nbl_resource_leonis.o \ nbl_hw/nbl_hw_leonis/nbl_hw_leonis_regs.o \ nbl_hw/nbl_resource.o \ + nbl_hw/nbl_interrupt.o \ nbl_core/nbl_dispatch.o \ nbl_core/nbl_dev.o \ nbl_main.o diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nb= l_hw_leonis.c b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis= /nbl_hw_leonis.c index 867eea831c10..837a4591849d 100644 --- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_le= onis.c +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_le= onis.c @@ -6,6 +6,73 @@ =20 #include "nbl_hw_leonis.h" =20 +static void nbl_hw_enable_mailbox_irq(struct nbl_hw_mgt *hw_mgt, u16 func_= id, + bool enable_msix, u16 global_vec_id) +{ + struct nbl_mailbox_qinfo_map_table mb_qinfo_map =3D { 0 }; + + nbl_hw_rd_regs(hw_mgt, NBL_MAILBOX_QINFO_MAP_REG_ARR(func_id), + (u8 *)&mb_qinfo_map, sizeof(mb_qinfo_map)); + + if (enable_msix) { + mb_qinfo_map.msix_idx =3D global_vec_id; + mb_qinfo_map.msix_idx_valid =3D 1; + } else { + mb_qinfo_map.msix_idx =3D 0; + mb_qinfo_map.msix_idx_valid =3D 0; + } + + nbl_hw_wr_regs(hw_mgt, NBL_MAILBOX_QINFO_MAP_REG_ARR(func_id), + (u8 *)&mb_qinfo_map, sizeof(mb_qinfo_map)); +} + +static void nbl_hw_configure_msix_map(struct nbl_hw_mgt *hw_mgt, u16 func_= id, + bool valid, dma_addr_t dma_addr, u8 bus, + u8 devid, u8 function) +{ + struct nbl_function_msix_map function_msix_map =3D { 0 }; + + if (valid) { + function_msix_map.msix_map_base_addr =3D dma_addr; + /* use af's bdf, because dma memmory is alloc by af */ + function_msix_map.function =3D function; + function_msix_map.devid =3D devid; + function_msix_map.bus =3D bus; + function_msix_map.valid =3D 1; + } + + nbl_hw_wr_regs(hw_mgt, + NBL_PCOMPLETER_FUNCTION_MSIX_MAP_REG_ARR(func_id), + (u8 *)&function_msix_map, sizeof(function_msix_map)); +} + +static void nbl_hw_configure_msix_info(struct nbl_hw_mgt *hw_mgt, u16 func= _id, + bool valid, u16 interrupt_id, u8 bus, + u8 devid, u8 function, bool msix_mask_en) +{ + struct nbl_pcompleter_host_msix_fid_table host_msix_fid_table =3D { 0 }; + struct nbl_host_msix_info msix_info =3D { 0 }; + + if (valid) { + host_msix_fid_table.vld =3D 1; + host_msix_fid_table.fid =3D func_id; + + msix_info.intrl_pnum =3D 0; + msix_info.intrl_rate =3D 0; + msix_info.function =3D function; + msix_info.devid =3D devid; + msix_info.bus =3D bus; + msix_info.valid =3D 1; + if (msix_mask_en) + msix_info.msix_mask_en =3D 1; + } + + nbl_hw_wr_regs(hw_mgt, NBL_PADPT_HOST_MSIX_INFO_REG_ARR(interrupt_id), + (u8 *)&msix_info, sizeof(msix_info)); + nbl_hw_wr_regs(hw_mgt, NBL_PCOMPLETER_HOST_MSIX_FID_TABLE(interrupt_id), + (u8 *)&host_msix_fid_table, sizeof(host_msix_fid_table)); +} + static void nbl_hw_update_mailbox_queue_tail_ptr(struct nbl_hw_mgt *hw_mgt, u16 tail_ptr, u8 txrx) { @@ -138,6 +205,9 @@ static u32 nbl_hw_get_fw_eth_map(struct nbl_hw_mgt *hw_= mgt) } =20 static struct nbl_hw_ops hw_ops =3D { + .configure_msix_map =3D nbl_hw_configure_msix_map, + .configure_msix_info =3D nbl_hw_configure_msix_info, + .update_mailbox_queue_tail_ptr =3D nbl_hw_update_mailbox_queue_tail_ptr, .config_mailbox_rxq =3D nbl_hw_config_mailbox_rxq, .config_mailbox_txq =3D nbl_hw_config_mailbox_txq, @@ -147,6 +217,7 @@ static struct nbl_hw_ops hw_ops =3D { .get_real_bus =3D nbl_hw_get_real_bus, =20 .cfg_mailbox_qinfo =3D nbl_hw_cfg_mailbox_qinfo, + .enable_mailbox_irq =3D nbl_hw_enable_mailbox_irq, =20 .get_fw_eth_num =3D nbl_hw_get_fw_eth_num, .get_fw_eth_map =3D nbl_hw_get_fw_eth_map, diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nb= l_resource_leonis.c b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_= leonis/nbl_resource_leonis.c index f3753771a299..af58a3d55854 100644 --- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_resou= rce_leonis.c +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_resou= rce_leonis.c @@ -34,6 +34,7 @@ static struct nbl_resource_ops res_ops =3D { .get_eth_id =3D nbl_res_get_eth_id, }; =20 +static bool is_ops_inited; static int nbl_res_setup_res_mgt(struct nbl_common_info *common, struct nbl_resource_mgt_leonis **res_mgt_leonis) @@ -61,15 +62,27 @@ static int nbl_res_setup_ops(struct device *dev, struct nbl_resource_ops_tbl **res_ops_tbl, struct nbl_resource_mgt_leonis *res_mgt_leonis) { + int ret =3D 0; + *res_ops_tbl =3D devm_kzalloc(dev, sizeof(struct nbl_resource_ops_tbl), GFP_KERNEL); if (!*res_ops_tbl) return -ENOMEM; =20 + if (!is_ops_inited) { + ret =3D nbl_intr_setup_ops(&res_ops); + if (ret) + goto setup_fail; + is_ops_inited =3D true; + } + (*res_ops_tbl)->ops =3D &res_ops; (*res_ops_tbl)->priv =3D &res_mgt_leonis->res_mgt; =20 return 0; + +setup_fail: + return -EAGAIN; } =20 static int nbl_res_ctrl_dev_setup_eth_info(struct nbl_resource_mgt *res_mg= t) @@ -228,6 +241,10 @@ static int nbl_res_start(struct nbl_resource_mgt_leoni= s *res_mgt_leonis, ret =3D nbl_res_ctrl_dev_vsi_info_init(res_mgt); if (ret) goto start_fail; + + ret =3D nbl_intr_mgt_start(res_mgt); + if (ret) + goto start_fail; } return 0; =20 diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_interrupt.c = b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_interrupt.c new file mode 100644 index 000000000000..a526b98cd384 --- /dev/null +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_interrupt.c @@ -0,0 +1,233 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 Nebula Matrix Limited. + * Author: + */ + +#include "nbl_interrupt.h" + +static int nbl_res_intr_destroy_msix_map(struct nbl_resource_mgt *res_mgt, + u16 func_id) +{ + struct nbl_interrupt_mgt *intr_mgt =3D res_mgt->intr_mgt; + struct nbl_hw_ops *hw_ops =3D res_mgt->hw_ops_tbl->ops; + struct device *dev =3D res_mgt->common->dev; + struct nbl_msix_map_table *msix_map_table; + u16 *interrupts; + u16 intr_num, i; + + /* use ctrl dev bdf */ + hw_ops->configure_msix_map(res_mgt->hw_ops_tbl->priv, func_id, false, 0, + 0, 0, 0); + + intr_num =3D intr_mgt->func_intr_res[func_id].num_interrupts; + interrupts =3D intr_mgt->func_intr_res[func_id].interrupts; + + WARN_ON(!interrupts); + for (i =3D 0; i < intr_num; i++) { + if (interrupts[i] >=3D NBL_MAX_OTHER_INTERRUPT) + clear_bit(interrupts[i] - NBL_MAX_OTHER_INTERRUPT, + intr_mgt->interrupt_net_bitmap); + else + clear_bit(interrupts[i], + intr_mgt->interrupt_others_bitmap); + + hw_ops->configure_msix_info(res_mgt->hw_ops_tbl->priv, func_id, + false, interrupts[i], 0, 0, 0, + false); + } + + kfree(interrupts); + intr_mgt->func_intr_res[func_id].interrupts =3D NULL; + intr_mgt->func_intr_res[func_id].num_interrupts =3D 0; + + msix_map_table =3D &intr_mgt->func_intr_res[func_id].msix_map_table; + dma_free_coherent(dev, msix_map_table->size, msix_map_table->base_addr, + msix_map_table->dma); + msix_map_table->size =3D 0; + msix_map_table->base_addr =3D NULL; + msix_map_table->dma =3D 0; + + return 0; +} + +static int nbl_res_intr_configure_msix_map(struct nbl_resource_mgt *res_mg= t, + u16 func_id, u16 num_net_msix, + u16 num_others_msix, + bool net_msix_mask_en) +{ + struct nbl_interrupt_mgt *intr_mgt =3D res_mgt->intr_mgt; + struct nbl_hw_ops *hw_ops =3D res_mgt->hw_ops_tbl->ops; + struct nbl_common_info *common =3D res_mgt->common; + struct nbl_msix_map_table *msix_map_table; + struct nbl_msix_map *msix_map_entries; + struct device *dev =3D common->dev; + u16 requested, intr_index; + u8 bus, devid, function; + bool msix_mask_en; + u16 *interrupts; + int ret =3D 0; + u16 i; + + if (intr_mgt->func_intr_res[func_id].interrupts) + nbl_res_intr_destroy_msix_map(res_mgt, func_id); + + nbl_res_func_id_to_bdf(res_mgt, func_id, &bus, &devid, &function); + + msix_map_table =3D &intr_mgt->func_intr_res[func_id].msix_map_table; + WARN_ON(msix_map_table->base_addr); + msix_map_table->size =3D + sizeof(struct nbl_msix_map) * NBL_MSIX_MAP_TABLE_MAX_ENTRIES; + msix_map_table->base_addr =3D dma_alloc_coherent(dev, + msix_map_table->size, + &msix_map_table->dma, + GFP_ATOMIC | __GFP_ZERO); + if (!msix_map_table->base_addr) { + pr_err("Allocate DMA memory for function msix map table failed\n"); + msix_map_table->size =3D 0; + return -ENOMEM; + } + + requested =3D num_net_msix + num_others_msix; + interrupts =3D kcalloc(requested, sizeof(interrupts[0]), GFP_ATOMIC); + if (!interrupts) { + pr_err("Allocate function interrupts array failed\n"); + ret =3D -ENOMEM; + goto alloc_interrupts_err; + } + + intr_mgt->func_intr_res[func_id].interrupts =3D interrupts; + intr_mgt->func_intr_res[func_id].num_interrupts =3D requested; + intr_mgt->func_intr_res[func_id].num_net_interrupts =3D num_net_msix; + + for (i =3D 0; i < num_net_msix; i++) { + intr_index =3D find_first_zero_bit(intr_mgt->interrupt_net_bitmap, + NBL_MAX_NET_INTERRUPT); + if (intr_index =3D=3D NBL_MAX_NET_INTERRUPT) { + pr_err("There is no available interrupt left\n"); + ret =3D -EAGAIN; + goto get_interrupt_err; + } + interrupts[i] =3D intr_index + NBL_MAX_OTHER_INTERRUPT; + set_bit(intr_index, intr_mgt->interrupt_net_bitmap); + } + + for (i =3D num_net_msix; i < requested; i++) { + intr_index =3D + find_first_zero_bit(intr_mgt->interrupt_others_bitmap, + NBL_MAX_OTHER_INTERRUPT); + if (intr_index =3D=3D NBL_MAX_OTHER_INTERRUPT) { + pr_err("There is no available interrupt left\n"); + ret =3D -EAGAIN; + goto get_interrupt_err; + } + interrupts[i] =3D intr_index; + set_bit(intr_index, intr_mgt->interrupt_others_bitmap); + } + + msix_map_entries =3D msix_map_table->base_addr; + for (i =3D 0; i < requested; i++) { + msix_map_entries[i].global_msix_index =3D interrupts[i]; + msix_map_entries[i].valid =3D 1; + + if (i < num_net_msix && net_msix_mask_en) + msix_mask_en =3D 1; + else + msix_mask_en =3D 0; + hw_ops->configure_msix_info(res_mgt->hw_ops_tbl->priv, func_id, + true, interrupts[i], bus, devid, + function, msix_mask_en); + } + + /* use ctrl dev bdf */ + hw_ops->configure_msix_map(res_mgt->hw_ops_tbl->priv, func_id, true, + msix_map_table->dma, common->hw_bus, + common->devid, common->function); + + return 0; + +get_interrupt_err: + while (i--) { + intr_index =3D interrupts[i]; + if (intr_index >=3D NBL_MAX_OTHER_INTERRUPT) + clear_bit(intr_index - NBL_MAX_OTHER_INTERRUPT, + intr_mgt->interrupt_net_bitmap); + else + clear_bit(intr_index, + intr_mgt->interrupt_others_bitmap); + } + kfree(interrupts); + intr_mgt->func_intr_res[func_id].num_interrupts =3D 0; + intr_mgt->func_intr_res[func_id].interrupts =3D NULL; + +alloc_interrupts_err: + dma_free_coherent(dev, msix_map_table->size, msix_map_table->base_addr, + msix_map_table->dma); + msix_map_table->size =3D 0; + msix_map_table->base_addr =3D NULL; + msix_map_table->dma =3D 0; + + return ret; +} + +static int nbl_res_intr_enable_mailbox_irq(struct nbl_resource_mgt *res_mg= t, + u16 func_id, u16 vector_id, + bool enable_msix) +{ + struct nbl_interrupt_mgt *intr_mgt =3D res_mgt->intr_mgt; + struct nbl_hw_ops *hw_ops =3D res_mgt->hw_ops_tbl->ops; + u16 global_vec_id; + + global_vec_id =3D intr_mgt->func_intr_res[func_id].interrupts[vector_id]; + hw_ops->enable_mailbox_irq(res_mgt->hw_ops_tbl->priv, func_id, + enable_msix, global_vec_id); + + return 0; +} + +/* NBL_INTR_SET_OPS(ops_name, func) + * + * Use X Macros to reduce setup and remove codes. + */ +#define NBL_INTR_OPS_TBL \ +do { \ + NBL_INTR_SET_OPS(configure_msix_map, \ + nbl_res_intr_configure_msix_map); \ + NBL_INTR_SET_OPS(destroy_msix_map, \ + nbl_res_intr_destroy_msix_map); \ + NBL_INTR_SET_OPS(enable_mailbox_irq, \ + nbl_res_intr_enable_mailbox_irq); \ +} while (0) + +/* Structure starts here, adding an op should not modify anything below */ +static int nbl_intr_setup_mgt(struct device *dev, + struct nbl_interrupt_mgt **intr_mgt) +{ + *intr_mgt =3D + devm_kzalloc(dev, sizeof(struct nbl_interrupt_mgt), GFP_KERNEL); + if (!*intr_mgt) + return -ENOMEM; + + return 0; +} + +int nbl_intr_mgt_start(struct nbl_resource_mgt *res_mgt) +{ + struct nbl_interrupt_mgt **intr_mgt =3D &res_mgt->intr_mgt; + struct device *dev =3D res_mgt->common->dev; + + return nbl_intr_setup_mgt(dev, intr_mgt); +} + +int nbl_intr_setup_ops(struct nbl_resource_ops *res_ops) +{ +#define NBL_INTR_SET_OPS(name, func) \ + do { \ + res_ops->NBL_NAME(name) =3D func; \ + ; \ + } while (0) + NBL_INTR_OPS_TBL; +#undef NBL_INTR_SET_OPS + + return 0; +} diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_interrupt.h = b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_interrupt.h new file mode 100644 index 000000000000..5448bcf36416 --- /dev/null +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_interrupt.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0*/ +/* + * Copyright (c) 2025 Nebula Matrix Limited. + * Author: + */ + +#ifndef _NBL_INTERRUPT_H_ +#define _NBL_INTERRUPT_H_ + +#include "nbl_resource.h" + +#define NBL_MSIX_MAP_TABLE_MAX_ENTRIES (1024) +#endif diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_resource.h b= /drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_resource.h index 9c4595f9463c..45876ccc72a6 100644 --- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_resource.h +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_resource.h @@ -22,6 +22,37 @@ struct nbl_resource_mgt; #define NBL_RES_MGT_TO_PF_NUM(res_mgt) \ (NBL_RES_MGT_TO_RES_INFO(res_mgt)->max_pf) =20 +/* --------- INTERRUPT ---------- */ +#define NBL_MAX_OTHER_INTERRUPT 1024 +#define NBL_MAX_NET_INTERRUPT 4096 + +struct nbl_msix_map { + u16 valid:1; + u16 global_msix_index:13; + u16 rsv:2; +}; + +struct nbl_msix_map_table { + struct nbl_msix_map *base_addr; + dma_addr_t dma; + size_t size; +}; + +struct nbl_func_interrupt_resource_mng { + u16 num_interrupts; + u16 num_net_interrupts; + u16 msix_base; + u16 msix_max; + u16 *interrupts; + struct nbl_msix_map_table msix_map_table; +}; + +struct nbl_interrupt_mgt { + DECLARE_BITMAP(interrupt_net_bitmap, NBL_MAX_NET_INTERRUPT); + DECLARE_BITMAP(interrupt_others_bitmap, NBL_MAX_OTHER_INTERRUPT); + struct nbl_func_interrupt_resource_mng func_intr_res[NBL_MAX_FUNC]; +}; + /* --------- INFO ---------- */ struct nbl_sriov_info { unsigned int bdf; @@ -89,6 +120,8 @@ int nbl_res_func_id_to_pfvfid(struct nbl_resource_mgt *r= es_mgt, u16 func_id, int *pfid, int *vfid); int nbl_res_func_id_to_bdf(struct nbl_resource_mgt *res_mgt, u16 func_id, u8 *bus, u8 *dev, u8 *function); +int nbl_intr_mgt_start(struct nbl_resource_mgt *res_mgt); +int nbl_intr_setup_ops(struct nbl_resource_ops *resource_ops); void nbl_res_pf_dev_vsi_type_to_hw_vsi_type(u16 src_type, enum nbl_vsi_serv_type *dst_type); #endif diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_include= .h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_include.h index 659f8fb84406..21fd0c09f654 100644 --- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_include.h +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_include.h @@ -11,14 +11,18 @@ #include /* ------ Basic definitions ------- */ #define NBL_DRIVER_NAME "nbl_core" - #define NBL_MAX_PF 8 #define NBL_NEXT_ID(id, max) \ ({ \ typeof(id) _id =3D (id); \ ((_id) =3D=3D (max) ? 0 : (_id) + 1); \ }) + #define NBL_MAX_FUNC (520) + +/* Used for macros to pass checkpatch */ +#define NBL_NAME(x) x + enum nbl_product_type { NBL_LEONIS_TYPE, NBL_PRODUCT_MAX, --=20 2.47.3 From nobody Sun Feb 8 00:11:39 2026 Received: from out198-10.us.a.mail.aliyun.com (out198-10.us.a.mail.aliyun.com [47.90.198.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0B67F2376FD; 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dmarc=none (p=none dis=none) header.from=nebula-matrix.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nebula-matrix.com Received: from localhost.localdomain(mailfrom:illusion.wang@nebula-matrix.com fp:SMTPD_---.gQHg4os_1770344298 cluster:ay29) by smtp.aliyun-inc.com; Fri, 06 Feb 2026 10:18:19 +0800 From: "illusion.wang" To: dimon.zhao@nebula-matrix.com, illusion.wang@nebula-matrix.com, alvin.wang@nebula-matrix.com, sam.chen@nebula-matrix.com, netdev@vger.kernel.org Cc: andrew+netdev@lunn.ch, corbet@lwn.net, kuba@kernel.org, linux-doc@vger.kernel.org, lorenzo@kernel.org, pabeni@redhat.com, horms@kernel.org, vadim.fedorenko@linux.dev, lukas.bulwahn@redhat.com, edumazet@google.com, linux-kernel@vger.kernel.org (open list) Subject: [PATCH v4 net-next 08/11] net/nebula-matrix: add vsi resource implementation Date: Fri, 6 Feb 2026 10:16:00 +0800 Message-ID: <20260206021608.85381-9-illusion.wang@nebula-matrix.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260206021608.85381-1-illusion.wang@nebula-matrix.com> References: <20260206021608.85381-1-illusion.wang@nebula-matrix.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The HW (Hardware) layer code can have a quick review since it is highly chip-specific. Chip initialization includes the initialization of the DP module, the intf module, and the P4 registers. The initialization of the DP module encompasses the initialization of the dped(downstream pkt edit), uped(upstream pkt edit), dsch(downstream schedule), ustore, dstore, dvn, uvn, and uqm modules. Signed-off-by: illusion.wang --- .../net/ethernet/nebula-matrix/nbl/Makefile | 1 + .../nbl/nbl_hw/nbl_hw_leonis/nbl_hw_leonis.c | 407 ++++++++++++++++++ .../nbl_hw_leonis/nbl_resource_leonis.c | 6 +- .../nebula-matrix/nbl/nbl_hw/nbl_resource.h | 1 + .../nebula-matrix/nbl/nbl_hw/nbl_vsi.c | 54 +++ .../nebula-matrix/nbl/nbl_hw/nbl_vsi.h | 12 + .../nbl/nbl_include/nbl_def_hw.h | 4 + .../nbl/nbl_include/nbl_include.h | 31 ++ 8 files changed, 514 insertions(+), 2 deletions(-) create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_vsi.c create mode 100644 drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_vsi.h diff --git a/drivers/net/ethernet/nebula-matrix/nbl/Makefile b/drivers/net/= ethernet/nebula-matrix/nbl/Makefile index 2d1ac72352bd..5c07fd65ad32 100644 --- a/drivers/net/ethernet/nebula-matrix/nbl/Makefile +++ b/drivers/net/ethernet/nebula-matrix/nbl/Makefile @@ -11,6 +11,7 @@ nbl_core-objs +=3D nbl_common/nbl_common.o \ nbl_hw/nbl_hw_leonis/nbl_hw_leonis_regs.o \ nbl_hw/nbl_resource.o \ nbl_hw/nbl_interrupt.o \ + nbl_hw/nbl_vsi.o \ nbl_core/nbl_dispatch.o \ nbl_core/nbl_dev.o \ nbl_main.o diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nb= l_hw_leonis.c b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis= /nbl_hw_leonis.c index 837a4591849d..a34dad884b47 100644 --- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_le= onis.c +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_hw_le= onis.c @@ -5,6 +5,410 @@ */ =20 #include "nbl_hw_leonis.h" +#include "nbl_hw_leonis_regs.h" + +static u32 nbl_hw_get_quirks(struct nbl_hw_mgt *hw_mgt) +{ + u32 quirks; + + nbl_hw_read_mbx_regs(hw_mgt, NBL_LEONIS_QUIRKS_OFFSET, (u8 *)&quirks, + sizeof(u32)); + + if (quirks =3D=3D NBL_LEONIS_ILLEGAL_REG_VALUE) + return 0; + + return quirks; +} + +static void nbl_configure_dped_checksum(struct nbl_hw_mgt *hw_mgt) +{ + union dped_l4_ck_cmd_40_u l4_ck_cmd_40; + + /* DPED dped_l4_ck_cmd_40 for sctp */ + nbl_hw_rd_regs(hw_mgt, NBL_DPED_L4_CK_CMD_40_ADDR, (u8 *)&l4_ck_cmd_40, + sizeof(l4_ck_cmd_40)); + l4_ck_cmd_40.info.en =3D 1; + nbl_hw_wr_regs(hw_mgt, NBL_DPED_L4_CK_CMD_40_ADDR, (u8 *)&l4_ck_cmd_40, + sizeof(l4_ck_cmd_40)); +} + +static int nbl_dped_init(struct nbl_hw_mgt *hw_mgt) +{ + nbl_hw_wr32(hw_mgt, NBL_DPED_VLAN_OFFSET, 0xC); + nbl_hw_wr32(hw_mgt, NBL_DPED_DSCP_OFFSET_0, 0x8); + nbl_hw_wr32(hw_mgt, NBL_DPED_DSCP_OFFSET_1, 0x4); + + // dped checksum offload + nbl_configure_dped_checksum(hw_mgt); + + return 0; +} + +static int nbl_uped_init(struct nbl_hw_mgt *hw_mgt) +{ + struct ped_hw_edit_profile hw_edit; + + nbl_hw_rd_regs(hw_mgt, NBL_UPED_HW_EDT_PROF_TABLE(5), (u8 *)&hw_edit, + sizeof(hw_edit)); + hw_edit.l3_len =3D 0; + nbl_hw_wr_regs(hw_mgt, NBL_UPED_HW_EDT_PROF_TABLE(5), (u8 *)&hw_edit, + sizeof(hw_edit)); + + nbl_hw_rd_regs(hw_mgt, NBL_UPED_HW_EDT_PROF_TABLE(6), (u8 *)&hw_edit, + sizeof(hw_edit)); + hw_edit.l3_len =3D 1; + nbl_hw_wr_regs(hw_mgt, NBL_UPED_HW_EDT_PROF_TABLE(6), (u8 *)&hw_edit, + sizeof(hw_edit)); + + return 0; +} + +static void nbl_shaping_eth_init(struct nbl_hw_mgt *hw_mgt, u8 eth_id, u8 = speed) +{ + struct nbl_shaping_dvn_dport dvn_dport =3D { 0 }; + struct nbl_shaping_dport dport =3D { 0 }; + u32 rate, half_rate; + + if (speed =3D=3D NBL_FW_PORT_SPEED_100G) { + rate =3D NBL_SHAPING_DPORT_100G_RATE; + half_rate =3D NBL_SHAPING_DPORT_HALF_100G_RATE; + } else { + rate =3D NBL_SHAPING_DPORT_25G_RATE; + half_rate =3D NBL_SHAPING_DPORT_HALF_25G_RATE; + } + + dport.cir =3D rate; + dport.pir =3D rate; + dport.depth =3D max(dport.cir * 2, NBL_LR_LEONIS_NET_BUCKET_DEPTH); + dport.cbs =3D dport.depth; + dport.pbs =3D dport.depth; + dport.valid =3D 1; + + dvn_dport.cir =3D half_rate; + dvn_dport.pir =3D rate; + dvn_dport.depth =3D dport.depth; + dvn_dport.cbs =3D dvn_dport.depth; + dvn_dport.pbs =3D dvn_dport.depth; + dvn_dport.valid =3D 1; + + nbl_hw_wr_regs(hw_mgt, NBL_SHAPING_DPORT_REG(eth_id), (u8 *)&dport, + sizeof(dport)); + nbl_hw_wr_regs(hw_mgt, NBL_SHAPING_DVN_DPORT_REG(eth_id), + (u8 *)&dvn_dport, sizeof(dvn_dport)); +} + +static int nbl_shaping_init(struct nbl_hw_mgt *hw_mgt, u8 speed) +{ +#define NBL_SHAPING_FLUSH_INTERVAL 128 + struct nbl_shaping_net net_shaping =3D { 0 }; + struct dsch_psha_en psha_en =3D { 0 }; + int i; + + for (i =3D 0; i < NBL_MAX_ETHERNET; i++) + nbl_shaping_eth_init(hw_mgt, i, speed); + + psha_en.en =3D 0xF; + nbl_hw_wr_regs(hw_mgt, NBL_DSCH_PSHA_EN_ADDR, (u8 *)&psha_en, + sizeof(psha_en)); + + for (i =3D 0; i < NBL_MAX_FUNC; i++) { + nbl_hw_wr_regs(hw_mgt, NBL_SHAPING_NET_REG(i), + (u8 *)&net_shaping, sizeof(net_shaping)); + if ((i % NBL_SHAPING_FLUSH_INTERVAL) =3D=3D 0) + nbl_flush_writes(hw_mgt); + } + nbl_flush_writes(hw_mgt); + return 0; +} + +static int nbl_dsch_qid_max_init(struct nbl_hw_mgt *hw_mgt) +{ + struct dsch_vn_quanta quanta =3D { 0 }; + + quanta.h_qua =3D NBL_HOST_QUANTA; + quanta.e_qua =3D NBL_ECPU_QUANTA; + nbl_hw_wr_regs(hw_mgt, NBL_DSCH_VN_QUANTA_ADDR, (u8 *)&quanta, + sizeof(quanta)); + nbl_hw_wr32(hw_mgt, NBL_DSCH_HOST_QID_MAX, NBL_MAX_QUEUE_ID); + + nbl_hw_wr32(hw_mgt, NBL_DVN_ECPU_QUEUE_NUM, 0); + nbl_hw_wr32(hw_mgt, NBL_UVN_ECPU_QUEUE_NUM, 0); + + return 0; +} + +static int nbl_ustore_init(struct nbl_hw_mgt *hw_mgt, u8 eth_num) +{ + struct nbl_ustore_port_drop_th drop_th; + struct ustore_pkt_len pkt_len; + int i; + + nbl_hw_rd_regs(hw_mgt, NBL_USTORE_PKT_LEN_ADDR, (u8 *)&pkt_len, + sizeof(pkt_len)); + /* min arp packet length 42 (14 + 28) */ + pkt_len.min =3D 42; + nbl_hw_wr_regs(hw_mgt, NBL_USTORE_PKT_LEN_ADDR, (u8 *)&pkt_len, + sizeof(pkt_len)); + + drop_th.en =3D 1; + if (eth_num =3D=3D 1) + drop_th.disc_th =3D NBL_USTORE_SIGNLE_ETH_DROP_TH; + else if (eth_num =3D=3D 2) + drop_th.disc_th =3D NBL_USTORE_DUAL_ETH_DROP_TH; + else + drop_th.disc_th =3D NBL_USTORE_QUAD_ETH_DROP_TH; + + for (i =3D 0; i < 4; i++) + nbl_hw_wr_regs(hw_mgt, NBL_USTORE_PORT_DROP_TH_REG_ARR(i), + (u8 *)&drop_th, sizeof(drop_th)); + + for (i =3D 0; i < NBL_MAX_ETHERNET; i++) { + nbl_hw_rd32(hw_mgt, NBL_USTORE_BUF_PORT_DROP_PKT(i)); + nbl_hw_rd32(hw_mgt, NBL_USTORE_BUF_PORT_TRUN_PKT(i)); + } + + return 0; +} + +static int nbl_dstore_init(struct nbl_hw_mgt *hw_mgt, u8 speed) +{ + struct dstore_port_drop_th drop_th; + struct dstore_d_dport_fc_th fc_th; + struct dstore_disc_bp_th bp_th; + int i; + + for (i =3D 0; i < 6; i++) { + nbl_hw_rd_regs(hw_mgt, NBL_DSTORE_PORT_DROP_TH_REG(i), + (u8 *)&drop_th, sizeof(drop_th)); + drop_th.en =3D 0; + nbl_hw_wr_regs(hw_mgt, NBL_DSTORE_PORT_DROP_TH_REG(i), + (u8 *)&drop_th, sizeof(drop_th)); + } + + nbl_hw_rd_regs(hw_mgt, NBL_DSTORE_DISC_BP_TH, (u8 *)&bp_th, + sizeof(bp_th)); + bp_th.en =3D 1; + nbl_hw_wr_regs(hw_mgt, NBL_DSTORE_DISC_BP_TH, (u8 *)&bp_th, + sizeof(bp_th)); + + for (i =3D 0; i < 4; i++) { + nbl_hw_rd_regs(hw_mgt, NBL_DSTORE_D_DPORT_FC_TH_REG(i), + (u8 *)&fc_th, sizeof(fc_th)); + if (speed =3D=3D NBL_FW_PORT_SPEED_100G) { + fc_th.xoff_th =3D NBL_DSTORE_DROP_XOFF_TH_100G; + fc_th.xon_th =3D NBL_DSTORE_DROP_XON_TH_100G; + } else { + fc_th.xoff_th =3D NBL_DSTORE_DROP_XOFF_TH; + fc_th.xon_th =3D NBL_DSTORE_DROP_XON_TH; + } + + fc_th.fc_en =3D 1; + nbl_hw_wr_regs(hw_mgt, NBL_DSTORE_D_DPORT_FC_TH_REG(i), + (u8 *)&fc_th, sizeof(fc_th)); + } + + return 0; +} + +static void nbl_dvn_descreq_num_cfg(struct nbl_hw_mgt *hw_mgt, u32 descreq= _num) +{ + u32 split_ring_prefect_num =3D (descreq_num >> 16) & 0xffff; + u32 packet_ring_prefect_num =3D descreq_num & 0xffff; + struct nbl_dvn_descreq_num_cfg num_cfg =3D { 0 }; + + packet_ring_prefect_num =3D + packet_ring_prefect_num > 32 ? 32 : packet_ring_prefect_num; + packet_ring_prefect_num =3D + packet_ring_prefect_num < 8 ? 8 : packet_ring_prefect_num; + num_cfg.packed_l1_num =3D (packet_ring_prefect_num - 8) / 4; + + split_ring_prefect_num =3D + split_ring_prefect_num > 16 ? 16 : split_ring_prefect_num; + split_ring_prefect_num =3D + split_ring_prefect_num < 8 ? 8 : split_ring_prefect_num; + num_cfg.avring_cfg_num =3D split_ring_prefect_num > 8 ? 1 : 0; + + nbl_hw_wr_regs(hw_mgt, NBL_DVN_DESCREQ_NUM_CFG, (u8 *)&num_cfg, + sizeof(num_cfg)); +} + +static int nbl_dvn_init(struct nbl_hw_mgt *hw_mgt, u8 speed) +{ + struct nbl_dvn_desc_wr_merge_timeout timeout =3D { 0 }; + struct nbl_dvn_dif_req_rd_ro_flag ro_flag =3D { 0 }; + + timeout.cfg_cycle =3D DEFAULT_DVN_DESC_WR_MERGE_TIMEOUT_MAX; + nbl_hw_wr_regs(hw_mgt, NBL_DVN_DESC_WR_MERGE_TIMEOUT, (u8 *)&timeout, + sizeof(timeout)); + + ro_flag.rd_desc_ro_en =3D 1; + ro_flag.rd_data_ro_en =3D 1; + ro_flag.rd_avring_ro_en =3D 1; + nbl_hw_wr_regs(hw_mgt, NBL_DVN_DIF_REQ_RD_RO_FLAG, (u8 *)&ro_flag, + sizeof(ro_flag)); + + if (speed =3D=3D NBL_FW_PORT_SPEED_100G) + nbl_dvn_descreq_num_cfg(hw_mgt, + DEFAULT_DVN_100G_DESCREQ_NUMCFG); + else + nbl_dvn_descreq_num_cfg(hw_mgt, DEFAULT_DVN_DESCREQ_NUMCFG); + + return 0; +} + +static int nbl_uvn_init(struct nbl_hw_mgt *hw_mgt) +{ + struct uvn_desc_prefetch_init prefetch_init =3D { 0 }; + struct uvn_desc_wr_timeout desc_wr_timeout =3D { 0 }; + struct uvn_dif_req_ro_flag flag =3D { 0 }; + struct uvn_queue_err_mask mask =3D { 0 }; + u16 wr_timeout =3D 0x12c; + u32 timeout =3D 119760; /* 200us 200000/1.67 */ + u32 quirks; + + nbl_hw_wr32(hw_mgt, NBL_UVN_DESC_RD_WAIT, timeout); + + desc_wr_timeout.num =3D wr_timeout; + nbl_hw_wr_regs(hw_mgt, NBL_UVN_DESC_WR_TIMEOUT, (u8 *)&desc_wr_timeout, + sizeof(desc_wr_timeout)); + + flag.avail_rd =3D 1; + flag.desc_rd =3D 1; + flag.pkt_wr =3D 1; + flag.desc_wr =3D 0; + nbl_hw_wr_regs(hw_mgt, NBL_UVN_DIF_REQ_RO_FLAG, (u8 *)&flag, + sizeof(flag)); + + nbl_hw_rd_regs(hw_mgt, NBL_UVN_QUEUE_ERR_MASK, (u8 *)&mask, + sizeof(mask)); + mask.dif_err =3D 1; + nbl_hw_wr_regs(hw_mgt, NBL_UVN_QUEUE_ERR_MASK, (u8 *)&mask, + sizeof(mask)); + + prefetch_init.num =3D NBL_UVN_DESC_PREFETCH_NUM; + prefetch_init.sel =3D 0; + quirks =3D nbl_hw_get_quirks(hw_mgt); + if (!(quirks & BIT(NBL_QUIRKS_UVN_PREFETCH_ALIGN))) + prefetch_init.sel =3D 1; + nbl_hw_wr_regs(hw_mgt, NBL_UVN_DESC_PREFETCH_INIT, (u8 *)&prefetch_init, + sizeof(prefetch_init)); + + return 0; +} + +static int nbl_uqm_init(struct nbl_hw_mgt *hw_mgt) +{ + struct nbl_uqm_que_type que_type =3D { 0 }; + u32 cnt =3D 0; + int i; + + nbl_hw_wr_regs(hw_mgt, NBL_UQM_FWD_DROP_CNT, (u8 *)&cnt, sizeof(cnt)); + + nbl_hw_wr_regs(hw_mgt, NBL_UQM_DROP_PKT_CNT, (u8 *)&cnt, sizeof(cnt)); + nbl_hw_wr_regs(hw_mgt, NBL_UQM_DROP_PKT_SLICE_CNT, (u8 *)&cnt, + sizeof(cnt)); + nbl_hw_wr_regs(hw_mgt, NBL_UQM_DROP_PKT_LEN_ADD_CNT, (u8 *)&cnt, + sizeof(cnt)); + nbl_hw_wr_regs(hw_mgt, NBL_UQM_DROP_HEAD_PNTR_ADD_CNT, (u8 *)&cnt, + sizeof(cnt)); + nbl_hw_wr_regs(hw_mgt, NBL_UQM_DROP_WEIGHT_ADD_CNT, (u8 *)&cnt, + sizeof(cnt)); + + for (i =3D 0; i < NBL_UQM_PORT_DROP_DEPTH; i++) { + nbl_hw_wr_regs(hw_mgt, + NBL_UQM_PORT_DROP_PKT_CNT + (sizeof(cnt) * i), + (u8 *)&cnt, sizeof(cnt)); + nbl_hw_wr_regs(hw_mgt, + NBL_UQM_PORT_DROP_PKT_SLICE_CNT + + (sizeof(cnt) * i), + (u8 *)&cnt, sizeof(cnt)); + nbl_hw_wr_regs(hw_mgt, + NBL_UQM_PORT_DROP_PKT_LEN_ADD_CNT + + (sizeof(cnt) * i), + (u8 *)&cnt, sizeof(cnt)); + nbl_hw_wr_regs(hw_mgt, + NBL_UQM_PORT_DROP_HEAD_PNTR_ADD_CNT + + (sizeof(cnt) * i), + (u8 *)&cnt, sizeof(cnt)); + nbl_hw_wr_regs(hw_mgt, + NBL_UQM_PORT_DROP_WEIGHT_ADD_CNT + + (sizeof(cnt) * i), + (u8 *)&cnt, sizeof(cnt)); + } + + for (i =3D 0; i < NBL_UQM_DPORT_DROP_DEPTH; i++) + nbl_hw_wr_regs(hw_mgt, + NBL_UQM_DPORT_DROP_CNT + (sizeof(cnt) * i), + (u8 *)&cnt, sizeof(cnt)); + + que_type.bp_drop =3D 0; + nbl_hw_wr_regs(hw_mgt, NBL_UQM_QUE_TYPE, (u8 *)&que_type, + sizeof(que_type)); + + return 0; +} + +static int nbl_dp_init(struct nbl_hw_mgt *hw_mgt, u8 speed, u8 eth_num) +{ + nbl_dped_init(hw_mgt); + nbl_uped_init(hw_mgt); + nbl_shaping_init(hw_mgt, speed); + nbl_dsch_qid_max_init(hw_mgt); + nbl_ustore_init(hw_mgt, eth_num); + nbl_dstore_init(hw_mgt, speed); + nbl_dvn_init(hw_mgt, speed); + nbl_uvn_init(hw_mgt); + nbl_uqm_init(hw_mgt); + + return 0; +} + +static int nbl_host_padpt_init(struct nbl_hw_mgt *hw_mgt) +{ + /* padpt flow control register */ + nbl_hw_wr32(hw_mgt, NBL_HOST_PADPT_HOST_CFG_FC_CPLH_UP, 0x10400); + nbl_hw_wr32(hw_mgt, NBL_HOST_PADPT_HOST_CFG_FC_PD_DN, 0x10080); + nbl_hw_wr32(hw_mgt, NBL_HOST_PADPT_HOST_CFG_FC_PH_DN, 0x10010); + nbl_hw_wr32(hw_mgt, NBL_HOST_PADPT_HOST_CFG_FC_NPH_DN, 0x10010); + + return 0; +} + +static int nbl_intf_init(struct nbl_hw_mgt *hw_mgt) +{ + nbl_host_padpt_init(hw_mgt); + return 0; +} + +static void nbl_hw_set_driver_status(struct nbl_hw_mgt *hw_mgt, bool activ= e) +{ + u32 status =3D 0; + + status =3D nbl_hw_rd32(hw_mgt, NBL_DRIVER_STATUS_REG); + + status =3D (status & ~(1 << NBL_DRIVER_STATUS_BIT)) | + (active << NBL_DRIVER_STATUS_BIT); + + nbl_hw_wr32(hw_mgt, NBL_DRIVER_STATUS_REG, status); +} + +static void nbl_hw_deinit_chip_module(struct nbl_hw_mgt *hw_mgt) +{ + nbl_hw_set_driver_status(hw_mgt, false); +} + +static int nbl_hw_init_chip_module(struct nbl_hw_mgt *hw_mgt, u8 eth_speed, + u8 eth_num) +{ + nbl_dp_init(hw_mgt, eth_speed, eth_num); + nbl_intf_init(hw_mgt); + + nbl_write_all_regs(hw_mgt); + nbl_hw_set_driver_status(hw_mgt, true); + hw_mgt->version =3D nbl_hw_rd32(hw_mgt, NBL_HW_DUMMY_REG); + + return 0; +} =20 static void nbl_hw_enable_mailbox_irq(struct nbl_hw_mgt *hw_mgt, u16 func_= id, bool enable_msix, u16 global_vec_id) @@ -205,6 +609,9 @@ static u32 nbl_hw_get_fw_eth_map(struct nbl_hw_mgt *hw_= mgt) } =20 static struct nbl_hw_ops hw_ops =3D { + .init_chip_module =3D nbl_hw_init_chip_module, + .deinit_chip_module =3D nbl_hw_deinit_chip_module, + .configure_msix_map =3D nbl_hw_configure_msix_map, .configure_msix_info =3D nbl_hw_configure_msix_info, =20 diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nb= l_resource_leonis.c b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_= leonis/nbl_resource_leonis.c index af58a3d55854..b7c0dd4c20c5 100644 --- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_resou= rce_leonis.c +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_hw_leonis/nbl_resou= rce_leonis.c @@ -71,6 +71,10 @@ static int nbl_res_setup_ops(struct device *dev, =20 if (!is_ops_inited) { ret =3D nbl_intr_setup_ops(&res_ops); + if (ret) + goto setup_fail; + + ret =3D nbl_vsi_setup_ops(&res_ops); if (ret) goto setup_fail; is_ops_inited =3D true; @@ -262,7 +266,6 @@ int nbl_res_init_leonis(struct nbl_adapter *adap, struc= t nbl_init_param *param) struct nbl_resource_mgt_leonis **mgt =3D (struct nbl_resource_mgt_leonis **)&NBL_ADAP_TO_RES_MGT(adap); struct device *dev =3D &adap->pdev->dev; - int ret =3D 0; =20 ret =3D nbl_res_setup_res_mgt(common, mgt); @@ -279,7 +282,6 @@ int nbl_res_init_leonis(struct nbl_adapter *adap, struc= t nbl_init_param *param) ret =3D nbl_res_setup_ops(dev, res_ops_tbl, *mgt); if (ret) goto setup_ops_fail; - return 0; =20 setup_ops_fail: diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_resource.h b= /drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_resource.h index 45876ccc72a6..d4a1096a25f6 100644 --- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_resource.h +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_resource.h @@ -122,6 +122,7 @@ int nbl_res_func_id_to_bdf(struct nbl_resource_mgt *res= _mgt, u16 func_id, u8 *bus, u8 *dev, u8 *function); int nbl_intr_mgt_start(struct nbl_resource_mgt *res_mgt); int nbl_intr_setup_ops(struct nbl_resource_ops *resource_ops); +int nbl_vsi_setup_ops(struct nbl_resource_ops *resource_ops); void nbl_res_pf_dev_vsi_type_to_hw_vsi_type(u16 src_type, enum nbl_vsi_serv_type *dst_type); #endif diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_vsi.c b/driv= ers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_vsi.c new file mode 100644 index 000000000000..df879e6976d7 --- /dev/null +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_vsi.c @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 Nebula Matrix Limited. + * Author: + */ + +#include "nbl_vsi.h" + +static void nbl_res_vsi_deinit_chip_module(struct nbl_resource_mgt *res_mg= t) +{ + struct nbl_hw_ops *hw_ops; + + hw_ops =3D res_mgt->hw_ops_tbl->ops; + + hw_ops->deinit_chip_module(res_mgt->hw_ops_tbl->priv); +} + +static int nbl_res_vsi_init_chip_module(struct nbl_resource_mgt *res_mgt) +{ + u8 eth_speed =3D res_mgt->resource_info->board_info.eth_speed; + u8 eth_num =3D res_mgt->resource_info->board_info.eth_num; + struct nbl_hw_ops *hw_ops =3D res_mgt->hw_ops_tbl->ops; + struct nbl_hw_mgt *p =3D res_mgt->hw_ops_tbl->priv; + int ret =3D 0; + + ret =3D hw_ops->init_chip_module(p, eth_speed, eth_num); + + return ret; +} + +/* NBL_VSI_SET_OPS(ops_name, func) + * + * Use X Macros to reduce setup and remove codes. + */ +#define NBL_VSI_OPS_TBL \ +do { \ + NBL_VSI_SET_OPS(init_chip_module, \ + nbl_res_vsi_init_chip_module); \ + NBL_VSI_SET_OPS(deinit_chip_module, \ + nbl_res_vsi_deinit_chip_module); \ +} while (0) + +int nbl_vsi_setup_ops(struct nbl_resource_ops *res_ops) +{ +#define NBL_VSI_SET_OPS(name, func) \ + do { \ + res_ops->NBL_NAME(name) =3D func; \ + ; \ + } while (0) + NBL_VSI_OPS_TBL; +#undef NBL_VSI_SET_OPS + + return 0; +} diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_vsi.h b/driv= ers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_vsi.h new file mode 100644 index 000000000000..94831e00b89a --- /dev/null +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_hw/nbl_vsi.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0*/ +/* + * Copyright (c) 2025 Nebula Matrix Limited. + * Author: + */ + +#ifndef _NBL_VSI_H_ +#define _NBL_VSI_H_ + +#include "nbl_resource.h" + +#endif diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_hw.= h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_hw.h index 80b152cad1b0..633bbc574aee 100644 --- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_hw.h +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_hw.h @@ -10,6 +10,10 @@ #include "nbl_include.h" struct nbl_hw_mgt; struct nbl_hw_ops { + int (*init_chip_module)(struct nbl_hw_mgt *hw_mgt, u8 eth_speed, + u8 eth_num); + void (*deinit_chip_module)(struct nbl_hw_mgt *hw_mgt); + void (*configure_msix_map)(struct nbl_hw_mgt *hw_mgt, u16 func_id, bool valid, dma_addr_t dma_addr, u8 bus, u8 devid, u8 function); diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_include= .h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_include.h index 21fd0c09f654..d4c7faaee844 100644 --- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_include.h +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_include.h @@ -47,4 +47,35 @@ struct nbl_init_param { bool pci_using_dac; }; =20 +enum nbl_fw_port_speed { + NBL_FW_PORT_SPEED_10G, + NBL_FW_PORT_SPEED_25G, + NBL_FW_PORT_SPEED_50G, + NBL_FW_PORT_SPEED_100G, +}; + +#define NBL_OPS_CALL(func, para) \ +do { \ + typeof(func) _func =3D (func); \ + if (_func) \ + _func para; \ +} while (0) + +#define NBL_OPS_CALL_RET(func, para) \ +({ \ + typeof(func) _func =3D (func); \ + _func ? _func para : 0; \ +}) + +#define NBL_OPS_CALL_RET_PTR(func, para) \ +({ \ + typeof(func) _func =3D (func); \ + _func ? _func para : NULL; \ +}) + +enum nbl_performance_mode { + NBL_QUIRKS_NO_TOE, + NBL_QUIRKS_UVN_PREFETCH_ALIGN, +}; + #endif --=20 2.47.3 From nobody Sun Feb 8 00:11:39 2026 Received: from out198-6.us.a.mail.aliyun.com (out198-6.us.a.mail.aliyun.com [47.90.198.6]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F5751AF4D5; Fri, 6 Feb 2026 02:18:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=47.90.198.6 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770344320; cv=none; b=liM7ydL8FTdaP1G34q0Cdjm0BeKI9Ym8M5I7fD6AZo7MsdxZDQ62vpjSyzxpsoNL1mNz+YADdNMi7DyD4Xkmd1KOhJIH5bVy0tJpCooBveA1z5R8BzkV1C7tAyCvxZkj9hecDmWXdQyw4s1FnLZRWmNJ+7AtgHRO3XOagLdSe8c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770344320; c=relaxed/simple; bh=x09YvlCyKoxRiiem8kfRgdH+CeLHmvrdYo9YVX3iIoI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=A2ohpVqOgqUeN2yQPVfApPzxSjYq09nomSnU07oH6iqP5TyEoF+Kcdugk0KE5WHbPeCNCjQAlg3DuiaOwwgQJjb8t7BGyi0GHb1YiIofXpLdvSFwtpG34+fxMDYzGLpELU+RpECM+UWruYQk9LjCyMy+pTb4dvHHI9VujrKzzzA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=nebula-matrix.com; spf=pass smtp.mailfrom=nebula-matrix.com; arc=none smtp.client-ip=47.90.198.6 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=nebula-matrix.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nebula-matrix.com Received: from localhost.localdomain(mailfrom:illusion.wang@nebula-matrix.com fp:SMTPD_---.gQHg4qb_1770344299 cluster:ay29) by smtp.aliyun-inc.com; Fri, 06 Feb 2026 10:18:20 +0800 From: "illusion.wang" To: dimon.zhao@nebula-matrix.com, illusion.wang@nebula-matrix.com, alvin.wang@nebula-matrix.com, sam.chen@nebula-matrix.com, netdev@vger.kernel.org Cc: andrew+netdev@lunn.ch, corbet@lwn.net, kuba@kernel.org, linux-doc@vger.kernel.org, lorenzo@kernel.org, pabeni@redhat.com, horms@kernel.org, vadim.fedorenko@linux.dev, lukas.bulwahn@redhat.com, edumazet@google.com, linux-kernel@vger.kernel.org (open list) Subject: [PATCH v4 net-next 09/11] net/nebula-matrix: add Dispatch layer implementation Date: Fri, 6 Feb 2026 10:16:01 +0800 Message-ID: <20260206021608.85381-10-illusion.wang@nebula-matrix.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260206021608.85381-1-illusion.wang@nebula-matrix.com> References: <20260206021608.85381-1-illusion.wang@nebula-matrix.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This patch can have a quick review, function is similar The primary issue in the Dispatch layer is how to determine the routing approach Two routing ways: Dispatch Layer-> Resource Layer -> HW layer The Dispatch Layer routes tasks to Resource Layer, which may interact with the HW Layer for hardware writes. Dispatch Layer->Channel Layer The Dispatch Layers redirects hooks to the Channel Layer. The primary challenge at the Dispatch layer lies in determining the routing approach, namely, how to decide which interfaces should directly invoke the Resource layer's interfaces and which should transmit requests via channels to the management PF for processing. To address this, a ctrl_lvl (control level) mechanism is established, which comprises two parts: the control level declared by each interface and the control level configured by the upper layer. The effect is that when the upper layer configures a specific control level, all interfaces declaring this level will directly call the Resource layer's interfaces; otherwise, they will send requests via channels. For instance, consider a regular PF that possesses network (net) capabilities but lacks control (ctrl) capabilities. It will only configure NET_LVL at the Dispatch layer. In this scenario, all interfaces declaring NET_LVL will directly invoke the Resource layer's interfaces, while those declaring CTRL_LVL will send requests via channels to the management PF. Conversely, if it is the management PF, it will configure both NET_LVL and CTRL_LVL at the Dispatch layer. Consequently, interfaces declaring CTRL_LVL will also directly call the Resource layer's interfaces without sending requests via channels. This configuration logic can be dynamic.(nbl_disp_setup_ctrl_lvl) Signed-off-by: illusion.wang --- .../nebula-matrix/nbl/nbl_core/nbl_dispatch.c | 417 ++++++++++++++++++ .../nebula-matrix/nbl/nbl_core/nbl_dispatch.h | 29 ++ .../nbl/nbl_include/nbl_def_dispatch.h | 12 + 3 files changed, 458 insertions(+) diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dispatch.c= b/drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dispatch.c index e326c59b9999..f89999224d98 100644 --- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dispatch.c +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dispatch.c @@ -6,6 +6,400 @@ =20 #include "nbl_dispatch.h" =20 +static u16 nbl_disp_chan_get_vsi_id_req(struct nbl_dispatch_mgt *disp_mgt, + u16 func_id, u16 type) +{ + struct nbl_channel_ops *chan_ops =3D disp_mgt->chan_ops_tbl->ops; + struct nbl_common_info *common =3D disp_mgt->common; + struct nbl_chan_param_get_vsi_id result =3D { 0 }; + struct nbl_chan_param_get_vsi_id param =3D { 0 }; + struct nbl_chan_send_info chan_send; + + param.type =3D type; + + NBL_CHAN_SEND(chan_send, common->mgt_pf, NBL_CHAN_MSG_GET_VSI_ID, + ¶m, sizeof(param), &result, sizeof(result), 1); + chan_ops->send_msg(disp_mgt->chan_ops_tbl->priv, &chan_send); + + return result.vsi_id; +} + +static void nbl_disp_chan_get_vsi_id_resp(void *priv, u16 src_id, u16 msg_= id, + void *data, u32 data_len) +{ + struct nbl_dispatch_mgt *disp_mgt =3D (struct nbl_dispatch_mgt *)priv; + struct nbl_channel_ops *chan_ops =3D disp_mgt->chan_ops_tbl->ops; + struct nbl_resource_ops *res_ops =3D disp_mgt->res_ops_tbl->ops; + struct nbl_resource_mgt *p =3D disp_mgt->res_ops_tbl->priv; + struct device *dev =3D disp_mgt->common->dev; + struct nbl_chan_param_get_vsi_id *param; + struct nbl_chan_param_get_vsi_id result; + struct nbl_chan_ack_info chan_ack; + int err =3D NBL_CHAN_RESP_OK; + int ret =3D 0; + + param =3D (struct nbl_chan_param_get_vsi_id *)data; + + result.vsi_id =3D + NBL_OPS_CALL_RET(res_ops->get_vsi_id, (p, src_id, param->type)); + + NBL_CHAN_ACK(chan_ack, src_id, NBL_CHAN_MSG_GET_VSI_ID, msg_id, err, + &result, sizeof(result)); + ret =3D chan_ops->send_ack(disp_mgt->chan_ops_tbl->priv, &chan_ack); + if (ret) + dev_err(dev, + "channel send ack failed with ret: %d, msg_type: %d\n", + ret, NBL_CHAN_MSG_GET_VSI_ID); +} + +static void nbl_disp_chan_get_eth_id_req(struct nbl_dispatch_mgt *disp_mgt, + u16 vsi_id, u8 *eth_mode, u8 *eth_id, + u8 *logic_eth_id) +{ + struct nbl_channel_ops *chan_ops =3D disp_mgt->chan_ops_tbl->ops; + struct nbl_common_info *common =3D disp_mgt->common; + struct nbl_chan_param_get_eth_id result =3D { 0 }; + struct nbl_chan_param_get_eth_id param =3D { 0 }; + struct nbl_chan_send_info chan_send; + + param.vsi_id =3D vsi_id; + + NBL_CHAN_SEND(chan_send, common->mgt_pf, NBL_CHAN_MSG_GET_ETH_ID, + ¶m, sizeof(param), &result, sizeof(result), 1); + chan_ops->send_msg(disp_mgt->chan_ops_tbl->priv, &chan_send); + + *eth_mode =3D result.eth_mode; + *eth_id =3D result.eth_id; + *logic_eth_id =3D result.logic_eth_id; +} + +static void nbl_disp_chan_get_eth_id_resp(void *priv, u16 src_id, u16 msg_= id, + void *data, u32 data_len) +{ + struct nbl_dispatch_mgt *disp_mgt =3D (struct nbl_dispatch_mgt *)priv; + struct nbl_channel_ops *chan_ops =3D disp_mgt->chan_ops_tbl->ops; + struct nbl_resource_ops *res_ops =3D disp_mgt->res_ops_tbl->ops; + struct nbl_resource_mgt *p =3D disp_mgt->res_ops_tbl->priv; + struct nbl_chan_param_get_eth_id result =3D { 0 }; + struct device *dev =3D disp_mgt->common->dev; + struct nbl_chan_param_get_eth_id *param; + struct nbl_chan_ack_info chan_ack; + int err =3D NBL_CHAN_RESP_OK; + int ret =3D 0; + + param =3D (struct nbl_chan_param_get_eth_id *)data; + + NBL_OPS_CALL(res_ops->get_eth_id, + (p, param->vsi_id, &result.eth_mode, &result.eth_id, + &result.logic_eth_id)); + + NBL_CHAN_ACK(chan_ack, src_id, NBL_CHAN_MSG_GET_ETH_ID, msg_id, err, + &result, sizeof(result)); + ret =3D chan_ops->send_ack(disp_mgt->chan_ops_tbl->priv, &chan_ack); + if (ret) + dev_err(dev, + "channel send ack failed with ret: %d, msg_type: %d\n", + ret, NBL_CHAN_MSG_GET_ETH_ID); +} + +static void nbl_disp_deinit_chip_module(struct nbl_dispatch_mgt *disp_mgt) +{ + struct nbl_resource_ops *res_ops =3D disp_mgt->res_ops_tbl->ops; + struct nbl_resource_mgt *p =3D disp_mgt->res_ops_tbl->priv; + + NBL_OPS_CALL(res_ops->deinit_chip_module, (p)); +} + +static int nbl_disp_init_chip_module(struct nbl_dispatch_mgt *disp_mgt) +{ + struct nbl_resource_ops *res_ops =3D disp_mgt->res_ops_tbl->ops; + struct nbl_resource_mgt *p =3D disp_mgt->res_ops_tbl->priv; + + return NBL_OPS_CALL_RET(res_ops->init_chip_module, (p)); +} + +static int nbl_disp_configure_msix_map(struct nbl_dispatch_mgt *disp_mgt, + u16 num_net_msix, u16 num_others_msix, + bool net_msix_mask_en) +{ + struct nbl_resource_ops *res_ops =3D disp_mgt->res_ops_tbl->ops; + struct nbl_resource_mgt *p =3D disp_mgt->res_ops_tbl->priv; + + return NBL_OPS_CALL_LOCK_RET(disp_mgt, res_ops->configure_msix_map, p, + 0, num_net_msix, num_others_msix, + net_msix_mask_en); +} + +static int +nbl_disp_chan_configure_msix_map_req(struct nbl_dispatch_mgt *disp_mgt, + u16 num_net_msix, u16 num_others_msix, + bool net_msix_mask_en) +{ + struct nbl_channel_ops *chan_ops =3D disp_mgt->chan_ops_tbl->ops; + struct nbl_common_info *common =3D disp_mgt->common; + struct nbl_chan_param_cfg_msix_map param =3D { 0 }; + struct nbl_chan_send_info chan_send; + + param.num_net_msix =3D num_net_msix; + param.num_others_msix =3D num_others_msix; + param.msix_mask_en =3D net_msix_mask_en; + + NBL_CHAN_SEND(chan_send, common->mgt_pf, + NBL_CHAN_MSG_CONFIGURE_MSIX_MAP, ¶m, sizeof(param), + NULL, 0, 1); + return chan_ops->send_msg(disp_mgt->chan_ops_tbl->priv, &chan_send); +} + +static void nbl_disp_chan_configure_msix_map_resp(void *priv, u16 src_id, + u16 msg_id, void *data, + u32 data_len) +{ + struct nbl_dispatch_mgt *disp_mgt =3D (struct nbl_dispatch_mgt *)priv; + struct nbl_channel_ops *chan_ops =3D disp_mgt->chan_ops_tbl->ops; + struct nbl_resource_ops *res_ops =3D disp_mgt->res_ops_tbl->ops; + struct nbl_resource_mgt *p =3D disp_mgt->res_ops_tbl->priv; + struct device *dev =3D disp_mgt->common->dev; + struct nbl_chan_param_cfg_msix_map *param; + struct nbl_chan_ack_info chan_ack; + int err =3D NBL_CHAN_RESP_OK; + int ret; + + param =3D (struct nbl_chan_param_cfg_msix_map *)data; + + ret =3D NBL_OPS_CALL_LOCK_RET(disp_mgt, res_ops->configure_msix_map, p, + src_id, param->num_net_msix, + param->num_others_msix, + param->msix_mask_en); + if (ret) + err =3D NBL_CHAN_RESP_ERR; + + NBL_CHAN_ACK(chan_ack, src_id, NBL_CHAN_MSG_CONFIGURE_MSIX_MAP, msg_id, + err, NULL, 0); + ret =3D chan_ops->send_ack(disp_mgt->chan_ops_tbl->priv, &chan_ack); + if (ret) + dev_err(dev, + "channel send ack failed with ret: %d, msg_type: %d\n", + ret, NBL_CHAN_MSG_CONFIGURE_MSIX_MAP); +} + +static int nbl_disp_chan_destroy_msix_map_req(struct nbl_dispatch_mgt *dis= p_mgt) +{ + struct nbl_channel_ops *chan_ops =3D disp_mgt->chan_ops_tbl->ops; + struct nbl_common_info *common =3D disp_mgt->common; + struct nbl_chan_send_info chan_send; + + NBL_CHAN_SEND(chan_send, common->mgt_pf, NBL_CHAN_MSG_DESTROY_MSIX_MAP, + NULL, 0, NULL, 0, 1); + return chan_ops->send_msg(disp_mgt->chan_ops_tbl->priv, &chan_send); +} + +static void nbl_disp_chan_destroy_msix_map_resp(void *priv, u16 src_id, + u16 msg_id, void *data, + u32 data_len) +{ + struct nbl_dispatch_mgt *disp_mgt =3D (struct nbl_dispatch_mgt *)priv; + struct nbl_channel_ops *chan_ops =3D disp_mgt->chan_ops_tbl->ops; + struct nbl_resource_ops *res_ops =3D disp_mgt->res_ops_tbl->ops; + struct nbl_resource_mgt *p =3D disp_mgt->res_ops_tbl->priv; + struct device *dev =3D disp_mgt->common->dev; + struct nbl_chan_ack_info chan_ack; + int err =3D NBL_CHAN_RESP_OK; + int ret; + + ret =3D NBL_OPS_CALL_LOCK_RET(disp_mgt, res_ops->destroy_msix_map, p, + src_id); + if (ret) + err =3D NBL_CHAN_RESP_ERR; + + NBL_CHAN_ACK(chan_ack, src_id, NBL_CHAN_MSG_DESTROY_MSIX_MAP, msg_id, + err, NULL, 0); + ret =3D chan_ops->send_ack(disp_mgt->chan_ops_tbl->priv, &chan_ack); + if (ret) + dev_err(dev, + "channel send ack failed with ret: %d, msg_type: %d\n", + ret, NBL_CHAN_MSG_DESTROY_MSIX_MAP); +} + +static int +nbl_disp_chan_enable_mailbox_irq_req(struct nbl_dispatch_mgt *disp_mgt, + u16 vector_id, bool enable_msix) +{ + struct nbl_channel_ops *chan_ops =3D disp_mgt->chan_ops_tbl->ops; + struct nbl_chan_param_enable_mailbox_irq param =3D { 0 }; + struct nbl_common_info *common =3D disp_mgt->common; + struct nbl_chan_send_info chan_send; + + param.vector_id =3D vector_id; + param.enable_msix =3D enable_msix; + + NBL_CHAN_SEND(chan_send, common->mgt_pf, + NBL_CHAN_MSG_MAILBOX_ENABLE_IRQ, ¶m, sizeof(param), + NULL, 0, 1); + return chan_ops->send_msg(disp_mgt->chan_ops_tbl->priv, &chan_send); +} + +static void nbl_disp_chan_enable_mailbox_irq_resp(void *priv, u16 src_id, + u16 msg_id, void *data, + u32 data_len) +{ + struct nbl_dispatch_mgt *disp_mgt =3D (struct nbl_dispatch_mgt *)priv; + struct nbl_channel_ops *chan_ops =3D disp_mgt->chan_ops_tbl->ops; + struct nbl_resource_ops *res_ops =3D disp_mgt->res_ops_tbl->ops; + struct nbl_resource_mgt *p =3D disp_mgt->res_ops_tbl->priv; + struct nbl_chan_param_enable_mailbox_irq *param; + struct device *dev =3D disp_mgt->common->dev; + struct nbl_chan_ack_info chan_ack; + int err =3D NBL_CHAN_RESP_OK; + int ret; + + param =3D (struct nbl_chan_param_enable_mailbox_irq *)data; + + ret =3D NBL_OPS_CALL_LOCK_RET(disp_mgt, res_ops->enable_mailbox_irq, p, + src_id, param->vector_id, + param->enable_msix); + if (ret) + err =3D NBL_CHAN_RESP_ERR; + + NBL_CHAN_ACK(chan_ack, src_id, NBL_CHAN_MSG_MAILBOX_ENABLE_IRQ, msg_id, + err, NULL, 0); + ret =3D chan_ops->send_ack(disp_mgt->chan_ops_tbl->priv, &chan_ack); + if (ret) + dev_err(dev, + "channel send ack failed with ret: %d, msg_type: %d\n", + ret, NBL_CHAN_MSG_MAILBOX_ENABLE_IRQ); +} + +static int nbl_disp_destroy_msix_map(struct nbl_dispatch_mgt *disp_mgt) +{ + struct nbl_resource_ops *res_ops =3D disp_mgt->res_ops_tbl->ops; + struct nbl_resource_mgt *p =3D disp_mgt->res_ops_tbl->priv; + + return NBL_OPS_CALL_LOCK_RET(disp_mgt, res_ops->destroy_msix_map, p, 0); +} + +static int nbl_disp_enable_mailbox_irq(struct nbl_dispatch_mgt *disp_mgt, + u16 vector_id, bool enable_msix) +{ + struct nbl_resource_ops *res_ops =3D disp_mgt->res_ops_tbl->ops; + struct nbl_resource_mgt *p =3D disp_mgt->res_ops_tbl->priv; + + return NBL_OPS_CALL_LOCK_RET(disp_mgt, res_ops->enable_mailbox_irq, p, + 0, vector_id, enable_msix); +} + +static u16 nbl_disp_get_vsi_id(struct nbl_dispatch_mgt *disp_mgt, u16 func= _id, + u16 type) +{ + struct nbl_resource_ops *res_ops =3D disp_mgt->res_ops_tbl->ops; + struct nbl_resource_mgt *p =3D disp_mgt->res_ops_tbl->priv; + + return NBL_OPS_CALL_RET(res_ops->get_vsi_id, (p, func_id, type)); +} + +static void nbl_disp_get_eth_id(struct nbl_dispatch_mgt *disp_mgt, u16 vsi= _id, + u8 *eth_mode, u8 *eth_id, u8 *logic_eth_id) +{ + struct nbl_resource_ops *res_ops =3D disp_mgt->res_ops_tbl->ops; + struct nbl_resource_mgt *p =3D disp_mgt->res_ops_tbl->priv; + + NBL_OPS_CALL(res_ops->get_eth_id, + (p, vsi_id, eth_mode, eth_id, logic_eth_id)); +} + +/* NBL_DISP_SET_OPS(disp_op_name, func, ctrl_lvl, msg_type, msg_req, msg_r= esp) + * ctrl_lvl is to define when this disp_op should go directly to res_op, + * not sending a channel msg. + * Use X Macros to reduce codes in channel_op and disp_op setup/remove + */ +#define NBL_DISP_OPS_TBL \ +do { \ + NBL_DISP_SET_OPS(init_chip_module, nbl_disp_init_chip_module, \ + NBL_DISP_CTRL_LVL_MGT, -1, NULL, NULL); \ + NBL_DISP_SET_OPS(deinit_chip_module, \ + nbl_disp_deinit_chip_module, \ + NBL_DISP_CTRL_LVL_MGT, -1, NULL, NULL); \ + NBL_DISP_SET_OPS(configure_msix_map, \ + nbl_disp_configure_msix_map, \ + NBL_DISP_CTRL_LVL_MGT, \ + NBL_CHAN_MSG_CONFIGURE_MSIX_MAP, \ + nbl_disp_chan_configure_msix_map_req, \ + nbl_disp_chan_configure_msix_map_resp); \ + NBL_DISP_SET_OPS(destroy_msix_map, nbl_disp_destroy_msix_map, \ + NBL_DISP_CTRL_LVL_MGT, \ + NBL_CHAN_MSG_DESTROY_MSIX_MAP, \ + nbl_disp_chan_destroy_msix_map_req, \ + nbl_disp_chan_destroy_msix_map_resp); \ + NBL_DISP_SET_OPS(enable_mailbox_irq, \ + nbl_disp_enable_mailbox_irq, \ + NBL_DISP_CTRL_LVL_MGT, \ + NBL_CHAN_MSG_MAILBOX_ENABLE_IRQ, \ + nbl_disp_chan_enable_mailbox_irq_req, \ + nbl_disp_chan_enable_mailbox_irq_resp); \ + NBL_DISP_SET_OPS(get_vsi_id, nbl_disp_get_vsi_id, \ + NBL_DISP_CTRL_LVL_MGT, NBL_CHAN_MSG_GET_VSI_ID,\ + nbl_disp_chan_get_vsi_id_req, \ + nbl_disp_chan_get_vsi_id_resp); \ + NBL_DISP_SET_OPS(get_eth_id, nbl_disp_get_eth_id, \ + NBL_DISP_CTRL_LVL_MGT, NBL_CHAN_MSG_GET_ETH_ID,\ + nbl_disp_chan_get_eth_id_req, \ + nbl_disp_chan_get_eth_id_resp); \ +} while (0) + +/* Structure starts here, adding an op should not modify anything below */ +static int nbl_disp_setup_msg(struct nbl_dispatch_mgt *disp_mgt) +{ + struct nbl_dispatch_ops *disp_ops =3D disp_mgt->disp_ops_tbl->ops; + struct nbl_channel_ops *chan_ops =3D disp_mgt->chan_ops_tbl->ops; + struct nbl_channel_mgt *p =3D disp_mgt->chan_ops_tbl->priv; + int ret =3D 0; + + if (!chan_ops->check_queue_exist(disp_mgt->chan_ops_tbl->priv, + NBL_CHAN_TYPE_MAILBOX)) + return 0; + + mutex_init(&disp_mgt->ops_mutex_lock); + +#define NBL_DISP_SET_OPS(disp_op, func, ctrl, msg_type, msg_req, resp) \ +do { \ + typeof(msg_type) _msg_type =3D (msg_type); \ + typeof(ctrl) _ctrl_lvl =3D (ctrl); \ + (void)(disp_ops->NBL_NAME(disp_op)); \ + (void)(func); \ + (void)(msg_req); \ + (void)_ctrl_lvl; \ + if (_msg_type >=3D 0) \ + ret +=3D chan_ops->register_msg(p, _msg_type, resp, disp_mgt);\ +} while (0) + NBL_DISP_OPS_TBL; +#undef NBL_DISP_SET_OPS + + return ret; +} + +/* Ctrl lvl means that if a certain level is set, then all disp_ops that + * decleared this lvl will go directly to res_ops, rather than send a + * channel msg, and vice versa. + */ +static int nbl_disp_setup_ctrl_lvl(struct nbl_dispatch_mgt *disp_mgt, u32 = lvl) +{ + struct nbl_dispatch_ops *disp_ops =3D disp_mgt->disp_ops_tbl->ops; + + set_bit(lvl, disp_mgt->ctrl_lvl); + +#define NBL_DISP_SET_OPS(disp_op, func, ctrl, msg_type, msg_req, msg_resp)= \ +do { \ + typeof(msg_type) _msg_type =3D (msg_type); \ + (void)(_msg_type); \ + (void)(msg_resp); \ + disp_ops->NBL_NAME(disp_op) =3D \ + test_bit(ctrl, disp_mgt->ctrl_lvl) ? func : msg_req; \ +} while (0) + NBL_DISP_OPS_TBL; +#undef NBL_DISP_SET_OPS + + return 0; +} + static int nbl_disp_setup_disp_mgt(struct nbl_common_info *common, struct nbl_dispatch_mgt **disp_mgt) { @@ -67,7 +461,30 @@ int nbl_disp_init(struct nbl_adapter *adapter, struct n= bl_init_param *param) (*disp_mgt)->res_ops_tbl =3D res_ops_tbl; (*disp_mgt)->chan_ops_tbl =3D chan_ops_tbl; (*disp_mgt)->disp_ops_tbl =3D *disp_ops_tbl; + + ret =3D nbl_disp_setup_msg(*disp_mgt); + if (ret) + goto setup_msg_fail; + + if (param->caps.has_ctrl) { + ret =3D nbl_disp_setup_ctrl_lvl(*disp_mgt, NBL_DISP_CTRL_LVL_MGT); + if (ret) + goto setup_msg_fail; + } + + if (param->caps.has_net) { + ret =3D nbl_disp_setup_ctrl_lvl(*disp_mgt, NBL_DISP_CTRL_LVL_NET); + if (ret) + goto setup_msg_fail; + } + + ret =3D nbl_disp_setup_ctrl_lvl(*disp_mgt, NBL_DISP_CTRL_LVL_ALWAYS); + if (ret) + goto setup_msg_fail; + return 0; + +setup_msg_fail: setup_ops_fail: setup_mgt_fail: return ret; diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dispatch.h= b/drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dispatch.h index 265bad944404..92784c5c1b4e 100644 --- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dispatch.h +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dispatch.h @@ -9,6 +9,35 @@ =20 #include "nbl_core.h" =20 +#define NBL_OPS_CALL_LOCK(disp_mgt, func, ...) \ +do { \ + typeof(disp_mgt) _disp_mgt =3D (disp_mgt); \ + typeof(func) _func =3D (func); \ + \ + mutex_lock(&_disp_mgt->ops_mutex_lock); \ + \ + if (_func) \ + _func(__VA_ARGS__); \ + \ + mutex_unlock(&_disp_mgt->ops_mutex_lock); \ +} while (0) + +#define NBL_OPS_CALL_LOCK_RET(disp_mgt, func, ...) \ +({ \ + typeof(disp_mgt) _disp_mgt =3D (disp_mgt); \ + typeof(func) _func =3D (func); \ + typeof(_func(__VA_ARGS__)) _ret =3D 0; \ + \ + mutex_lock(&_disp_mgt->ops_mutex_lock); \ + \ + if (_func) \ + _ret =3D _func(__VA_ARGS__); \ + \ + mutex_unlock(&_disp_mgt->ops_mutex_lock); \ + \ + _ret; \ +}) + struct nbl_dispatch_mgt { struct nbl_common_info *common; struct nbl_resource_ops_tbl *res_ops_tbl; diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_dis= patch.h b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_dispat= ch.h index 9ece74c48898..0a76690e7831 100644 --- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_dispatch.h +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_include/nbl_def_dispatch.h @@ -18,6 +18,18 @@ enum { }; =20 struct nbl_dispatch_ops { + int (*init_chip_module)(struct nbl_dispatch_mgt *disp_mgt); + void (*deinit_chip_module)(struct nbl_dispatch_mgt *disp_mgt); + int (*configure_msix_map)(struct nbl_dispatch_mgt *disp_mgt, + u16 num_net_msix, u16 num_others_msix, + bool net_msix_mask_en); + int (*destroy_msix_map)(struct nbl_dispatch_mgt *disp_mgt); + int (*enable_mailbox_irq)(struct nbl_dispatch_mgt *disp_mgt, + u16 vector_id, bool enable_msix); + u16 (*get_vsi_id)(struct nbl_dispatch_mgt *disp_mgt, u16 func_id, + u16 type); + void (*get_eth_id)(struct nbl_dispatch_mgt *disp_mgt, u16 vsi_id, + u8 *eth_mode, u8 *eth_id, u8 *logic_eth_id); }; =20 struct nbl_dispatch_ops_tbl { --=20 2.47.3 From nobody Sun Feb 8 00:11:39 2026 Received: from out198-12.us.a.mail.aliyun.com (out198-12.us.a.mail.aliyun.com [47.90.198.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 82AF024EAB1; Fri, 6 Feb 2026 02:18:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=47.90.198.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770344322; cv=none; b=RWOho7sUeZudRHa+mXvNNsWU8Pn+GlUk7hraVJRvqoU+ck/XgBTEKdou8eKrPFa59ZPuNpaQSJT472OoNy5moANr5hzxi1UH9bMiqe5bEg1VSnpz4IaJx2vW0nd2KEvTR9PqWwJoFXnYoIcwKCcouKL3VeEDpZmoXN6gkxxQZjI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770344322; c=relaxed/simple; bh=AL3AZhPBmEc7Xa/w9zmQ7fwqMbLqwtO+LeyqPBccKgM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=cjvI3kpszx5J9fYmVoeSuaZ+WS79/kIRPuLYI34H4tVYRkqGlTK8QcIA+cF4SnqsuGLgnHPVMvchejo6m5jO+vx5GTO0/WqLISFuVDpDFjvukh0riI9vYF8qL1+uWUW/9VTj8jd0nLRpmE/YZBovac4R35lhJbYPI6g7us5wpwg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=nebula-matrix.com; spf=pass smtp.mailfrom=nebula-matrix.com; arc=none smtp.client-ip=47.90.198.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=nebula-matrix.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nebula-matrix.com Received: from localhost.localdomain(mailfrom:illusion.wang@nebula-matrix.com fp:SMTPD_---.gQHg4s4_1770344300 cluster:ay29) by smtp.aliyun-inc.com; Fri, 06 Feb 2026 10:18:21 +0800 From: "illusion.wang" To: dimon.zhao@nebula-matrix.com, illusion.wang@nebula-matrix.com, alvin.wang@nebula-matrix.com, sam.chen@nebula-matrix.com, netdev@vger.kernel.org Cc: andrew+netdev@lunn.ch, corbet@lwn.net, kuba@kernel.org, linux-doc@vger.kernel.org, lorenzo@kernel.org, pabeni@redhat.com, horms@kernel.org, vadim.fedorenko@linux.dev, lukas.bulwahn@redhat.com, edumazet@google.com, linux-kernel@vger.kernel.org (open list) Subject: [PATCH v4 net-next 10/11] net/nebula-matrix: add common/ctrl dev init/reinit operation Date: Fri, 6 Feb 2026 10:16:02 +0800 Message-ID: <20260206021608.85381-11-illusion.wang@nebula-matrix.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260206021608.85381-1-illusion.wang@nebula-matrix.com> References: <20260206021608.85381-1-illusion.wang@nebula-matrix.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Common Device Setup: nbl_dev_setup_common_dev configures mailbox queues, registers cleanup tasks, and requests IRQs. Control Device Setup (optional): nbl_dev_setup_ctrl_dev initializes the chip and configures all channel queues. Signed-off-by: illusion.wang --- .../nebula-matrix/nbl/nbl_core/nbl_dev.c | 178 ++++++++++++++++++ .../nebula-matrix/nbl/nbl_core/nbl_dev.h | 35 ++++ 2 files changed, 213 insertions(+) diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dev.c b/dr= ivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dev.c index fd7c97f3b0fe..9927dd3a1791 100644 --- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dev.c +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dev.c @@ -6,6 +6,164 @@ =20 #include "nbl_dev.h" =20 +static void nbl_dev_register_common_irq(struct nbl_dev_mgt *dev_mgt) +{ + struct nbl_dev_common *dev_common =3D dev_mgt->common_dev; + struct nbl_msix_info *msix_info =3D &dev_common->msix_info; + + msix_info->serv_info[NBL_MSIX_MAILBOX_TYPE].num =3D 1; +} + +/* ---------- Channel config ---------- */ +static int nbl_dev_setup_chan_qinfo(struct nbl_dev_mgt *dev_mgt, u8 chan_t= ype) +{ + struct nbl_channel_ops *chan_ops =3D dev_mgt->chan_ops_tbl->ops; + struct nbl_channel_mgt *priv =3D dev_mgt->chan_ops_tbl->priv; + struct device *dev =3D dev_mgt->common->dev; + int ret =3D 0; + + if (!chan_ops->check_queue_exist(priv, chan_type)) + return 0; + + ret =3D chan_ops->cfg_chan_qinfo_map_table(priv, chan_type); + if (ret) + dev_err(dev, "setup chan:%d, qinfo map table failed\n", + chan_type); + + return ret; +} + +static int nbl_dev_setup_chan_queue(struct nbl_dev_mgt *dev_mgt, u8 chan_t= ype) +{ + struct nbl_channel_ops *chan_ops =3D dev_mgt->chan_ops_tbl->ops; + struct nbl_channel_mgt *priv =3D dev_mgt->chan_ops_tbl->priv; + int ret =3D 0; + + if (chan_ops->check_queue_exist(priv, chan_type)) + ret =3D chan_ops->setup_queue(priv, chan_type); + + return ret; +} + +static int nbl_dev_remove_chan_queue(struct nbl_dev_mgt *dev_mgt, u8 chan_= type) +{ + struct nbl_channel_ops *chan_ops =3D dev_mgt->chan_ops_tbl->ops; + struct nbl_channel_mgt *priv =3D dev_mgt->chan_ops_tbl->priv; + int ret =3D 0; + + if (chan_ops->check_queue_exist(priv, chan_type)) + ret =3D chan_ops->teardown_queue(priv, chan_type); + + return ret; +} + +static void nbl_dev_register_chan_task(struct nbl_dev_mgt *dev_mgt, + u8 chan_type, struct work_struct *task) +{ + struct nbl_channel_ops *chan_ops =3D dev_mgt->chan_ops_tbl->ops; + + if (chan_ops->check_queue_exist(dev_mgt->chan_ops_tbl->priv, chan_type)) + chan_ops->register_chan_task(dev_mgt->chan_ops_tbl->priv, + chan_type, task); +} + +/* ---------- Tasks config ---------- */ +static void nbl_dev_clean_mailbox_task(struct work_struct *work) +{ + struct nbl_dev_common *common_dev =3D + container_of(work, struct nbl_dev_common, clean_mbx_task); + struct nbl_dev_mgt *dev_mgt =3D common_dev->dev_mgt; + struct nbl_channel_ops *chan_ops =3D dev_mgt->chan_ops_tbl->ops; + + chan_ops->clean_queue_subtask(dev_mgt->chan_ops_tbl->priv, + NBL_CHAN_TYPE_MAILBOX); +} + +/* ---------- Dev init process ---------- */ +static int nbl_dev_setup_common_dev(struct nbl_adapter *adapter, + struct nbl_init_param *param) +{ + struct nbl_dev_mgt *dev_mgt =3D + (struct nbl_dev_mgt *)NBL_ADAP_TO_DEV_MGT(adapter); + struct nbl_dispatch_ops *disp_ops =3D dev_mgt->disp_ops_tbl->ops; + struct nbl_dispatch_mgt *priv =3D dev_mgt->disp_ops_tbl->priv; + struct nbl_common_info *common =3D dev_mgt->common; + struct nbl_dev_common *common_dev; + + common_dev =3D devm_kzalloc(&adapter->pdev->dev, + sizeof(struct nbl_dev_common), GFP_KERNEL); + if (!common_dev) + return -ENOMEM; + common_dev->dev_mgt =3D dev_mgt; + + if (nbl_dev_setup_chan_queue(dev_mgt, NBL_CHAN_TYPE_MAILBOX)) + goto setup_chan_fail; + + INIT_WORK(&common_dev->clean_mbx_task, nbl_dev_clean_mailbox_task); + common->vsi_id =3D disp_ops->get_vsi_id(priv, 0, NBL_VSI_DATA); + disp_ops->get_eth_id(priv, common->vsi_id, + &common->eth_mode, &common->eth_id, + &common->logic_eth_id); + + nbl_dev_register_chan_task(dev_mgt, NBL_CHAN_TYPE_MAILBOX, + &common_dev->clean_mbx_task); + + dev_mgt->common_dev =3D common_dev; + nbl_dev_register_common_irq(dev_mgt); + return 0; + +setup_chan_fail: + return -EFAULT; +} + +static void nbl_dev_remove_common_dev(struct nbl_adapter *adapter) +{ + struct nbl_dev_mgt *dev_mgt =3D + (struct nbl_dev_mgt *)NBL_ADAP_TO_DEV_MGT(adapter); + struct nbl_dev_common *common_dev =3D dev_mgt->common_dev; + + if (!common_dev) + return; + + nbl_dev_register_chan_task(dev_mgt, NBL_CHAN_TYPE_MAILBOX, NULL); + cancel_work_sync(&common_dev->clean_mbx_task); + nbl_dev_remove_chan_queue(dev_mgt, NBL_CHAN_TYPE_MAILBOX); +} + +static int nbl_dev_setup_ctrl_dev(struct nbl_adapter *adapter, + struct nbl_init_param *param) +{ + struct nbl_dev_mgt *dev_mgt =3D + (struct nbl_dev_mgt *)NBL_ADAP_TO_DEV_MGT(adapter); + struct nbl_dispatch_ops *disp_ops =3D dev_mgt->disp_ops_tbl->ops; + int i, ret =3D 0; + + ret =3D disp_ops->init_chip_module(dev_mgt->disp_ops_tbl->priv); + if (ret) + goto chip_init_fail; + + for (i =3D 0; i < NBL_CHAN_TYPE_MAX; i++) { + ret =3D nbl_dev_setup_chan_qinfo(dev_mgt, i); + if (ret) + goto setup_chan_q_fail; + } + + return 0; +setup_chan_q_fail: + disp_ops->deinit_chip_module(dev_mgt->disp_ops_tbl->priv); +chip_init_fail: + return ret; +} + +static void nbl_dev_remove_ctrl_dev(struct nbl_adapter *adapter) +{ + struct nbl_dev_mgt *dev_mgt =3D + (struct nbl_dev_mgt *)NBL_ADAP_TO_DEV_MGT(adapter); + struct nbl_dispatch_ops *disp_ops =3D dev_mgt->disp_ops_tbl->ops; + + disp_ops->deinit_chip_module(dev_mgt->disp_ops_tbl->priv); +} + static int nbl_dev_setup_dev_mgt(struct nbl_common_info *common, struct nbl_dev_mgt **dev_mgt) { @@ -35,13 +193,33 @@ int nbl_dev_init(struct nbl_adapter *adapter, struct n= bl_init_param *param) =20 (*dev_mgt)->disp_ops_tbl =3D disp_ops_tbl; (*dev_mgt)->chan_ops_tbl =3D chan_ops_tbl; + + ret =3D nbl_dev_setup_common_dev(adapter, param); + if (ret) + goto setup_common_dev_fail; + + if (common->is_ctrl) { + ret =3D nbl_dev_setup_ctrl_dev(adapter, param); + if (ret) + goto setup_ctrl_dev_fail; + } + return 0; + +setup_ctrl_dev_fail: + nbl_dev_remove_common_dev(adapter); +setup_common_dev_fail: setup_mgt_fail: return ret; } =20 void nbl_dev_remove(struct nbl_adapter *adapter) { + struct nbl_common_info *common =3D &adapter->common; + + if (common->is_ctrl) + nbl_dev_remove_ctrl_dev(adapter); + nbl_dev_remove_common_dev(adapter); } =20 /* ---------- Dev start process ---------- */ diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dev.h b/dr= ivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dev.h index d41ba06d00fb..1d48a91cd230 100644 --- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dev.h +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dev.h @@ -9,10 +9,45 @@ =20 #include "nbl_core.h" =20 +#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | \ + NETIF_MSG_LINK | NETIF_MSG_IFDOWN | \ + NETIF_MSG_IFUP) + +#define NBL_STRING_NAME_LEN 32 + +enum nbl_msix_serv_type { + /* virtio_dev has a config vector_id, and the vector_id need is 0 */ + NBL_MSIX_VIRTIO_TYPE =3D 0, + NBL_MSIX_NET_TYPE, + NBL_MSIX_MAILBOX_TYPE, + NBL_MSIX_TYPE_MAX +}; + +struct nbl_msix_serv_info { + char irq_name[NBL_STRING_NAME_LEN]; + u16 num; + u16 base_vector_id; + /* true: hw report msix, hw need to mask actively */ + bool hw_self_mask_en; +}; + +struct nbl_msix_info { + struct nbl_msix_serv_info serv_info[NBL_MSIX_TYPE_MAX]; +}; + +struct nbl_dev_common { + struct nbl_dev_mgt *dev_mgt; + struct nbl_msix_info msix_info; + char mailbox_name[NBL_STRING_NAME_LEN]; + // for ctrl-dev/net-dev mailbox recv msg + struct work_struct clean_mbx_task; +}; + struct nbl_dev_mgt { struct nbl_common_info *common; struct nbl_dispatch_ops_tbl *disp_ops_tbl; struct nbl_channel_ops_tbl *chan_ops_tbl; + struct nbl_dev_common *common_dev; }; =20 #endif --=20 2.47.3 From nobody Sun Feb 8 00:11:39 2026 Received: from out198-10.us.a.mail.aliyun.com (out198-10.us.a.mail.aliyun.com [47.90.198.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2DEDC25F96D; Fri, 6 Feb 2026 02:23:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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spf=pass smtp.mailfrom=nebula-matrix.com Received: from localhost.localdomain(mailfrom:illusion.wang@nebula-matrix.com fp:SMTPD_---.gQHg4u-_1770344301 cluster:ay29) by smtp.aliyun-inc.com; Fri, 06 Feb 2026 10:18:22 +0800 From: "illusion.wang" To: dimon.zhao@nebula-matrix.com, illusion.wang@nebula-matrix.com, alvin.wang@nebula-matrix.com, sam.chen@nebula-matrix.com, netdev@vger.kernel.org Cc: andrew+netdev@lunn.ch, corbet@lwn.net, kuba@kernel.org, linux-doc@vger.kernel.org, lorenzo@kernel.org, pabeni@redhat.com, horms@kernel.org, vadim.fedorenko@linux.dev, lukas.bulwahn@redhat.com, edumazet@google.com, linux-kernel@vger.kernel.org (open list) Subject: [PATCH v4 net-next 11/11] net/nebula-matrix: add common dev start/stop operation Date: Fri, 6 Feb 2026 10:16:03 +0800 Message-ID: <20260206021608.85381-12-illusion.wang@nebula-matrix.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260206021608.85381-1-illusion.wang@nebula-matrix.com> References: <20260206021608.85381-1-illusion.wang@nebula-matrix.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" start common dev: config msix map table, alloc and enable msix vectors, register mailbox ISR and enable mailbox irq Signed-off-by: illusion.wang --- .../nebula-matrix/nbl/nbl_core/nbl_dev.c | 241 +++++++++++++++++- .../net/ethernet/nebula-matrix/nbl/nbl_main.c | 33 ++- 2 files changed, 272 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dev.c b/dr= ivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dev.c index 9927dd3a1791..59d23e93e923 100644 --- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dev.c +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_core/nbl_dev.c @@ -6,6 +6,17 @@ =20 #include "nbl_dev.h" =20 +static int nbl_dev_clean_mailbox_schedule(struct nbl_dev_mgt *dev_mgt); + +/* ---------- Interrupt config ---------- */ +static irqreturn_t nbl_dev_clean_mailbox(int __always_unused irq, void *da= ta) +{ + struct nbl_dev_mgt *dev_mgt =3D (struct nbl_dev_mgt *)data; + + nbl_dev_clean_mailbox_schedule(dev_mgt); + return IRQ_HANDLED; +} + static void nbl_dev_register_common_irq(struct nbl_dev_mgt *dev_mgt) { struct nbl_dev_common *dev_common =3D dev_mgt->common_dev; @@ -14,6 +25,179 @@ static void nbl_dev_register_common_irq(struct nbl_dev_= mgt *dev_mgt) msix_info->serv_info[NBL_MSIX_MAILBOX_TYPE].num =3D 1; } =20 +static int nbl_dev_request_mailbox_irq(struct nbl_dev_mgt *dev_mgt) +{ + struct nbl_dev_common *dev_common =3D dev_mgt->common_dev; + struct nbl_msix_info *msix_info =3D &dev_common->msix_info; + struct nbl_common_info *common =3D dev_mgt->common; + u16 local_vec_id; + u32 irq_num; + int err; + + if (!msix_info->serv_info[NBL_MSIX_MAILBOX_TYPE].num) + return 0; + + local_vec_id =3D + msix_info->serv_info[NBL_MSIX_MAILBOX_TYPE].base_vector_id; + irq_num =3D pci_irq_vector(common->pdev, local_vec_id); + + snprintf(dev_common->mailbox_name, sizeof(dev_common->mailbox_name), + "nbl_mailbox@pci:%s", pci_name(common->pdev)); + err =3D request_irq(irq_num, nbl_dev_clean_mailbox, 0, + dev_common->mailbox_name, dev_mgt); + if (err) + return err; + + return 0; +} + +static void nbl_dev_free_mailbox_irq(struct nbl_dev_mgt *dev_mgt) +{ + struct nbl_dev_common *dev_common =3D dev_mgt->common_dev; + struct nbl_msix_info *msix_info =3D &dev_common->msix_info; + struct nbl_common_info *common =3D dev_mgt->common; + u16 local_vec_id; + u32 irq_num; + + if (!msix_info->serv_info[NBL_MSIX_MAILBOX_TYPE].num) + return; + + local_vec_id =3D + msix_info->serv_info[NBL_MSIX_MAILBOX_TYPE].base_vector_id; + irq_num =3D pci_irq_vector(common->pdev, local_vec_id); + + free_irq(irq_num, dev_mgt); +} + +static int nbl_dev_enable_mailbox_irq(struct nbl_dev_mgt *dev_mgt) +{ + struct nbl_dispatch_ops *disp_ops =3D dev_mgt->disp_ops_tbl->ops; + struct nbl_channel_ops *chan_ops =3D dev_mgt->chan_ops_tbl->ops; + struct nbl_dev_common *dev_common =3D dev_mgt->common_dev; + struct nbl_msix_info *msix_info =3D &dev_common->msix_info; + u16 local_vec_id; + + if (!msix_info->serv_info[NBL_MSIX_MAILBOX_TYPE].num) + return 0; + + local_vec_id =3D + msix_info->serv_info[NBL_MSIX_MAILBOX_TYPE].base_vector_id; + chan_ops->set_queue_state(dev_mgt->chan_ops_tbl->priv, + NBL_CHAN_INTERRUPT_READY, + NBL_CHAN_TYPE_MAILBOX, true); + + return disp_ops->enable_mailbox_irq(dev_mgt->disp_ops_tbl->priv, + local_vec_id, true); +} + +static int nbl_dev_disable_mailbox_irq(struct nbl_dev_mgt *dev_mgt) +{ + struct nbl_dispatch_ops *disp_ops =3D dev_mgt->disp_ops_tbl->ops; + struct nbl_channel_ops *chan_ops =3D dev_mgt->chan_ops_tbl->ops; + struct nbl_dev_common *dev_common =3D dev_mgt->common_dev; + struct nbl_msix_info *msix_info =3D &dev_common->msix_info; + u16 local_vec_id; + + if (!msix_info->serv_info[NBL_MSIX_MAILBOX_TYPE].num) + return 0; + + flush_work(&dev_common->clean_mbx_task); + local_vec_id =3D + msix_info->serv_info[NBL_MSIX_MAILBOX_TYPE].base_vector_id; + chan_ops->set_queue_state(dev_mgt->chan_ops_tbl->priv, + NBL_CHAN_INTERRUPT_READY, + NBL_CHAN_TYPE_MAILBOX, false); + + return disp_ops->enable_mailbox_irq(dev_mgt->disp_ops_tbl->priv, + local_vec_id, false); +} + +static int nbl_dev_configure_msix_map(struct nbl_dev_mgt *dev_mgt) +{ + struct nbl_dispatch_ops *disp_ops =3D dev_mgt->disp_ops_tbl->ops; + struct nbl_dev_common *dev_common =3D dev_mgt->common_dev; + struct nbl_msix_info *msix_info =3D &dev_common->msix_info; + bool mask_en =3D msix_info->serv_info[NBL_MSIX_NET_TYPE].hw_self_mask_en; + u16 msix_net_num =3D msix_info->serv_info[NBL_MSIX_NET_TYPE].num; + u16 msix_not_net_num =3D 0; + int err, i; + + for (i =3D NBL_MSIX_NET_TYPE; i < NBL_MSIX_TYPE_MAX; i++) + msix_info->serv_info[i].base_vector_id =3D + msix_info->serv_info[i - 1].base_vector_id + + msix_info->serv_info[i - 1].num; + + for (i =3D NBL_MSIX_MAILBOX_TYPE; i < NBL_MSIX_TYPE_MAX; i++) { + if (i =3D=3D NBL_MSIX_NET_TYPE) + continue; + + msix_not_net_num +=3D msix_info->serv_info[i].num; + } + + err =3D disp_ops->configure_msix_map(dev_mgt->disp_ops_tbl->priv, + msix_net_num, msix_not_net_num, + mask_en); + + return err; +} + +static int nbl_dev_destroy_msix_map(struct nbl_dev_mgt *dev_mgt) +{ + struct nbl_dispatch_ops *disp_ops =3D dev_mgt->disp_ops_tbl->ops; + + return disp_ops->destroy_msix_map(dev_mgt->disp_ops_tbl->priv); +} + +static int nbl_dev_alloc_msix_intr(struct nbl_dev_mgt *dev_mgt) +{ + struct nbl_dev_common *dev_common =3D dev_mgt->common_dev; + struct nbl_msix_info *msix_info =3D &dev_common->msix_info; + struct nbl_common_info *common =3D dev_mgt->common; + int needed =3D 0; + int err; + int i; + + for (i =3D 0; i < NBL_MSIX_TYPE_MAX; i++) + needed +=3D msix_info->serv_info[i].num; + + err =3D pci_alloc_irq_vectors(common->pdev, needed, needed, + PCI_IRQ_MSIX | PCI_IRQ_AFFINITY); + if (err < 0) { + pr_err("pci_enable_msix_range failed, err =3D %d.\n", err); + goto enable_msix_failed; + } + + return needed; + +enable_msix_failed: + return err; +} + +static void nbl_dev_free_msix_intr(struct nbl_dev_mgt *dev_mgt) +{ + struct nbl_common_info *common =3D dev_mgt->common; + + pci_free_irq_vectors(common->pdev); +} + +static int nbl_dev_init_interrupt_scheme(struct nbl_dev_mgt *dev_mgt) +{ + int err =3D 0; + + err =3D nbl_dev_alloc_msix_intr(dev_mgt); + if (err < 0) { + dev_err(dev_mgt->common->dev, + "Failed to enable MSI-X vectors\n"); + return err; + } + return 0; +} + +static void nbl_dev_clear_interrupt_scheme(struct nbl_dev_mgt *dev_mgt) +{ + nbl_dev_free_msix_intr(dev_mgt); +} + /* ---------- Channel config ---------- */ static int nbl_dev_setup_chan_qinfo(struct nbl_dev_mgt *dev_mgt, u8 chan_t= ype) { @@ -79,6 +263,14 @@ static void nbl_dev_clean_mailbox_task(struct work_stru= ct *work) NBL_CHAN_TYPE_MAILBOX); } =20 +static int nbl_dev_clean_mailbox_schedule(struct nbl_dev_mgt *dev_mgt) +{ + struct nbl_dev_common *common_dev =3D dev_mgt->common_dev; + + nbl_common_queue_work(&common_dev->clean_mbx_task); + return 0; +} + /* ---------- Dev init process ---------- */ static int nbl_dev_setup_common_dev(struct nbl_adapter *adapter, struct nbl_init_param *param) @@ -223,11 +415,58 @@ void nbl_dev_remove(struct nbl_adapter *adapter) } =20 /* ---------- Dev start process ---------- */ -int nbl_dev_start(struct nbl_adapter *adapter, struct nbl_init_param *para= m) + +static int nbl_dev_start_common_dev(struct nbl_adapter *adapter, + struct nbl_init_param *param) { + struct nbl_dev_mgt *dev_mgt =3D + (struct nbl_dev_mgt *)NBL_ADAP_TO_DEV_MGT(adapter); + int ret; + + ret =3D nbl_dev_configure_msix_map(dev_mgt); + if (ret) + goto config_msix_map_err; + + ret =3D nbl_dev_init_interrupt_scheme(dev_mgt); + if (ret) + goto init_interrupt_scheme_err; + ret =3D nbl_dev_request_mailbox_irq(dev_mgt); + if (ret) + goto mailbox_request_irq_err; + ret =3D nbl_dev_enable_mailbox_irq(dev_mgt); + if (ret) + goto enable_mailbox_irq_err; return 0; +enable_mailbox_irq_err: + nbl_dev_free_mailbox_irq(dev_mgt); +mailbox_request_irq_err: + nbl_dev_clear_interrupt_scheme(dev_mgt); +init_interrupt_scheme_err: + nbl_dev_destroy_msix_map(dev_mgt); +config_msix_map_err: + return ret; +} + +static void nbl_dev_stop_common_dev(struct nbl_adapter *adapter) +{ + struct nbl_dev_mgt *dev_mgt =3D + (struct nbl_dev_mgt *)NBL_ADAP_TO_DEV_MGT(adapter); + + nbl_dev_disable_mailbox_irq(dev_mgt); + nbl_dev_free_mailbox_irq(dev_mgt); + nbl_dev_clear_interrupt_scheme(dev_mgt); + nbl_dev_destroy_msix_map(dev_mgt); +} + +int nbl_dev_start(struct nbl_adapter *adapter, struct nbl_init_param *para= m) +{ + int ret; + + ret =3D nbl_dev_start_common_dev(adapter, param); + return ret; } =20 void nbl_dev_stop(struct nbl_adapter *adapter) { + nbl_dev_stop_common_dev(adapter); } diff --git a/drivers/net/ethernet/nebula-matrix/nbl/nbl_main.c b/drivers/ne= t/ethernet/nebula-matrix/nbl/nbl_main.c index a16a685e4f29..55ed560624d3 100644 --- a/drivers/net/ethernet/nebula-matrix/nbl/nbl_main.c +++ b/drivers/net/ethernet/nebula-matrix/nbl/nbl_main.c @@ -283,7 +283,38 @@ static struct pci_driver nbl_driver =3D { .remove =3D nbl_remove, }; =20 -module_pci_driver(nbl_driver); +static int __init nbl_module_init(void) +{ + int status; + + status =3D nbl_common_create_wq(); + if (status) { + pr_err("Failed to create wq, err =3D %d\n", status); + goto wq_create_failed; + } + status =3D pci_register_driver(&nbl_driver); + if (status) { + pr_err("Failed to register PCI driver, err =3D %d\n", status); + goto pci_register_driver_failed; + } + pr_info("nbl module loaded\n"); + return 0; + +pci_register_driver_failed: + nbl_common_destroy_wq(); +wq_create_failed: + return status; +} + +static void __exit nbl_module_exit(void) +{ + pci_unregister_driver(&nbl_driver); + nbl_common_destroy_wq(); + + pr_info("nbl module unloaded\n"); +} =20 +module_init(nbl_module_init); +module_exit(nbl_module_exit); MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("Nebula Matrix Network Driver"); --=20 2.47.3