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charset="utf-8" Include rva(20|22)(u|s)64 isa bases in the output when they are detected. Signed-off-by: Andrew Jones --- arch/riscv/include/asm/cpufeature.h | 4 ++ arch/riscv/kernel/cpu.c | 4 ++ arch/riscv/kernel/cpufeature.c | 65 +++++++++++++++++++++++------ 3 files changed, 61 insertions(+), 12 deletions(-) diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/c= pufeature.h index e750735c5686..41431e89bb3b 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -27,6 +27,10 @@ struct riscv_cpuinfo { =20 enum { RISCV_ISA_BASE_IMA, + RISCV_ISA_BASE_RVA20U64, + RISCV_ISA_BASE_RVA20S64, + RISCV_ISA_BASE_RVA22U64, + RISCV_ISA_BASE_RVA22S64, RISCV_ISA_BASE_RVA23U64, RISCV_ISA_BASE_RVA23S64, RISCV_NR_ISA_BASES, diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 228867d7dc00..007958744ae5 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -313,6 +313,10 @@ static const char * const riscv_isa_base_names[] =3D { #else [RISCV_ISA_BASE_IMA] =3D "rv64ima", #endif + [RISCV_ISA_BASE_RVA20U64] =3D "rva20u64", + [RISCV_ISA_BASE_RVA20S64] =3D "rva20s64", + [RISCV_ISA_BASE_RVA22U64] =3D "rva22u64", + [RISCV_ISA_BASE_RVA22S64] =3D "rva22s64", [RISCV_ISA_BASE_RVA23U64] =3D "rva23u64", [RISCV_ISA_BASE_RVA23S64] =3D "rva23s64", }; diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 07a42545e9e0..ac46b974e5e4 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -1281,33 +1281,74 @@ void riscv_set_isa_bases(unsigned long *bases, cons= t unsigned long *isa_bitmap) =20 set_bit(RISCV_ISA_BASE_IMA, bases); =20 - /* RVA23U64 */ - - /* Zic64b and Supm with PMLEN=3D7 */ - if (riscv_cbom_block_size !=3D 64 || - riscv_cbop_block_size !=3D 64 || - riscv_cboz_block_size !=3D 64 || - !riscv_have_user_pmlen_7) - return; - + /* RVA20U64 */ set_bit(RISCV_ISA_EXT_F, ext_mask); set_bit(RISCV_ISA_EXT_D, ext_mask); set_bit(RISCV_ISA_EXT_C, ext_mask); - set_bit(RISCV_ISA_EXT_B, ext_mask); set_bit(RISCV_ISA_EXT_ZICSR, ext_mask); set_bit(RISCV_ISA_EXT_ZICNTR, ext_mask); - set_bit(RISCV_ISA_EXT_ZIHPM, ext_mask); set_bit(RISCV_ISA_EXT_ZICCIF, ext_mask); set_bit(RISCV_ISA_EXT_ZICCRSE, ext_mask); set_bit(RISCV_ISA_EXT_ZICCAMOA, ext_mask); - set_bit(RISCV_ISA_EXT_ZICCLSM, ext_mask); + /* Spec says Za128rs, but Za64rs is compatible and mandated by later prof= iles */ set_bit(RISCV_ISA_EXT_ZA64RS, ext_mask); + set_bit(RISCV_ISA_EXT_ZICCLSM, ext_mask); + + if (bitmap_andnot(tmp, ext_mask, isa, RISCV_ISA_EXT_MAX)) + return; + + set_bit(RISCV_ISA_BASE_RVA20U64, bases); + + /* RVA20S64 */ + set_bit(RISCV_ISA_EXT_ZIFENCEI, ext_mask); + /* TODO: Ss1p11 */ + /* Svbare, Sv39 -- assumed */ + set_bit(RISCV_ISA_EXT_SVADE, ext_mask); + /* TODO: Ssccptr, Sstvecd, Sstvala */ + + if (/*TODO*/ false && !bitmap_andnot(tmp, ext_mask, isa, RISCV_ISA_EXT_MA= X)) + set_bit(RISCV_ISA_BASE_RVA20S64, bases); + + /* RVA22U64 */ + + /* Zic64b */ + if (riscv_cbom_block_size !=3D 64 || + riscv_cbop_block_size !=3D 64 || + riscv_cboz_block_size !=3D 64) + return; + + set_bit(RISCV_ISA_EXT_B, ext_mask); + set_bit(RISCV_ISA_EXT_ZIHPM, ext_mask); set_bit(RISCV_ISA_EXT_ZIHINTPAUSE, ext_mask); set_bit(RISCV_ISA_EXT_ZICBOM, ext_mask); set_bit(RISCV_ISA_EXT_ZICBOP, ext_mask); set_bit(RISCV_ISA_EXT_ZICBOZ, ext_mask); set_bit(RISCV_ISA_EXT_ZFHMIN, ext_mask); set_bit(RISCV_ISA_EXT_ZKT, ext_mask); + + if (bitmap_andnot(tmp, ext_mask, isa, RISCV_ISA_EXT_MAX)) + return; + + set_bit(RISCV_ISA_BASE_RVA22U64, bases); + + /* RVA22S64 */ + set_bit(RISCV_ISA_EXT_ZIFENCEI, ext_mask); + /* TODO: Ss1p12 */ + /* Svbare, Sv39 -- assumed */ + set_bit(RISCV_ISA_EXT_SVADE, ext_mask); + /* TODO: Ssccptr, Sstvecd, Sstvala, Sscounterenw */ + set_bit(RISCV_ISA_EXT_SVPBMT, ext_mask); + set_bit(RISCV_ISA_EXT_SVINVAL, ext_mask); + + if (/*TODO*/ false && !bitmap_andnot(tmp, ext_mask, isa, RISCV_ISA_EXT_MA= X)) + set_bit(RISCV_ISA_BASE_RVA22S64, bases); + + /* RVA23U64 */ + + /* Supm with PMLEN=3D7 */ + if (!riscv_have_user_pmlen_7) + return; + set_bit(RISCV_ISA_EXT_V, ext_mask); set_bit(RISCV_ISA_EXT_ZVFHMIN, ext_mask); set_bit(RISCV_ISA_EXT_ZVBB, ext_mask); --=20 2.43.0