From nobody Sat Feb 7 17:09:40 2026 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8AA58330B2D for ; Thu, 5 Feb 2026 21:24:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770326650; cv=none; b=iZgXpfgE6RF9glGcUo4fUHkzqMqyyZ5E00j2yvSMyDA6rjKwV9wcq92lXNDjLjYxNu+KrTVrw1GEnRpciP8V4+eQDV4+HAbXJGlL0PD9u6YlOqQZkDZrG7jtkswneWEhd7AXxf4ZNCRXF8oVkNcIZs+p3LYY3g/+raO1Z5mULG0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770326650; c=relaxed/simple; bh=XMaDVYmuWuR7Vozem00RyLezzf4ecLHPGnFKrah7WlU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=X80fxjg24Ep3839v54M5FEeMKFTch5wSM/tLhc55I1j/Wb3p9EdLUywlMbpT2QwI54g+QHGC6BiHztnO0snv/MJqCVveNujGIpaFMGXVCuHK9IJfjmZ6obDPPWrGWdwZUf/W0taX5T6v/m73Q6Or+2YsEafNpjfbCXVIIj9dOjY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b=iI0zpFv9; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b="iI0zpFv9" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-Type; bh=GlCPNfoDyu0ihNPCW4h5bfptKMnnPn3SUFCxT54wycY=; b=iI0zpFv96qHRyPz9kl8S/DgiRF StCE1Aq3CN2+f4C3ETzvtyEevNNeslzwwJ4SVqOf8e3PkdEwkArObejTMgMpzFqOyMdNIrNDRjwMQ u77HMWw1u0W341c70qdwuCvWblOmZ8FjZaq4lUODafIWgzeAKkyDoz5IBdwTswHH5QIMCncBf3Dla S3huvc0KxRpm4maBQDNHpvILmy+qqpBhyH8/Wf9mN7Du0weNaEjquQ6X6frFHwnDyBOfTur1KsN2E m7JIetxsBqCQj4zULjGVCSMlRCuB3paBTva+FmmdtetHHnrQrPtFUvXBriONJY2rzMLslyWT5E9g0 AS2UPUBg==; Received: from i53875afe.versanet.de ([83.135.90.254] helo=localhost.localdomain) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1vo6pc-007GK0-AQ; Thu, 05 Feb 2026 22:24:08 +0100 From: Heiko Stuebner To: heiko@sntech.de Cc: linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, kever.yang@rock-chips.com, finley.xiao@rock-chips.com, w@1wt.eu, jonas@kwiboo.se Subject: [PATCH 1/3] arm64: dts: rockchip: Enable OTP controller for RK3562 Date: Thu, 5 Feb 2026 22:23:45 +0100 Message-ID: <20260205212347.490636-2-heiko@sntech.de> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20260205212347.490636-1-heiko@sntech.de> References: <20260205212347.490636-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable the One Time Programmable Controller (OTPC) in RK3562 and add an initial nvmem fixed layout. Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3562.dtsi | 46 ++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3562.dtsi b/arch/arm64/boot/dts= /rockchip/rk3562.dtsi index f84676b47b27..07626dba21bf 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3562.dtsi @@ -1093,6 +1093,52 @@ sdmmc1: mmc@ff890000 { status =3D "disabled"; }; =20 + otp: otp@ff930000 { + compatible =3D "rockchip,rk3562-otp"; + reg =3D <0x0 0xff930000 0x0 0x4000>; + clocks =3D <&cru CLK_USER_OTPC_NS>, <&cru PCLK_OTPC_NS>, + <&cru PCLK_OTPPHY>, <&cru CLK_SBPI_OTPC_NS>; + clock-names =3D "otp", "apb_pclk", "phy", "sbpi"; + resets =3D <&cru SRST_USER_OTPC_NS>, <&cru SRST_P_OTPC_NS>, + <&cru SRST_P_OTPPHY>, <&cru SRST_SBPI_OTPC_NS>; + reset-names =3D "otp", "apb", "phy", "sbpi"; + + nvmem-layout { + compatible =3D "fixed-layout"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + cpu_code: cpu-code@2 { + reg =3D <0x02 0x2>; + }; + + otp_cpu_version: cpu-version@8 { + reg =3D <0x08 0x1>; + bits =3D <3 3>; + }; + + otp_id: id@a { + reg =3D <0x0a 0x10>; + }; + + cpu_leakage: cpu-leakage@1a { + reg =3D <0x1a 0x1>; + }; + + log_leakage: log-leakage@1b { + reg =3D <0x1b 0x1>; + }; + + npu_leakage: npu-leakage@1c { + reg =3D <0x1c 0x1>; + }; + + gpu_leakage: gpu-leakage@1d { + reg =3D <0x1d 0x1>; + }; + }; + }; + dmac: dma-controller@ff990000 { compatible =3D "arm,pl330", "arm,primecell"; reg =3D <0x0 0xff990000 0x0 0x4000>; --=20 2.47.2 From nobody Sat Feb 7 17:09:40 2026 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DC173330D24 for ; Thu, 5 Feb 2026 21:24:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770326651; cv=none; b=G0flHEG2sh1xuF9/JlCi93loS62ZQsnUvwGu07J2iL/A8WLMEIEOUmxUhvmixjjw+M2nlD4oGxcrSyGaoPEJcm49fqGMV6QfiQwk310SmEb7qht7JmLCThctU8QyRUpj4rZ2jP9O+MxRL7xJXYq4LSBhgBeMQTYyPGsMWPd0bAg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770326651; c=relaxed/simple; bh=ZpSXfzrpOKE0DLjroe+KbpIJ/ddO7WWlHV362LvmFGw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Mew9wngBpQjeQ0FbUtTJbyOXTmAbnoqda0lUJi8B82rfFzXfBYzr8zNwEY/Vxe2wkEvbyyg4LqsGNvHSkeffJnHDZ867bQmu0X3w++uKp498D2Y9zhxcv7VJdBWPUJHFqPU/0Imw90TMD/eTgpERkxK4Q+FvY8CkJr4DQo09M1Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b=D3ZZlSqC; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b="D3ZZlSqC" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-Type; bh=WRPya6AIFwDaMGiHsseB8k3Ge2ToLgr+LbHZKiorHIg=; b=D3ZZlSqC/V8jGbUYAe/9aTMTok 5dPOQSyFo7SoiefracTnJHYvnbe2WapAnhcNCudSRqSh9pwL4sG7jJ1WU3Nl5qy+n6SsHnzmFpXf+ NO0+H1h7chE5OjauXcUYwK3fthUDC2DND2bCK5ujILnxZJwjp3xOUeZuV01NrKSmLCL+ynlKrrSB4 6vPfmOUO66zijmms6b+6unOadVdSM+nHxf/fBt2xjwYvay+UF6332JC8cEsLSse1DTRhyJRKjiQQ0 Wfjop5RafwGNimx7K31lEObm7Uu+CgYOzNdTSy/rwhzAZXsHULNELVaqlTtGrVwT/zWjxXgeJIsjb p2DOJsAw==; Received: from i53875afe.versanet.de ([83.135.90.254] helo=localhost.localdomain) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1vo6pc-007GK0-Ma; Thu, 05 Feb 2026 22:24:09 +0100 From: Heiko Stuebner To: heiko@sntech.de Cc: linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, kever.yang@rock-chips.com, finley.xiao@rock-chips.com, w@1wt.eu, jonas@kwiboo.se Subject: [PATCH 2/3] arm64: dts: rockchip: Enable OTP controller for RK356x Date: Thu, 5 Feb 2026 22:23:46 +0100 Message-ID: <20260205212347.490636-3-heiko@sntech.de> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20260205212347.490636-1-heiko@sntech.de> References: <20260205212347.490636-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable the One Time Programmable Controller (OTPC) in RK356x and add an initial nvmem fixed layout. Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boo= t/dts/rockchip/rk356x-base.dtsi index 8893b7b6cc9f..72c98337f359 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi @@ -1104,6 +1104,52 @@ rng: rng@fe388000 { status =3D "disabled"; }; =20 + otp: otp@fe38c000 { + compatible =3D "rockchip,rk3568-otp"; + reg =3D <0x0 0xfe38c000 0x0 0x4000>; + clocks =3D <&cru CLK_OTPC_NS_USR>, <&cru PCLK_OTPC_NS>, + <&cru PCLK_OTPPHY>, <&cru CLK_OTPC_NS_SBPI>; + clock-names =3D "otp", "apb_pclk", "phy", "sbpi"; + resets =3D <&cru SRST_OTPC_NS_USR>, <&cru SRST_P_OTPC_NS>, + <&cru SRST_OTPPHY>, <&cru SRST_OTPC_NS_SBPI>; + reset-names =3D "otp", "apb", "phy", "sbpi"; + + nvmem-layout { + compatible =3D "fixed-layout"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + cpu_code: cpu-code@2 { + reg =3D <0x02 0x2>; + }; + + otp_cpu_version: cpu-version@8 { + reg =3D <0x08 0x1>; + bits =3D <3 3>; + }; + + otp_id: id@a { + reg =3D <0x0a 0x10>; + }; + + cpu_leakage: cpu-leakage@1a { + reg =3D <0x1a 0x1>; + }; + + log_leakage: log-leakage@1b { + reg =3D <0x1b 0x1>; + }; + + npu_leakage: npu-leakage@1c { + reg =3D <0x1c 0x1>; + }; + + gpu_leakage: gpu-leakage@1d { + reg =3D <0x1d 0x1>; + }; + }; + }; + i2s0_8ch: i2s@fe400000 { compatible =3D "rockchip,rk3568-i2s-tdm"; reg =3D <0x0 0xfe400000 0x0 0x1000>; --=20 2.47.2 From nobody Sat Feb 7 17:09:40 2026 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6DF2733121E for ; Thu, 5 Feb 2026 21:24:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770326651; cv=none; b=sLuqo4DfblQATnBKIi8TWbBGdafSUt1LvDTVf307RtmMI1b0S17i90pAlcxOoE7VN9rh6KgVRiq07ck2OdprHZ2QAUHeJGoDXQErFVz0jU+FRiBVHZ3wgDIcYMPHQddBWN5W3rc6kXeFrCdnkIxHQiDtR3SJ8ui+NkqYzaGReCA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770326651; c=relaxed/simple; bh=Jl7tXaC6DIYRuNHUeQFgm3yXqeMVCHvKuKcyZV9znf8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=REFbB0BvhWiEXnLJKensL8v5cmaaVWnd+4oHQx1DvTkdIuRa3LKZucekkqr7XSmYtSckU5YRZfv2r26tROV73Af08vOtYZzg8QY80RxYLkHf5qQxBQjHgFMGNpD8vxKLQmdtRjIbx+aqsoXtw/ujHjaH+KD7Qxzoh47fTsw+UTw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b=sL4JlmT2; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b="sL4JlmT2" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-Type; bh=5vvatJcVDYv2jsixz0CF+35CybVqCxF1N7tYF0/veLg=; b=sL4JlmT2/cM/n+LPn05/JVHtXq h+UlWA6Q8AWMbBNCIvHKpjlSfXW+TKhUJP5vTvbXbABjbNQHTg3Al2W7NpouIeVbwzSj5KXwx+zrg bs8nktdyZNDjCimlwku+IK1hYd9QjPDCmWeLomQCqVC4ammvLPVDBtFTGwgauqDhjFU9/1758FrZl n9KQEfUx0Tg+1nnc2NgdAVRlbwtH5Q1ZxPvuSabmCf9MbInpFyoRQmA+5nL8l15TjZ3eSwX1UvVLG 4UfGvJyBcGKYg6xLvbE2rOyoufQqr8S/FY5EcH30GSxXiGLQXJGzyTcnS2LgnsEBk2S+Ae3/FaAaq Khwblq9g==; Received: from i53875afe.versanet.de ([83.135.90.254] helo=localhost.localdomain) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1vo6pd-007GK0-1z; Thu, 05 Feb 2026 22:24:09 +0100 From: Heiko Stuebner To: heiko@sntech.de Cc: linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, kever.yang@rock-chips.com, finley.xiao@rock-chips.com, w@1wt.eu, jonas@kwiboo.se Subject: [PATCH 3/3] arm64: dts: rockchip: Enable OTP controller for RK3528 Date: Thu, 5 Feb 2026 22:23:47 +0100 Message-ID: <20260205212347.490636-4-heiko@sntech.de> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20260205212347.490636-1-heiko@sntech.de> References: <20260205212347.490636-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jonas Karlman Enable the One Time Programmable Controller (OTPC) in RK3528 and add an initial nvmem fixed layout. Signed-off-by: Jonas Karlman Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3528.dtsi | 47 ++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts= /rockchip/rk3528.dtsi index d402f2828814..171b48c9cdb7 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi @@ -1190,6 +1190,53 @@ sdmmc: mmc@ffc30000 { status =3D "disabled"; }; =20 + otp: nvmem@ffce0000 { + compatible =3D "rockchip,rk3528-otp"; + reg =3D <0x0 0xffce0000 0x0 0x4000>; + clocks =3D <&cru CLK_USER_OTPC_NS>, <&cru PCLK_OTPC_NS>, + <&cru CLK_SBPI_OTPC_NS>; + clock-names =3D "otp", "apb_pclk", "sbpi"; + resets =3D <&cru SRST_USER_OTPC_NS>, <&cru SRST_P_OTPC_NS>, + <&cru SRST_SBPI_OTPC_NS>; + reset-names =3D "otp", "apb", "sbpi"; + + nvmem-layout { + compatible =3D "fixed-layout"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + cpu_code: cpu-code@2 { + reg =3D <0x02 0x2>; + }; + + otp_cpu_version: cpu-version@8 { + reg =3D <0x08 0x1>; + bits =3D <3 3>; + }; + + otp_id: id@a { + reg =3D <0x0a 0x10>; + }; + + cpu_leakage: cpu-leakage@1a { + reg =3D <0x1a 0x1>; + }; + + logic_leakage: logic-leakage@1b { + reg =3D <0x1b 0x1>; + }; + + gpu_leakage: gpu-leakage@1c { + reg =3D <0x1c 0x1>; + }; + + tsadc_trim: tsadc-trim@44 { + reg =3D <0x44 0x2>; + bits =3D <0 10>; + }; + }; + }; + dmac: dma-controller@ffd60000 { compatible =3D "arm,pl330", "arm,primecell"; reg =3D <0x0 0xffd60000 0x0 0x4000>; --=20 2.47.2