From nobody Mon Feb 9 05:59:33 2026 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4C3753A63EF for ; Thu, 5 Feb 2026 10:21:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770286876; cv=none; b=qHFu0VRifFfocEYXrkx5nr1CiGDlmpWg4aW34UaaifAOvjY7hVESzmqBH0Wiz/b9E1aQbgX06Q1Hn+IpNSygRJZfp2X1025vfYNWxI1dD5ia9osbxeWAlYwT+FCPv3d/yP/l9hH1zeTtRmjO07RSePizbabk7gocCkKHPbyY16I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770286876; c=relaxed/simple; bh=/T3NK/diXd1A5/o4dGbi2BHCZI+4FYU5BNPLZnmfUD8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=i4UDhdN0wHJOshfvtC3C7HoU/5cboJxYe7viYEmh/itTlweIF/jEn3Qkox9rdB2HU/r1YktXzTdvTZNmfRCKzX3dtY5nu21Gy48xfkIDMtn+T7wX/JbXSloKb/cXTIdPoQkSkfiEwajooEiikPXuhJJPsyKhIgrldlqnwV1DvfU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b=liyafqLL; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b="liyafqLL" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-Type; bh=xySJEGujkFZ5SXwhZvO8uWauZklpO37yk1SL78e8tXg=; b=liyafqLL6Ss89F6mVD5XkguWuC GERgLbswu++vGijR1UVRX2VmxV+RrAlvzFDRrBFO/c4LEPmzXtVAZ685xyLLTTWAEE3PjVwDvWxid Yf5AjFHXfBvnRjAdl13ZGZYBv/eENpTZaOjS9l710D15ar0ioF7NjpR9++QZMRU1KK6sb5gOPu/IK m75rjpJ/9xc27Wt+XXGr/suzI3lJirQ04md2vPmU3DjiJFOEXoAGvf0HGxKmHehC0y/X/lt8zemgC pFhny2J5bA0wm+PCAq8srSHrR1DR2MWk1KSzVYQoVHu/5Q7AiyMLa9QWgIOb7MRsSpfl0TebSvd+Y klBRrCTw==; Received: from i53875afe.versanet.de ([83.135.90.254] helo=localhost.localdomain) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1vnwU5-0075El-Rr; Thu, 05 Feb 2026 11:21:14 +0100 From: Heiko Stuebner To: heiko@sntech.de Cc: quentin.schulz@cherry.de, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Heiko Stuebner Subject: [PATCH 2/3] arm64: dts: rockchip: use gated-fixed-clock for pcie-refclk on rk3588-tiger Date: Thu, 5 Feb 2026 11:21:03 +0100 Message-ID: <20260205102104.394991-3-heiko@sntech.de> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20260205102104.394991-1-heiko@sntech.de> References: <20260205102104.394991-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Heiko Stuebner Using a combination of fixed clock and gpio-gate clock works but does not describe the actual hardware. Use the gated-fixed-clock binding to describe this in a nicer way. Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi b/arch/arm64/bo= ot/dts/rockchip/rk3588-tiger.dtsi index 27269b7b08aa..259fb125e13f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi @@ -51,19 +51,14 @@ led-1 { * 100MHz reference clock for PCIe peripherals from PI6C557-05BLE * clock generator. * The clock output is gated via the OE pin on the clock generator. - * This is modeled as a fixed-clock plus a gpio-gate-clock. */ - pcie_refclk_gen: pcie-refclk-gen-clock { - compatible =3D "fixed-clock"; + pcie_refclk: pcie-clock-generator { + compatible =3D "gated-fixed-clock"; #clock-cells =3D <0>; clock-frequency =3D <100000000>; - }; - - pcie_refclk: pcie-refclk-clock { - compatible =3D "gpio-gate-clock"; - clocks =3D <&pcie_refclk_gen>; - #clock-cells =3D <0>; + clock-output-names =3D "pcie3_refclk"; enable-gpios =3D <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; /* PCIE30X4_CLKREQN_M= 1_L */ + vdd-supply =3D <&vcca_3v3_s0>; }; =20 vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { --=20 2.47.2