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Wed, 04 Feb 2026 23:07:02 -0800 (PST) Received: from work.lan ([2409:4091:a0f4:6806:a143:fe87:de49:8a5d]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c6c8553e888sm3819165a12.31.2026.02.04.23.06.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Feb 2026 23:07:01 -0800 (PST) From: Manivannan Sadhasivam To: robh@kernel.org, saravanak@kernel.org Cc: andersson@kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, qiang.yu@oss.qualcomm.com, Manivannan Sadhasivam Subject: [PATCH] of: property: Create devlink between PCI Host bridge and Root Port suppliers Date: Thu, 5 Feb 2026 12:36:40 +0530 Message-ID: <20260205070640.10653-1-manivannan.sadhasivam@oss.qualcomm.com> X-Mailer: git-send-email 2.51.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjA1MDA0OSBTYWx0ZWRfX7DrXRqwwjIDb 2ydBu22pjVz31OIEu4aGg5AVo0qfyaza+z2c6MwkEcTU8jOb2WGnt0Y0EwLoecBHKPSfXgRss/m UqPLc9MRIxKXA/KOp6qpT9xhn7jp4pPm/ID/lkdHNf95o/5XMJA/tIpNLr4qgHnwF1nz0kCCeJf ZVGgZrYfz6aFbWMYYPTUBNU4qkF0FML6ud8TanDBQ+6arcUMUMLPR9xNnAdgKV8EAsEuCPeztlF fLSj3hhb7OUJyhTFgRFIpPPScAIwHfbUn6l+5Eos+5mUmdjocodrsjyE3WhegOc4CR7q5YyiUCN 7bNbeIQmP2zQ7iry9lt5Fe5eL+Wq8GfQot9S3HrlPeIBUvPg3gopGVQo9xyjyJhV84JSz5am9HQ rEDshfTgLJ9lD4DDcyS7zMowfcNuJw2HvrLQFYUTnnb2r5ydHjd9YSprCM925KA9E2ZsJDTEehJ PYxVqqqT+83N9xwxwJQ== X-Proofpoint-ORIG-GUID: aoO08e2KeqEFXiEtWN2JSjQrj1oVddej X-Authority-Analysis: v=2.4 cv=UoBu9uwB c=1 sm=1 tr=0 ts=69844198 cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=xqWC_Br6kY4A:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=n9glyVbX8GFbeWSgBHEA:9 a=uKXjsCUrEbL0IQVhDsJ9:22 X-Proofpoint-GUID: aoO08e2KeqEFXiEtWN2JSjQrj1oVddej X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-05_01,2026-02-04_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 suspectscore=0 bulkscore=0 adultscore=0 malwarescore=0 spamscore=0 lowpriorityscore=0 impostorscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602050049 Content-Type: text/plain; charset="utf-8" In the recent times, devicetree started to represent the PCI Host bridge supplies like PHY in the Root Port nodes as seen in commit 38fcbfbd4207 ("dt-bindings: PCI: qcom: Move PHY & reset GPIO to Root Port node"). But the Host bridge drivers still need to control these supplies as a part of their controller initialization/deinitialization sequence. So the Host bridge drivers end up parsing the Root Port supplies in their probe() and controlled them. A downside to this approach is that the devlink dependency between the suppliers and Host bridge is completely broken. Due to this, the driver core probes the Host bridge drivers even if the suppliers are not ready, causing probe deferrals and setup teardowns in probe(). These probe deferrals sometime happen over 1000 times (as reported in Qcom Glymur platform) leading to a waste of CPU resources and increase in boot time. So to fix these unnecessary deferrals, create devlink between the Host bridge and Root Port suppliers in of_fwnode_add_links(). This will allow the driver core to probe the Host bridge drivers only when all Root Port suppliers are available. Reported-by: Bjorn Andersson Signed-off-by: Manivannan Sadhasivam --- drivers/of/property.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/drivers/of/property.c b/drivers/of/property.c index 50d95d512bf5..10d041ea61f7 100644 --- a/drivers/of/property.c +++ b/drivers/of/property.c @@ -1561,6 +1561,7 @@ static const struct supplier_bindings of_supplier_bin= dings[] =3D { /** * of_link_property - Create device links to suppliers listed in a property * @con_np: The consumer device tree node which contains the property + * @parent_np: Optional parent device tree node requiring child's supplies * @prop_name: Name of property to be parsed * * This function checks if the property @prop_name that is present in the @@ -1577,7 +1578,8 @@ static const struct supplier_bindings of_supplier_bin= dings[] =3D { * device tree nodes even when attempts to create a link to one or more * suppliers fail. */ -static int of_link_property(struct device_node *con_np, const char *prop_n= ame) +static int of_link_property(struct device_node *con_np, struct device_node= *parent_np, + const char *prop_name) { struct device_node *phandle; const struct supplier_bindings *s =3D of_supplier_bindings; @@ -1598,6 +1600,10 @@ static int of_link_property(struct device_node *con_= np, const char *prop_name) matched =3D true; i++; of_link_to_phandle(con_dev_np, phandle, s->fwlink_flags); + + /* Link the child's supplies to parent if needed */ + if (parent_np) + of_link_to_phandle(parent_np, phandle, s->fwlink_flags); of_node_put(phandle); } s++; @@ -1632,7 +1638,21 @@ static int of_fwnode_add_links(struct fwnode_handle = *fwnode) return -EINVAL; =20 for_each_property_of_node(con_np, p) - of_link_property(con_np, p->name); + of_link_property(con_np, NULL, p->name); + + /* + * Supplies for the PCI host bridges are typically present in the Root + * Port nodes. So parse the Root Port supplies and link them to Host + * bridges (identified by the presence of "linux,pci-domain" property). + */ + if (of_property_present(con_np, "linux,pci-domain")) { + for_each_available_child_of_node_scoped(con_np, child) { + if (of_node_is_type(child, "pci")) { + for_each_property_of_node(child, p) + of_link_property(child, con_np, p->name); + } + } + } =20 return 0; } --=20 2.51.0