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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3549c487a7bsm673571a91.16.2026.02.04.17.40.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Feb 2026 17:40:23 -0800 (PST) From: Joey Lu To: andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mcoquelin.stm32@gmail.com, richardcochran@gmail.com Cc: alexandre.torgue@foss.st.com, joabreu@synopsys.com, ychuang3@nuvoton.com, schung@nuvoton.com, yclu4@nuvoton.com, peppe.cavallaro@st.com, linux-arm-kernel@lists.infradead.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, openbmc@lists.ozlabs.org, linux-stm32@st-md-mailman.stormreply.com, Joey Lu , Andrew Lunn Subject: [PATCH net-next v11 3/3] net: stmmac: dwmac-nuvoton: Add dwmac glue for Nuvoton MA35 family Date: Thu, 5 Feb 2026 09:40:05 +0800 Message-ID: <20260205014006.735408-4-a0987203069@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260205014006.735408-1-a0987203069@gmail.com> References: <20260205014006.735408-1-a0987203069@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for Gigabit Ethernet on Nuvoton MA35 series using dwmac driver. Reviewed-by: Andrew Lunn Signed-off-by: Joey Lu --- drivers/net/ethernet/stmicro/stmmac/Kconfig | 12 ++ drivers/net/ethernet/stmicro/stmmac/Makefile | 1 + .../ethernet/stmicro/stmmac/dwmac-nuvoton.c | 173 ++++++++++++++++++ 3 files changed, 186 insertions(+) create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-nuvoton.c diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethe= rnet/stmicro/stmmac/Kconfig index 07088d03dbab..861f1c6c14f1 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Kconfig +++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig @@ -132,6 +132,18 @@ config DWMAC_MESON the stmmac device driver. This driver is used for Meson6, Meson8, Meson8b and GXBB SoCs. =20 +config DWMAC_NUVOTON + tristate "Nuvoton MA35 dwmac support" + default ARCH_MA35 + depends on OF && (ARCH_MA35 || COMPILE_TEST) + select MFD_SYSCON + help + Support for Ethernet controller on Nuvoton MA35 series SoC. + + This selects the Nuvoton MA35 series SoC glue layer support + for the stmmac device driver. The nuvoton-dwmac driver is + used for MA35 series SoCs. + config DWMAC_QCOM_ETHQOS tristate "Qualcomm ETHQOS support" default ARCH_QCOM diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/eth= ernet/stmicro/stmmac/Makefile index c9263987ef8d..4ade030b634f 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Makefile +++ b/drivers/net/ethernet/stmicro/stmmac/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_DWMAC_IPQ806X) +=3D dwmac-ipq806x.o obj-$(CONFIG_DWMAC_LPC18XX) +=3D dwmac-lpc18xx.o obj-$(CONFIG_DWMAC_MEDIATEK) +=3D dwmac-mediatek.o obj-$(CONFIG_DWMAC_MESON) +=3D dwmac-meson.o dwmac-meson8b.o +obj-$(CONFIG_DWMAC_NUVOTON) +=3D dwmac-nuvoton.o obj-$(CONFIG_DWMAC_QCOM_ETHQOS) +=3D dwmac-qcom-ethqos.o obj-$(CONFIG_DWMAC_RENESAS_GBETH) +=3D dwmac-renesas-gbeth.o obj-$(CONFIG_DWMAC_ROCKCHIP) +=3D dwmac-rk.o diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-nuvoton.c b/drivers/= net/ethernet/stmicro/stmmac/dwmac-nuvoton.c new file mode 100644 index 000000000000..dd233e0a32ee --- /dev/null +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-nuvoton.c @@ -0,0 +1,173 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Nuvoton DWMAC specific glue layer + * + * Copyright (C) 2025 Nuvoton Technology Corp. + * + * Author: Joey Lu + */ + +#include +#include +#include +#include +#include +#include + +#include "stmmac.h" +#include "stmmac_platform.h" + +#define NVT_REG_SYS_GMAC0MISCR 0x108 +#define NVT_REG_SYS_GMAC1MISCR 0x10C + +#define NVT_MISCR_RMII BIT(0) + +/* Two thousand picoseconds are evenly mapped to a 4-bit field, + * resulting in each step being 2000/15 picoseconds. + */ +#define NVT_PATH_DELAY_STEP 134 +#define NVT_TX_DELAY_MASK GENMASK(19, 16) +#define NVT_RX_DELAY_MASK GENMASK(23, 20) + +struct nvt_priv_data { + struct platform_device *pdev; + struct regmap *regmap; +}; + +static struct nvt_priv_data * +nvt_gmac_setup(struct platform_device *pdev, struct plat_stmmacenet_data *= plat) +{ + struct device *dev =3D &pdev->dev; + struct nvt_priv_data *bsp_priv; + phy_interface_t phy_mode; + u32 macid, arg, reg; + u32 tx_delay_step; + u32 rx_delay_step; + u32 miscr; + + bsp_priv =3D devm_kzalloc(dev, sizeof(*bsp_priv), GFP_KERNEL); + if (!bsp_priv) + return ERR_PTR(-ENOMEM); + + bsp_priv->regmap =3D + syscon_regmap_lookup_by_phandle_args(dev->of_node, "nuvoton,sys", 1, &ma= cid); + if (IS_ERR(bsp_priv->regmap)) + return ERR_PTR(dev_err_probe(dev, PTR_ERR(bsp_priv->regmap), + "Failed to get sys register\n")); + if (macid > 1) { + dev_err(dev, "Invalid sys arguments\n"); + return ERR_PTR(-EINVAL); + } + + if (of_property_read_u32(dev->of_node, "tx-internal-delay-ps", &arg)) { + tx_delay_step =3D 0; + } else { + if (arg <=3D 2000) { + tx_delay_step =3D (arg =3D=3D 2000) ? 0xf : (arg / NVT_PATH_DELAY_STEP); + dev_dbg(dev, "Set Tx path delay to 0x%x\n", tx_delay_step); + } else { + dev_err(dev, "Invalid Tx path delay argument.\n"); + return ERR_PTR(-EINVAL); + } + } + if (of_property_read_u32(dev->of_node, "rx-internal-delay-ps", &arg)) { + rx_delay_step =3D 0; + } else { + if (arg <=3D 2000) { + rx_delay_step =3D (arg =3D=3D 2000) ? 0xf : (arg / NVT_PATH_DELAY_STEP); + dev_dbg(dev, "Set Rx path delay to 0x%x\n", rx_delay_step); + } else { + dev_err(dev, "Invalid Rx path delay argument.\n"); + return ERR_PTR(-EINVAL); + } + } + + miscr =3D (macid =3D=3D 0) ? NVT_REG_SYS_GMAC0MISCR : NVT_REG_SYS_GMAC1MI= SCR; + regmap_read(bsp_priv->regmap, miscr, ®); + reg &=3D ~(NVT_TX_DELAY_MASK | NVT_RX_DELAY_MASK); + + if (of_get_phy_mode(pdev->dev.of_node, &phy_mode)) { + dev_err(dev, "missing phy mode property\n"); + return ERR_PTR(-EINVAL); + } + + switch (phy_mode) { + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + reg &=3D ~NVT_MISCR_RMII; + break; + case PHY_INTERFACE_MODE_RMII: + reg |=3D NVT_MISCR_RMII; + break; + default: + dev_err(dev, "Unsupported phy-mode (%d)\n", phy_mode); + return ERR_PTR(-EINVAL); + } + + if (!(reg & NVT_MISCR_RMII)) { + reg |=3D FIELD_PREP(NVT_TX_DELAY_MASK, tx_delay_step); + reg |=3D FIELD_PREP(NVT_RX_DELAY_MASK, rx_delay_step); + } + + regmap_write(bsp_priv->regmap, miscr, reg); + + bsp_priv->pdev =3D pdev; + + return bsp_priv; +} + +static int nvt_gmac_probe(struct platform_device *pdev) +{ + struct plat_stmmacenet_data *plat_dat; + struct stmmac_resources stmmac_res; + struct nvt_priv_data *priv_data; + int ret; + + ret =3D stmmac_get_platform_resources(pdev, &stmmac_res); + if (ret) + return ret; + + plat_dat =3D devm_stmmac_probe_config_dt(pdev, stmmac_res.mac); + if (IS_ERR(plat_dat)) + return PTR_ERR(plat_dat); + + /* Nuvoton DWMAC configs */ + plat_dat->core_type =3D DWMAC_CORE_GMAC; + plat_dat->tx_fifo_size =3D 2048; + plat_dat->rx_fifo_size =3D 4096; + plat_dat->multicast_filter_bins =3D 0; + plat_dat->unicast_filter_entries =3D 8; + + priv_data =3D nvt_gmac_setup(pdev, plat_dat); + if (IS_ERR(priv_data)) + return PTR_ERR(priv_data); + + ret =3D stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res); + if (ret) + return ret; + + return 0; +} + +static const struct of_device_id nvt_dwmac_match[] =3D { + { .compatible =3D "nuvoton,ma35d1-dwmac"}, + { } +}; +MODULE_DEVICE_TABLE(of, nvt_dwmac_match); + +static struct platform_driver nvt_dwmac_driver =3D { + .probe =3D nvt_gmac_probe, + .remove =3D stmmac_pltfr_remove, + .driver =3D { + .name =3D "nuvoton-dwmac", + .pm =3D &stmmac_pltfr_pm_ops, + .of_match_table =3D nvt_dwmac_match, + }, +}; +module_platform_driver(nvt_dwmac_driver); + +MODULE_AUTHOR("Joey Lu "); +MODULE_DESCRIPTION("Nuvoton DWMAC specific glue layer"); +MODULE_LICENSE("GPL"); --=20 2.43.0