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Thu, 05 Feb 2026 10:57:15 -0800 (PST) From: Mel Henning Date: Thu, 05 Feb 2026 13:56:10 -0500 Subject: [PATCH v2 1/2] drm/nouveau: Fetch zcull info from device Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260205-zcull3-v2-1-ac572f38cc7b@darkrefraction.com> References: <20260205-zcull3-v2-0-ac572f38cc7b@darkrefraction.com> In-Reply-To: <20260205-zcull3-v2-0-ac572f38cc7b@darkrefraction.com> To: Lyude Paul , Danilo Krummrich , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Mary Guillemard Cc: dri-devel@lists.freedesktop.org, nouveau@lists.freedesktop.org, linux-kernel@vger.kernel.org, Mel Henning X-Mailer: b4 0.14.3 This information will be exposed to userspace in the following commit. Signed-off-by: Mel Henning --- drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h | 19 +++++++++++++ .../gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gr.c | 9 ++++-- .../gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/gr.c | 32 ++++++++++++++++++= ++-- .../drm/nouveau/nvkm/subdev/gsp/rm/r570/nvrm/gr.h | 19 +++++++++++++ drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/rm.h | 2 +- 5 files changed, 75 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h b/drivers/gpu= /drm/nouveau/include/nvkm/engine/gr.h index a2333cfe6955..490ce410f6cb 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h @@ -3,9 +3,28 @@ #define __NVKM_GR_H__ #include =20 +struct nvkm_gr_zcull_info { + __u32 width_align_pixels; + __u32 height_align_pixels; + __u32 pixel_squares_by_aliquots; + __u32 aliquot_total; + __u32 zcull_region_byte_multiplier; + __u32 zcull_region_header_size; + __u32 zcull_subregion_header_size; + __u32 subregion_count; + __u32 subregion_width_align_pixels; + __u32 subregion_height_align_pixels; + + __u32 ctxsw_size; + __u32 ctxsw_align; +}; + struct nvkm_gr { const struct nvkm_gr_func *func; struct nvkm_engine engine; + + struct nvkm_gr_zcull_info zcull_info; + bool has_zcull_info; }; =20 u64 nvkm_gr_units(struct nvkm_gr *); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gr.c b/drivers= /gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gr.c index ddb57d5e73d6..73844e1e7294 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gr.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gr.c @@ -249,7 +249,7 @@ r535_gr_get_ctxbuf_info(struct r535_gr *gr, int i, } =20 static int -r535_gr_get_ctxbufs_info(struct r535_gr *gr) +r535_gr_get_ctxbufs_and_zcull_info(struct r535_gr *gr) { NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS *info; struct nvkm_subdev *subdev =3D &gr->base.engine.subdev; @@ -265,6 +265,9 @@ r535_gr_get_ctxbufs_info(struct r535_gr *gr) r535_gr_get_ctxbuf_info(gr, i, &info->engineContextBuffersInfo[0].engine= [i]); =20 nvkm_gsp_rm_ctrl_done(&gsp->internal.device.subdevice, info); + + gr->base.has_zcull_info =3D false; + return 0; } =20 @@ -312,7 +315,7 @@ r535_gr_oneinit(struct nvkm_gr *base) * * Also build the information that'll be used to create channel contexts. */ - ret =3D rm->api->gr->get_ctxbufs_info(gr); + ret =3D rm->api->gr->get_ctxbufs_and_zcull_info(gr); if (ret) goto done; =20 @@ -352,5 +355,5 @@ r535_gr_dtor(struct nvkm_gr *base) =20 const struct nvkm_rm_api_gr r535_gr =3D { - .get_ctxbufs_info =3D r535_gr_get_ctxbufs_info, + .get_ctxbufs_and_zcull_info =3D r535_gr_get_ctxbufs_and_zcull_info, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/gr.c b/drivers= /gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/gr.c index b6cced9b8aa1..3e7af2ffece9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/gr.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/gr.c @@ -164,9 +164,10 @@ r570_gr_scrubber_init(struct r535_gr *gr) } =20 static int -r570_gr_get_ctxbufs_info(struct r535_gr *gr) +r570_gr_get_ctxbufs_and_zcull_info(struct r535_gr *gr) { NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS *info; + NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS *zcull_info; struct nvkm_subdev *subdev =3D &gr->base.engine.subdev; struct nvkm_gsp *gsp =3D subdev->device->gsp; =20 @@ -179,13 +180,40 @@ r570_gr_get_ctxbufs_info(struct r535_gr *gr) for (int i =3D 0; i < ARRAY_SIZE(info->engineContextBuffersInfo[0].engine= ); i++) r535_gr_get_ctxbuf_info(gr, i, &info->engineContextBuffersInfo[0].engine= [i]); =20 + NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO zcull =3D info->engineCon= textBuffersInfo[0] + .engine[NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHIC= S_ZCULL]; + gr->base.zcull_info.ctxsw_size =3D zcull.size; + gr->base.zcull_info.ctxsw_align =3D zcull.alignment; + nvkm_gsp_rm_ctrl_done(&gsp->internal.device.subdevice, info); + + zcull_info =3D nvkm_gsp_rm_ctrl_rd(&gsp->internal.device.subdevice, + NV2080_CTRL_CMD_GR_GET_ZCULL_INFO, + sizeof(*zcull_info)); + if (WARN_ON(IS_ERR(zcull_info))) + return PTR_ERR(zcull_info); + + gr->base.zcull_info.width_align_pixels =3D zcull_info->widthAlignPixels; + gr->base.zcull_info.height_align_pixels =3D zcull_info->heightAlignPixels; + gr->base.zcull_info.pixel_squares_by_aliquots =3D zcull_info->pixelSquare= sByAliquots; + gr->base.zcull_info.aliquot_total =3D zcull_info->aliquotTotal; + gr->base.zcull_info.zcull_region_byte_multiplier =3D zcull_info->zcullReg= ionByteMultiplier; + gr->base.zcull_info.zcull_region_header_size =3D zcull_info->zcullRegionH= eaderSize; + gr->base.zcull_info.zcull_subregion_header_size =3D zcull_info->zcullSubr= egionHeaderSize; + gr->base.zcull_info.subregion_count =3D zcull_info->subregionCount; + gr->base.zcull_info.subregion_width_align_pixels =3D zcull_info->subregio= nWidthAlignPixels; + gr->base.zcull_info.subregion_height_align_pixels =3D zcull_info->subregi= onHeightAlignPixels; + + nvkm_gsp_rm_ctrl_done(&gsp->internal.device.subdevice, zcull_info); + + gr->base.has_zcull_info =3D true; + return 0; } =20 const struct nvkm_rm_api_gr r570_gr =3D { - .get_ctxbufs_info =3D r570_gr_get_ctxbufs_info, + .get_ctxbufs_and_zcull_info =3D r570_gr_get_ctxbufs_and_zcull_info, .scrubber.init =3D r570_gr_scrubber_init, .scrubber.fini =3D r570_gr_scrubber_fini, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/nvrm/gr.h b/dr= ivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/nvrm/gr.h index feed1dabd9d2..a7a15a4de9d5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/nvrm/gr.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/nvrm/gr.h @@ -76,4 +76,23 @@ typedef struct NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_W= AR_PARAMS { } NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS; =20 #define NV2080_CTRL_CMD_INTERNAL_KGR_INIT_BUG4208224_WAR (0x20800a46) /* f= inn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | N= V2080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_CMD_GR_GET_ZCULL_INFO (0x20801206U) /* finn= : Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTR= L_GR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_SUBREGION_SUPPORTED +#define NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID (0x6U) + +typedef struct NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS { + NvU32 widthAlignPixels; + NvU32 heightAlignPixels; + NvU32 pixelSquaresByAliquots; + NvU32 aliquotTotal; + NvU32 zcullRegionByteMultiplier; + NvU32 zcullRegionHeaderSize; + NvU32 zcullSubregionHeaderSize; + NvU32 subregionCount; + NvU32 subregionWidthAlignPixels; + NvU32 subregionHeightAlignPixels; +} NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS; + #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/rm.h b/drivers/gpu/= drm/nouveau/nvkm/subdev/gsp/rm/rm.h index 393ea775941f..0fb0e67406c6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/rm.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/rm.h @@ -124,7 +124,7 @@ struct nvkm_rm_api { } *ce, *nvdec, *nvenc, *nvjpg, *ofa; =20 const struct nvkm_rm_api_gr { - int (*get_ctxbufs_info)(struct r535_gr *); + int (*get_ctxbufs_and_zcull_info)(struct r535_gr *); struct { int (*init)(struct r535_gr *); void (*fini)(struct r535_gr *); --=20 2.52.0 From nobody Sun Feb 8 05:20:23 2026 Received: from mail-qt1-f175.google.com (mail-qt1-f175.google.com [209.85.160.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EF5F4309F0E for ; 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Thu, 05 Feb 2026 10:57:16 -0800 (PST) Received: from [108.27.160.201] ([108.27.160.201]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-506392902f9sm1678331cf.18.2026.02.05.10.57.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Feb 2026 10:57:16 -0800 (PST) From: Mel Henning Date: Thu, 05 Feb 2026 13:56:11 -0500 Subject: [PATCH v2 2/2] drm/nouveau: Add DRM_IOCTL_NOUVEAU_GET_ZCULL_INFO Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260205-zcull3-v2-2-ac572f38cc7b@darkrefraction.com> References: <20260205-zcull3-v2-0-ac572f38cc7b@darkrefraction.com> In-Reply-To: <20260205-zcull3-v2-0-ac572f38cc7b@darkrefraction.com> To: Lyude Paul , Danilo Krummrich , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Mary Guillemard Cc: dri-devel@lists.freedesktop.org, nouveau@lists.freedesktop.org, linux-kernel@vger.kernel.org, Mel Henning X-Mailer: b4 0.14.3 Add kernel-side support for using the zcull hardware in nvidia gpus. zcull aims to improve memory bandwidth by using an early approximate depth test, similar to hierarchical Z on an AMD card. Add a new ioctl that exposes zcull information that has been read from the hardware. Userspace uses each of these parameters either in a heuristic for determining zcull region parameters or in the calculation of a buffer size. It appears the hardware hasn't changed its structure for these values since FERMI_C (circa 2011), so the assumption is that it won't change on us too quickly, and is therefore reasonable to include in UAPI. This bypasses the nvif layer and instead accesses nvkm_gr directly, which mirrors existing usage of nvkm_gr_units(). There is no nvif object for nvkm_gr yet, and adding one is not trivial. Signed-off-by: Mel Henning --- drivers/gpu/drm/nouveau/nouveau_abi16.c | 29 +++++++++++++++ drivers/gpu/drm/nouveau/nouveau_abi16.h | 1 + drivers/gpu/drm/nouveau/nouveau_drm.c | 1 + include/uapi/drm/nouveau_drm.h | 66 +++++++++++++++++++++++++++++= ++++ 4 files changed, 97 insertions(+) diff --git a/drivers/gpu/drm/nouveau/nouveau_abi16.c b/drivers/gpu/drm/nouv= eau/nouveau_abi16.c index a3ba07fc48a0..91d6f51c5a2f 100644 --- a/drivers/gpu/drm/nouveau/nouveau_abi16.c +++ b/drivers/gpu/drm/nouveau/nouveau_abi16.c @@ -333,6 +333,35 @@ nouveau_abi16_ioctl_getparam(ABI16_IOCTL_ARGS) return 0; } =20 +int +nouveau_abi16_ioctl_get_zcull_info(ABI16_IOCTL_ARGS) +{ + struct nouveau_drm *drm =3D nouveau_drm(dev); + struct nvkm_gr *gr =3D nvxx_gr(drm); + struct drm_nouveau_get_zcull_info *out =3D data; + + if (gr->has_zcull_info) { + const struct nvkm_gr_zcull_info *i =3D &gr->zcull_info; + + out->width_align_pixels =3D i->width_align_pixels; + out->height_align_pixels =3D i->height_align_pixels; + out->pixel_squares_by_aliquots =3D i->pixel_squares_by_aliquots; + out->aliquot_total =3D i->aliquot_total; + out->zcull_region_byte_multiplier =3D i->zcull_region_byte_multiplier; + out->zcull_region_header_size =3D i->zcull_region_header_size; + out->zcull_subregion_header_size =3D i->zcull_subregion_header_size; + out->subregion_count =3D i->subregion_count; + out->subregion_width_align_pixels =3D i->subregion_width_align_pixels; + out->subregion_height_align_pixels =3D i->subregion_height_align_pixels; + out->ctxsw_size =3D i->ctxsw_size; + out->ctxsw_align =3D i->ctxsw_align; + + return 0; + } else { + return -ENODEV; + } +} + int nouveau_abi16_ioctl_channel_alloc(ABI16_IOCTL_ARGS) { diff --git a/drivers/gpu/drm/nouveau/nouveau_abi16.h b/drivers/gpu/drm/nouv= eau/nouveau_abi16.h index af6b4e1cefd2..134b3ab58719 100644 --- a/drivers/gpu/drm/nouveau/nouveau_abi16.h +++ b/drivers/gpu/drm/nouveau/nouveau_abi16.h @@ -6,6 +6,7 @@ struct drm_device *dev, void *data, struct drm_file *file_priv =20 int nouveau_abi16_ioctl_getparam(ABI16_IOCTL_ARGS); +int nouveau_abi16_ioctl_get_zcull_info(ABI16_IOCTL_ARGS); int nouveau_abi16_ioctl_channel_alloc(ABI16_IOCTL_ARGS); int nouveau_abi16_ioctl_channel_free(ABI16_IOCTL_ARGS); int nouveau_abi16_ioctl_grobj_alloc(ABI16_IOCTL_ARGS); diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouvea= u/nouveau_drm.c index 1527b801f013..b698ac38e947 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drm.c +++ b/drivers/gpu/drm/nouveau/nouveau_drm.c @@ -1272,6 +1272,7 @@ nouveau_ioctls[] =3D { DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_abi16_ioctl_grobj_alloc, D= RM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_abi16_ioctl_notifier= obj_alloc, DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_abi16_ioctl_gpuobj_free, D= RM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(NOUVEAU_GET_ZCULL_INFO, nouveau_abi16_ioctl_get_zcull_i= nfo, DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(NOUVEAU_SVM_INIT, nouveau_svmm_init, DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(NOUVEAU_SVM_BIND, nouveau_svmm_bind, DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_RENDER_ALLO= W), diff --git a/include/uapi/drm/nouveau_drm.h b/include/uapi/drm/nouveau_drm.h index dd87f8f30793..1fa82fa6af38 100644 --- a/include/uapi/drm/nouveau_drm.h +++ b/include/uapi/drm/nouveau_drm.h @@ -432,6 +432,69 @@ struct drm_nouveau_exec { __u64 push_ptr; }; =20 +struct drm_nouveau_get_zcull_info { + /** + * @width_align_pixels: required alignment for region widths, in pixels + * (typically #TPC's * 16). + */ + __u32 width_align_pixels; + /** + * @height_align_pixels: required alignment for region heights, in + * pixels (typically 32). + */ + __u32 height_align_pixels; + /** + * @pixel_squares_by_aliquots: the pixel area covered by an aliquot + * (typically #Zcull_banks * 16 * 16). + */ + __u32 pixel_squares_by_aliquots; + /** + * @aliquot_total: the total aliquot pool available in hardware + */ + __u32 aliquot_total; + /** + * @zcull_region_byte_multiplier: the size of an aliquot in bytes, which + * is used for save/restore operations on a region + */ + __u32 zcull_region_byte_multiplier; + /** + * @zcull_region_header_size: the region header size in bytes, which is + * used for save/restore operations on a region + */ + __u32 zcull_region_header_size; + /** + * @zcull_subregion_header_size: the subregion header size in bytes, + * which is used for save/restore operations on a region + */ + __u32 zcull_subregion_header_size; + /** + * @subregion_count: the total number of subregions the hardware + * supports + */ + __u32 subregion_count; + /** + * @subregion_width_align_pixels: required alignment for subregion + * widths, in pixels (typically #TPC's * 16). + */ + __u32 subregion_width_align_pixels; + /** + * @subregion_height_align_pixels: required alignment for subregion + * heights, in pixels + */ + __u32 subregion_height_align_pixels; + + /** + * @ctxsw_size: the size, in bytes, of a zcull context switching region. + * Will be zero if the kernel does not support zcull context switching. + */ + __u32 ctxsw_size; + /** + * @ctxsw_align: the alignment, in bytes, of a zcull context switching + * region + */ + __u32 ctxsw_align; +}; + #define DRM_NOUVEAU_GETPARAM 0x00 #define DRM_NOUVEAU_SETPARAM 0x01 /* deprecated */ #define DRM_NOUVEAU_CHANNEL_ALLOC 0x02 @@ -445,6 +508,7 @@ struct drm_nouveau_exec { #define DRM_NOUVEAU_VM_INIT 0x10 #define DRM_NOUVEAU_VM_BIND 0x11 #define DRM_NOUVEAU_EXEC 0x12 +#define DRM_NOUVEAU_GET_ZCULL_INFO 0x13 #define DRM_NOUVEAU_GEM_NEW 0x40 #define DRM_NOUVEAU_GEM_PUSHBUF 0x41 #define DRM_NOUVEAU_GEM_CPU_PREP 0x42 @@ -513,6 +577,8 @@ struct drm_nouveau_svm_bind { #define DRM_IOCTL_NOUVEAU_VM_INIT DRM_IOWR(DRM_COMMAND_BASE + D= RM_NOUVEAU_VM_INIT, struct drm_nouveau_vm_init) #define DRM_IOCTL_NOUVEAU_VM_BIND DRM_IOWR(DRM_COMMAND_BASE + D= RM_NOUVEAU_VM_BIND, struct drm_nouveau_vm_bind) #define DRM_IOCTL_NOUVEAU_EXEC DRM_IOWR(DRM_COMMAND_BASE + D= RM_NOUVEAU_EXEC, struct drm_nouveau_exec) + +#define DRM_IOCTL_NOUVEAU_GET_ZCULL_INFO DRM_IOR (DRM_COMMAND_BASE + D= RM_NOUVEAU_GET_ZCULL_INFO, struct drm_nouveau_get_zcull_info) #if defined(__cplusplus) } #endif --=20 2.52.0