From nobody Mon Feb 9 14:00:11 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6520D313E17 for ; Thu, 5 Feb 2026 19:07:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770318433; cv=none; b=AymACBhCdw9Q8W9UagKJBxJxke27t2PvAJLbx2Hjcq9Su1W8E5AKbl+Zp71mkZ0qs+kUwQoYG+nYsWm1PZlNYtBR87zJuDKzoIG7ZUB2sT8ZaLaAN8QPXNOxw8B5FeCn+HYTeXbyNAY8+UIuS1Hb0N3P32kz3qB+pEaf1OUrIc4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770318433; c=relaxed/simple; bh=FknqC59Pjh4glzE0SB6TxNJb2mBOqsygzb2ElZBtEW8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=AG8UKQuCkwP5QcJJvr/rAPmP//RFf205vQ+eyj/qvNzLNCMQe9bXHhP9BAeXbnFJvP2S98oZXGKSLEHfGQbMaDHW6xFzC8esSyWq7AOKA6dLIcvsiYeOkrLG2ft0OfzDNnBl5EOEtV0UXoXcLOPjA+EahdqRQWFV6WwGxZKFdCc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=zrZK+Cko; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="zrZK+Cko" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id 0E3B51A2C36; Thu, 5 Feb 2026 19:07:12 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id D311B6074D; Thu, 5 Feb 2026 19:07:11 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 7685D119D1700; Thu, 5 Feb 2026 20:07:09 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1770318431; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=6dF/17CA4aFWIO+80ewE32jYEzEuuauKlwQf6WYBUQo=; b=zrZK+CkoK6bofm8eBAttaZNEVv+aghn2O+YH3IE6CEniuKxy+0xH+AvY2yoOupOC89/1Qw 8q/dYNe0ot67DvC/Mez8n2kC2kKlzFarAChTp9UmekqBWSuDuNwG+Y4coLudRK7GaR4XS1 YvMNZFM3SBioejL93oslTNqneiXuPlKdWjh3L46AZ9AMiEnxsVQFWncmdX5ndE0J8xVgnv zziGK0E7pFSYwi8bAe6fY0vNYgJ2g6npvTUBTXFd1b5SYh7bcan2wKGWQAlP/PHHebLMS3 XoYCOs9CSJy0SDjs+OPL5DYA2sOgi/5RoHoWKdu9JCL6VzEFQlI9pXm+qqE0ZA== From: Miquel Raynal Date: Thu, 05 Feb 2026 20:06:58 +0100 Subject: [PATCH RFC 1/4] spi: spi-mem: Flag DQS capability Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260205-winbond-nand-next-phy-tuning-v1-1-5e7d3976f0f1@bootlin.com> References: <20260205-winbond-nand-next-phy-tuning-v1-0-5e7d3976f0f1@bootlin.com> In-Reply-To: <20260205-winbond-nand-next-phy-tuning-v1-0-5e7d3976f0f1@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Thomas Petazzoni , praneeth@ti.com, u-kumar1@ti.com, p-mantena@ti.com, a-dutta@ti.com, s-k6@ti.com, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 DQS is a typical SPI memory signal used to help with reading the data on the bus at high speeds (especially in DTR mode) by avoiding clock skews. The chip generates a clock signal synchronized with its data output fronts, also called data strobe. SPI NOR and SPI NAND cores must set this flag in order to indicate to other layers that DQS is available. Create a getter and a setter to reach this capability. Signed-off-by: Miquel Raynal Acked-by: Mark Brown --- drivers/spi/spi-mem.c | 32 ++++++++++++++++++++++++++++++++ include/linux/spi/spi-mem.h | 4 ++++ 2 files changed, 36 insertions(+) diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c index 444bd8ec34f5..b746a821c984 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c @@ -534,6 +534,38 @@ const char *spi_mem_get_name(struct spi_mem *mem) } EXPORT_SYMBOL_GPL(spi_mem_get_name); =20 +/** + * spi_mem_set_dqs() - Mark DQS as being available + * @mem: the SPI memory + * + * When reading at high frequencies (> 100MHz), especially when DTR is ena= bled, + * transfer speed is limited due to clock skews. In particular, the contro= ller + * does not know the board propagation delay nor the memory chip internal = delay + * (clock in to data out) and thus cannot optimize its sampling points. + * Mitigating this limitation is possible with the addition of a data stro= be + * signal, commonly named DQS. + * + * Set the DQS boolean if the feature is available and configured at the c= hip + * level. Controllers may query this value. + */ +void spi_mem_set_dqs(struct spi_mem *mem) +{ + mem->dqs =3D true; +} +EXPORT_SYMBOL_GPL(spi_mem_set_dqs); + +/** + * spi_mem_has_dqs() - Query whether the DQS is available or not + * @mem: the SPI memory + * + * Return: a boolean indicating whether the DQS signal is available or not. + */ +bool spi_mem_has_dqs(struct spi_mem *mem) +{ + return mem->dqs; +} +EXPORT_SYMBOL_GPL(spi_mem_has_dqs); + /** * spi_mem_adjust_op_size() - Adjust the data size of a SPI mem operation = to * match controller limitations diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h index a0543ca09da4..b58963242ba6 100644 --- a/include/linux/spi/spi-mem.h +++ b/include/linux/spi/spi-mem.h @@ -259,6 +259,7 @@ struct spi_mem_dirmap_desc { * @spi: the underlying SPI device * @drvpriv: spi_mem_driver private data * @name: name of the SPI memory device + * @dqs: extra data trobe pin available for high frequency read operations * * Extra information that describe the SPI memory device and may be needed= by * the controller to properly handle this device should be placed here. @@ -270,6 +271,7 @@ struct spi_mem { struct spi_device *spi; void *drvpriv; const char *name; + bool dqs; }; =20 /** @@ -440,6 +442,8 @@ bool spi_mem_default_supports_op(struct spi_mem *mem, } #endif /* CONFIG_SPI_MEM */ =20 +void spi_mem_set_dqs(struct spi_mem *mem); +bool spi_mem_has_dqs(struct spi_mem *mem); int spi_mem_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op); void spi_mem_adjust_op_freq(struct spi_mem *mem, struct spi_mem_op *op); u64 spi_mem_calc_op_duration(struct spi_mem *mem, struct spi_mem_op *op); --=20 2.51.1 From nobody Mon Feb 9 14:00:11 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 837B1314D03 for ; Thu, 5 Feb 2026 19:07:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770318435; cv=none; b=lJNYmaHzqtFrZtFzD1nsC5wpMZWjpTcu6zRA7caY9HYmvokok2To/Y/ini9UveM8rOPBNkbzVoowvPRC9HWsCycfTcfrksUj2A/3obtt6/X9Lh8ckTAakHoJMJZomOP5iANQRGTW7Y/leTITaLJIwj6jZBMqw8t8/KAPKWUwmNc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770318435; c=relaxed/simple; bh=gL0MO5i4yl4cd8Ysu3IS9ZJCBbFeLpuuqhGpzKERqpQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=LC3vNfxhxh3c6N4ZZxfu1kFFMphlwq3MaSdV+0l0w4L/vZQHSntqafwfa+E1JkJXsuR6XaTQeSEiMtAGLpmbBBzKOFuPTjk1xqy9AHz/1/pPYWtCliTmAoO1SOPE5m1UZomGKcDwi4hAIh0HPZA3AXSZuXYs2oRL3qiL1hkAZas= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=IKjNbScy; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="IKjNbScy" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id 41B381A2C34; Thu, 5 Feb 2026 19:07:14 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 18ACA6074D; Thu, 5 Feb 2026 19:07:14 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 9F7EE119D1750; Thu, 5 Feb 2026 20:07:11 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1770318433; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=BpN8z+kIDrZwG5aYIIQwAbhujY/X57BjDOA4OXNNt5U=; b=IKjNbScyxiCWSy2AsHFNMEJUi48XhsOcZqxIPvPwn1COX5iJ1z9G5/O5BygSEOUlUC5puN ShRwiOqUNxajOf/8BsVnL6rnvbMJksMlGYGS5/2z6zTN1rp/uzYfRBkS2IGDuESKEsc6XM dhSz6PiqGjZPNAxSrYzkDYFYMFcNUw80rEK1bHqBXdqEwmPgBVoc6Y2nzTYjW80FIaMWsl 4f8hC9lTitTbFQ2Thvcb9vGXt0osF5+DRc8uXv1rI8lvcKdi+c52X/7HaZIEQY8sFJRo9n +yDyfLk2mMivtIi3EibJ1jTNVF8cfV8J/PasDJXJdKh/sxL8F7Z1NdtKpsVmRg== From: Miquel Raynal Date: Thu, 05 Feb 2026 20:06:59 +0100 Subject: [PATCH RFC 2/4] mtd: spi-nand: Set the DQS spi-mem capability if available Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260205-winbond-nand-next-phy-tuning-v1-2-5e7d3976f0f1@bootlin.com> References: <20260205-winbond-nand-next-phy-tuning-v1-0-5e7d3976f0f1@bootlin.com> In-Reply-To: <20260205-winbond-nand-next-phy-tuning-v1-0-5e7d3976f0f1@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Thomas Petazzoni , praneeth@ti.com, u-kumar1@ti.com, p-mantena@ti.com, a-dutta@ti.com, s-k6@ti.com, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Check whether the NAND is capable of generating a DQS signal and set the flag accordingly. Not wiring the DQS signal on a DQS capable chip that will be used at frequency requiring this signal may be considered a hardware bug, so let's assume this line will be routed "in most cases". If/when we get issues with this assumption, a DT property describing the lacking line in the routing can be created. Signed-off-by: Miquel Raynal --- drivers/mtd/nand/spi/core.c | 4 ++++ include/linux/mtd/spinand.h | 1 + 2 files changed, 5 insertions(+) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 95df4dd5330d..67270e49c179 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -1974,6 +1974,10 @@ static int spinand_probe(struct spi_mem *mem) read_op =3D *spinand->op_templates->read_cache; write_op =3D *spinand->op_templates->write_cache; =20 + /* Assume manufacturer drivers will enable the DQS pin if it is available= */ + if (spinand->flags & SPINAND_HAS_DQS) + spi_mem_set_dqs(mem); + ret =3D spi_mem_execute_tuning(mem, &read_op, &write_op); if (ret && ret !=3D -EOPNOTSUPP) { dev_warn(&mem->spi->dev, "Failed to execute PHY tuning: %d\n", diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index 58abd306ebe3..72babba69c7a 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -483,6 +483,7 @@ struct spinand_ecc_info { #define SPINAND_HAS_PROG_PLANE_SELECT_BIT BIT(2) #define SPINAND_HAS_READ_PLANE_SELECT_BIT BIT(3) #define SPINAND_NO_RAW_ACCESS BIT(4) +#define SPINAND_HAS_DQS BIT(5) =20 /** * struct spinand_ondie_ecc_conf - private SPI-NAND on-die ECC engine stru= cture --=20 2.51.1 From nobody Mon Feb 9 14:00:11 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C8249313E2F for ; Thu, 5 Feb 2026 19:07:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770318438; cv=none; b=bacTbFFDmAgUrncno1RngBp58c+xOPrfo4O3qGMob9UTipl9ANr1VMEDDfOR36DBlJ4vdiPlv+lMvZlewmC6khNG18jXMivmlq8nq5I00HZhbbArIKX/ackqnjYZoAeExzqPm0Q7UpqGzFkW5vaVvswGGTgiBnZ0eGrwGoHQyOA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770318438; c=relaxed/simple; bh=y8b4WMelJUB37lemSSU0kVvZc6ACW4vDsXwVaNigLwc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=l3fpdlCywpIbYZjvEjKRRT4J2RVzSvUXrYj3JStKregA62xmwgihElTnkG5WhFIk648V141thnmYzLo8Qkh5vYt6JcgK+IGQbvZNE88O7ep1Wnv7olz7V2JG8nc5MwAPMQ4LRfKGbwV4+4MCsmwKSUjW+totz/qBA8tkthmivaw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=rjUwHRu9; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="rjUwHRu9" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id 6C7D64E42428; Thu, 5 Feb 2026 19:07:16 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 438C06074D; Thu, 5 Feb 2026 19:07:16 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id CF3F5119D1700; Thu, 5 Feb 2026 20:07:13 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1770318435; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=XDXLiZY8XfAXjeC91sKPVk2e9adP7fRa4aGhrR6KVTY=; b=rjUwHRu9Qkn6W14cO/ZKOSolIGLNSKocJm4zDypZWWqeDewMU1T56965ZkP03j+DoH2tBI 6xdB7q+4xp1bAvm9HnG+gIREmDWdoqTTcBudla5AXh+31r5ZZHzPw/BuvCRY5UHX56xDcx J1aHYwjE6/hG2tWCaq3fotlIrPme3f4gPMN6WXoFQR/e6mDuoUv8yEHppczTOctHX07LdL g5Tdp28aSUhSC+yH5k+5diRJxghBVR2yeBYv060qEfxouDgAK22ooEWb//1qOq+C1VpPi6 1JgWE3gJMXQQl8GjqWqVPx0NXJDpFM1g+ZHculSIwFdqR9gV8ZRqtmNdK/DgHg== From: Miquel Raynal Date: Thu, 05 Feb 2026 20:07:00 +0100 Subject: [PATCH RFC 3/4] mtd: spi-nand: winbond: Enable the DQS pin on W35N**JW series Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260205-winbond-nand-next-phy-tuning-v1-3-5e7d3976f0f1@bootlin.com> References: <20260205-winbond-nand-next-phy-tuning-v1-0-5e7d3976f0f1@bootlin.com> In-Reply-To: <20260205-winbond-nand-next-phy-tuning-v1-0-5e7d3976f0f1@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Thomas Petazzoni , praneeth@ti.com, u-kumar1@ti.com, p-mantena@ti.com, a-dutta@ti.com, s-k6@ti.com, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 These chips have a DQS pin, enable it by default in DTR mode because there is apparently no issue in setting it for lower frequencies, and the extra power consumption seems very low compared to the current drawn by the NAND array itself while operating. This setting will be required for high speed I/O transfers (with PHY tuning). Signed-off-by: Miquel Raynal --- drivers/mtd/nand/spi/winbond.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c index 6dfd0dcc8ee7..7401ee1007c0 100644 --- a/drivers/mtd/nand/spi/winbond.c +++ b/drivers/mtd/nand/spi/winbond.c @@ -437,7 +437,7 @@ static int w35n0xjw_vcr_cfg(struct spinand_device *spin= and, else if (!single && !dtr) io_mode =3D W35N01JW_VCR_IO_MODE_OCTAL_SDR; else if (!single && dtr) - io_mode =3D W35N01JW_VCR_IO_MODE_OCTAL_DDR; + io_mode =3D W35N01JW_VCR_IO_MODE_OCTAL_DDR_DS; else return -EINVAL; =20 @@ -504,7 +504,7 @@ static const struct spinand_info winbond_spinand_table[= ] =3D { SPINAND_INFO_OP_VARIANTS(&read_cache_octal_variants, &write_cache_octal_variants, &update_cache_octal_variants), - 0, + SPINAND_HAS_DQS, SPINAND_INFO_VENDOR_OPS(&winbond_w35_ops), SPINAND_ECCINFO(&w35n01jw_ooblayout, NULL), SPINAND_CONFIGURE_CHIP(w35n0xjw_vcr_cfg)), @@ -515,7 +515,7 @@ static const struct spinand_info winbond_spinand_table[= ] =3D { SPINAND_INFO_OP_VARIANTS(&read_cache_octal_variants, &write_cache_octal_variants, &update_cache_octal_variants), - 0, + SPINAND_HAS_DQS, SPINAND_INFO_VENDOR_OPS(&winbond_w35_ops), SPINAND_ECCINFO(&w35n01jw_ooblayout, NULL), SPINAND_CONFIGURE_CHIP(w35n0xjw_vcr_cfg)), @@ -526,7 +526,7 @@ static const struct spinand_info winbond_spinand_table[= ] =3D { SPINAND_INFO_OP_VARIANTS(&read_cache_octal_variants, &write_cache_octal_variants, &update_cache_octal_variants), - 0, + SPINAND_HAS_DQS, SPINAND_INFO_VENDOR_OPS(&winbond_w35_ops), SPINAND_ECCINFO(&w35n01jw_ooblayout, NULL), SPINAND_CONFIGURE_CHIP(w35n0xjw_vcr_cfg)), --=20 2.51.1 From nobody Mon Feb 9 14:00:11 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 453C9313E2F for ; Thu, 5 Feb 2026 19:07:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770318441; cv=none; b=E1lafsh0KoxqemDnEmnRbVd5AtCC+s9YNJe3gg9zCuOG/yDv6lJKvbTvGZcPuZjOTMrxb6l7jBZNP/uRzwLEqzh5iiKc+OwlQoVMSAGcPqLDKWlcx6vMhNng7tHYtBZjmrfTeIGv7sdeJObOC4ueeZNoPfkKQizX22HFXx67/2w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770318441; c=relaxed/simple; bh=0ZtYMNIrVVrkdSY3M3AQ9WB/wN01k0rFv3mR889UOsc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=PKsVlkZDsxQtGFSGhl25aU7EE6VqhqpCwAX93iDfMCRz8mfbBAxJW5dvgIx9cOlNEWrgmqVNR4Q0JfSzVWg9jhb68o92vpN7iX8geQxFgL4JWsREdwV85dm6HyjP+ETXhueHEk4VZk5objhedUJNATRAEDvUaa4rRGdKOyKfrNc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=ciHAmq+n; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="ciHAmq+n" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id 9F210C243B7; Thu, 5 Feb 2026 19:07:24 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 64BFF6074D; Thu, 5 Feb 2026 19:07:18 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id E2208119D178B; Thu, 5 Feb 2026 20:07:15 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1770318437; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=dYYkOMmkvYm09ui+5e6ZadWbVo/SG1FMXVi2GURuVG8=; b=ciHAmq+nFySpzxqrOxnRMm491XzCE3ClAKpYW74F8w8q08takX5II9/7Nk/xgQyhIByA3b vD4f+Git2Nrq5ypf7ZFmDJF6i+48n8KG89drsVwtyu7bDdA5QBFreqZ1c8feMYvA8I4b8O ytC7XhvkgtsEEfK567U6lWksCetzINMiyyKcWt0VWM95EcK8kMQcPuIqFjlNKZUDnM/URq k0XyoK/ls801GlMSGAmMMmxdXhg1gyb4RGb68mp/bXkAOJ5FVLF2YcXzgRtmrpIQEgJkOP OyaeKqe3+3tF7N19oRwuU1B81REHxTU8un9CFOK3wdj9mIEZ38u/y7EUyowy7A== From: Miquel Raynal Date: Thu, 05 Feb 2026 20:07:01 +0100 Subject: [PATCH DO NOT MERGE RFC 4/4] spi: cadence-qspi: Retrieve DQS capability using the core helper Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260205-winbond-nand-next-phy-tuning-v1-4-5e7d3976f0f1@bootlin.com> References: <20260205-winbond-nand-next-phy-tuning-v1-0-5e7d3976f0f1@bootlin.com> In-Reply-To: <20260205-winbond-nand-next-phy-tuning-v1-0-5e7d3976f0f1@bootlin.com> To: Mark Brown , Richard Weinberger , Vignesh Raghavendra Cc: Thomas Petazzoni , praneeth@ti.com, u-kumar1@ti.com, p-mantena@ti.com, a-dutta@ti.com, s-k6@ti.com, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 This is just a suggestion for Santhosh on how to get the DQS capability information without the DT property, to introduce in his Cadence QSPI PHY tuning series: https://lore.kernel.org/linux-spi/87v7gbdwdh.fsf@bootlin.com/T/#t This patch shall not be applied as-is and is just given as an FYI. Signed-off-by: Miquel Raynal --- drivers/spi/spi-cadence-quadspi.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index 4f799f747346..0809846a6ef0 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -3476,6 +3476,12 @@ static int cqspi_mem_op_execute_tuning(struct spi_me= m *mem, if (!cqspi->ddata->execute_tuning) return -EOPNOTSUPP; =20 + /* + * FIXME: maybe this boolean could be queried when needed by + * saving a pointer to the spi memory somewhere? + */ + cqspi->f_pdata->has_dqs =3D spi_mem_has_dqs(mem); + return cqspi->ddata->execute_tuning(mem, read_op, write_op); } =20 @@ -3517,8 +3523,6 @@ static int cqspi_of_get_flash_pdata(struct platform_d= evice *pdev, f_pdata->non_phy_clk_rate =3D f_pdata->cqspi->ddata->get_non_phy_clk_rate(f_pdata->cqspi); =20 - f_pdata->has_dqs =3D of_property_read_bool(np, "spi-has-dqs"); - return 0; } =20 --=20 2.51.1