From nobody Mon Feb 9 14:10:05 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B57482FE595; Thu, 5 Feb 2026 18:10:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770315012; cv=none; b=IaNO9f47mIJpWI/DfOUBNtEPxxJjSm2utE5WMv5lrj4U9Oy6rx59oKxLrAfIGD10YKQVFmPs/A9F7484NzoekpFmvkbu6FeOUeCDmf+ASlG4z62fjZrWNq29I6muyqVf73Dt0vG/wfSVWqTFk2FVE2mAB+7wncFQqB9Lgm7FcQg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770315012; c=relaxed/simple; bh=Pt5FlRkEKwzIGfewhqHR8A78kJ71IAiCm7pqKrlRxSE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Wml3A6CYTB5zGbrLhMORoOqtFjaskPVP4fNXtAUuzG/hI4TjkVkCtfrp5i558T2p1CNl2OLDBrOnoA/JXtFs1JdroyzFMeOwZ1RteD/8qDfZ3tQ21PC1Vc7e0OQFH1JatRJx+3FoFq+D1qcJz5YuTuQo+1Yg9D84xrHh47MObMo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=UG56/n9M; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="UG56/n9M" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id 4965D4E42427; Thu, 5 Feb 2026 18:10:11 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 1E8876074D; Thu, 5 Feb 2026 18:10:11 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 4A15F119D170F; Thu, 5 Feb 2026 19:10:07 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1770315009; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=/HEikuqB/j/cT8sdeHhmkNX1YhSQzvZ02fJms5jDTDI=; b=UG56/n9MAsv6+BVZf65cGqC0f/P7AUdvq2+qZgk2Sd4Kmax4ic8lB51b1x3Sn34NWufGaw R8roi8wqwrHRo7IXwOlMBPG7XDXQyRyjeuzGBDXNiG5BAecknhLoSC9dpML4lqNofO01xm K3VfL1lkhraiwTDVJXJkcg6IuA9De9nQH85gu8cWEUMb5llFCX1RdRECi5DHCLKJunB92D +OyzBSv7Jwcz/5zvo3w0NKWpox1HTYcZtFK/1RhzshOMiCXjaXvhhZLaTGBVODc+howbsZ +W3TZPTq+sLIux+C7kpubyO6XObmCHiag4VQm+Qno4VzSAbeFzOhNS8EK6HBlw== From: "Miquel Raynal (Schneider Electric)" Date: Thu, 05 Feb 2026 19:09:48 +0100 Subject: [PATCH v5 1/4] spi: dt-bindings: cdns,qspi-nor: Add Renesas RZ/N1D400 to the list Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260205-schneider-6-19-rc1-qspi-v5-1-843632b3c674@bootlin.com> References: <20260205-schneider-6-19-rc1-qspi-v5-0-843632b3c674@bootlin.com> In-Reply-To: <20260205-schneider-6-19-rc1-qspi-v5-0-843632b3c674@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Vaishnav Achath Cc: Thomas Petazzoni , =?utf-8?q?Herv=C3=A9_Codina?= , Wolfram Sang , Vignesh Raghavendra , Santhosh Kumar K , Pratyush Yadav , Pascal Eberhard , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, "Miquel Raynal (Schneider Electric)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Add support for the Renesas RZ/N1D400 QSPI controller. This SoC is identified in the bindings with its other name: r9a06g032. It is part of the RZ/N1 family, which contains a "D" and a "S" variant. IPs in this SoC are typically described using 2 compatibles: the SoC specific compatible and the family compatible. The original Cadence IP compatible is dropped because it is unusable on its own. Indirect accesses are not supported by this flavour of the Cadence IP, which means several properties have no meaning in the scope of the Renesas compatible. Let's make sure they are no longer expected nor mandatory. Tested-by: Wolfram Sang Reviewed-by: Rob Herring (Arm) Signed-off-by: Miquel Raynal (Schneider Electric) --- .../devicetree/bindings/spi/cdns,qspi-nor.yaml | 19 +++++++++++++++= ++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Doc= umentation/devicetree/bindings/spi/cdns,qspi-nor.yaml index 0d47bd94d67e..891f578b5ac4 100644 --- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml @@ -61,6 +61,20 @@ allOf: cdns,fifo-depth: enum: [ 128, 256 ] default: 128 + - if: + properties: + compatible: + contains: + const: renesas,rzn1-qspi + then: + properties: + cdns,trigger-address: false + cdns,fifo-depth: false + cdns,fifo-width: false + else: + required: + - cdns,trigger-address + - cdns,fifo-depth =20 properties: compatible: @@ -80,6 +94,9 @@ properties: # controllers are meant to be used with flashes of all kinds, # ie. also NAND flashes, not only NOR flashes. - const: cdns,qspi-nor + - items: + - const: renesas,r9a06g032-qspi + - const: renesas,rzn1-qspi - const: cdns,qspi-nor deprecated: true =20 @@ -163,8 +180,6 @@ required: - reg - interrupts - clocks - - cdns,fifo-width - - cdns,trigger-address - '#address-cells' - '#size-cells' =20 --=20 2.51.1 From nobody Mon Feb 9 14:10:05 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7211E301024 for ; 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arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="pR6IxgBA" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id E38AEC243B2; Thu, 5 Feb 2026 18:10:20 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id B0D486074D; Thu, 5 Feb 2026 18:10:14 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 7F426119D1711; Thu, 5 Feb 2026 19:10:10 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1770315013; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=fSuCg3K7Jx0Gwv/8AMmGnZqgPu9OCuOQpbJh8hioD/g=; b=pR6IxgBA0tLEiL2O2qlWJXGpPWGZRegEJFUqpkFXEuJ5yOlan38RwbwEi28Yxbs8Gns3L4 +Jd7ecWoSqYRLSPyagvuxnfWhJzrHPWXOz9cLFQpXHqMary/3OzLW+gO7We4MEV0AVsbYf UIZf3DJsIeIxwOoe59q0WSXl0S92H6e+i9p4+8nUp1qVMhGcU6zLJFfmPDzBlrB/vdSnGC Hoa7mhp3KAyzXAsQOjvl3awrzSFGt53+pfKcwR1on/ZUmZmsl4yTB41g74zOjM4cnG2+EM l2NYgVM0EAMwUGDq4LA+oxL7hy7TSg259pNqJS9EHO1W5cnrkCPbC8l8uJFHjA== From: "Miquel Raynal (Schneider Electric)" Date: Thu, 05 Feb 2026 19:09:49 +0100 Subject: [PATCH v5 2/4] spi: cadence-qspi: Kill cqspi_jh7110_clk_init Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260205-schneider-6-19-rc1-qspi-v5-2-843632b3c674@bootlin.com> References: <20260205-schneider-6-19-rc1-qspi-v5-0-843632b3c674@bootlin.com> In-Reply-To: <20260205-schneider-6-19-rc1-qspi-v5-0-843632b3c674@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Vaishnav Achath Cc: Thomas Petazzoni , =?utf-8?q?Herv=C3=A9_Codina?= , Wolfram Sang , Vignesh Raghavendra , Santhosh Kumar K , Pratyush Yadav , Pascal Eberhard , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, "Miquel Raynal (Schneider Electric)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 This controller can be fed by either a main "ref" clock, or three clocks ("ref" again, "ahb", "apb"). In practice, it is likely that all controllers have the same inputs, but a single clock feeds the three interfaces (ref is used for controlling the external interface, ahb/apb the internal ones). Handling these clocks is in no way SoC specific, only the number of expected clocks may change. Plus, we will soon be adding another controller requiring an AHB and an APB clock as well, so it is time to align the whole clock handling. Furthermore, the use of the cqspi_jh7110_clk_init() helper, which specifically grabs and enables the "ahb" and "apb" clocks, is a bit convoluted: - only the JH7110 compatible provides the ->jh7110_clk_init() callback, - in the probe, if the above callback is set in the driver data, the driver does not call the callback (!) but instead calls the helper directly (?), - in the helper, the is_jh7110 boolean is set. This logic does not make sense. Instead: - in the probe, set the is_jh7110 boolean based on the compatible, - collect all available clocks with the "bulk" helper, - enable the extra clocks if they are available, - kill the SoC specific cqspi_jh7110_clk_init() helper. This also allows to group the clock handling instead of depending on the driver data pointer, which further simplifies the error path and the remove callback. Tested-by: Wolfram Sang Signed-off-by: Miquel Raynal (Schneider Electric) --- drivers/spi/spi-cadence-quadspi.c | 112 ++++++++++------------------------= ---- 1 file changed, 29 insertions(+), 83 deletions(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index 2d287950d44c..f14a746cba2d 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -57,7 +57,8 @@ static_assert(CQSPI_MAX_CHIPSELECT <=3D SPI_DEVICE_CS_CNT= _MAX); #define CQSPI_OP_WIDTH(part) ((part).nbytes ? ilog2((part).buswidth) : 0) =20 enum { - CLK_QSPI_APB =3D 0, + CLK_QSPI_REF =3D 0, + CLK_QSPI_APB, CLK_QSPI_AHB, CLK_QSPI_NUM, }; @@ -78,8 +79,7 @@ struct cqspi_flash_pdata { struct cqspi_st { struct platform_device *pdev; struct spi_controller *host; - struct clk *clk; - struct clk *clks[CLK_QSPI_NUM]; + struct clk_bulk_data clks[CLK_QSPI_NUM]; unsigned int sclk; =20 void __iomem *iobase; @@ -123,8 +123,6 @@ struct cqspi_driver_platdata { int (*indirect_read_dma)(struct cqspi_flash_pdata *f_pdata, u_char *rxbuf, loff_t from_addr, size_t n_rx); u32 (*get_dma_status)(struct cqspi_st *cqspi); - int (*jh7110_clk_init)(struct platform_device *pdev, - struct cqspi_st *cqspi); }; =20 /* Operation timeout value */ @@ -1771,51 +1769,6 @@ static int cqspi_setup_flash(struct cqspi_st *cqspi) return 0; } =20 -static int cqspi_jh7110_clk_init(struct platform_device *pdev, struct cqsp= i_st *cqspi) -{ - static struct clk_bulk_data qspiclk[] =3D { - { .id =3D "apb" }, - { .id =3D "ahb" }, - }; - - int ret =3D 0; - - ret =3D devm_clk_bulk_get(&pdev->dev, ARRAY_SIZE(qspiclk), qspiclk); - if (ret) { - dev_err(&pdev->dev, "%s: failed to get qspi clocks\n", __func__); - return ret; - } - - cqspi->clks[CLK_QSPI_APB] =3D qspiclk[0].clk; - cqspi->clks[CLK_QSPI_AHB] =3D qspiclk[1].clk; - - ret =3D clk_prepare_enable(cqspi->clks[CLK_QSPI_APB]); - if (ret) { - dev_err(&pdev->dev, "%s: failed to enable CLK_QSPI_APB\n", __func__); - return ret; - } - - ret =3D clk_prepare_enable(cqspi->clks[CLK_QSPI_AHB]); - if (ret) { - dev_err(&pdev->dev, "%s: failed to enable CLK_QSPI_AHB\n", __func__); - goto disable_apb_clk; - } - - cqspi->is_jh7110 =3D true; - - return 0; - -disable_apb_clk: - clk_disable_unprepare(cqspi->clks[CLK_QSPI_APB]); - - return ret; -} - -static void cqspi_jh7110_disable_clk(struct platform_device *pdev, struct = cqspi_st *cqspi) -{ - clk_disable_unprepare(cqspi->clks[CLK_QSPI_AHB]); - clk_disable_unprepare(cqspi->clks[CLK_QSPI_APB]); -} static int cqspi_probe(struct platform_device *pdev) { const struct cqspi_driver_platdata *ddata; @@ -1824,8 +1777,7 @@ static int cqspi_probe(struct platform_device *pdev) struct spi_controller *host; struct resource *res_ahb; struct cqspi_st *cqspi; - int ret; - int irq; + int ret, irq; =20 host =3D devm_spi_alloc_host(&pdev->dev, sizeof(*cqspi)); if (!host) @@ -1836,10 +1788,11 @@ static int cqspi_probe(struct platform_device *pdev) host->mem_caps =3D &cqspi_mem_caps; =20 cqspi =3D spi_controller_get_devdata(host); + if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) + cqspi->is_jh7110 =3D true; =20 cqspi->pdev =3D pdev; cqspi->host =3D host; - cqspi->is_jh7110 =3D false; cqspi->ddata =3D ddata =3D of_device_get_match_data(dev); platform_set_drvdata(pdev, cqspi); =20 @@ -1856,12 +1809,14 @@ static int cqspi_probe(struct platform_device *pdev) return ret; } =20 - /* Obtain QSPI clock. */ - cqspi->clk =3D devm_clk_get(dev, NULL); - if (IS_ERR(cqspi->clk)) { - dev_err(dev, "Cannot claim QSPI clock.\n"); - ret =3D PTR_ERR(cqspi->clk); - return ret; + /* Obtain QSPI clocks. */ + ret =3D devm_clk_bulk_get_optional(dev, CLK_QSPI_NUM, cqspi->clks); + if (ret) + return dev_err_probe(dev, ret, "Failed to get clocks\n"); + + if (!cqspi->clks[CLK_QSPI_REF].clk) { + dev_err(dev, "Cannot claim mandatory QSPI ref clock.\n"); + return -ENODEV; } =20 /* Obtain and remap controller address. */ @@ -1893,10 +1848,9 @@ static int cqspi_probe(struct platform_device *pdev) if (ret) return ret; =20 - - ret =3D clk_prepare_enable(cqspi->clk); + ret =3D clk_bulk_prepare_enable(CLK_QSPI_NUM, cqspi->clks); if (ret) { - dev_err(dev, "Cannot enable QSPI clock.\n"); + dev_err(dev, "Cannot enable QSPI clocks.\n"); goto disable_rpm; } =20 @@ -1905,22 +1859,22 @@ static int cqspi_probe(struct platform_device *pdev) if (IS_ERR(rstc)) { ret =3D PTR_ERR(rstc); dev_err(dev, "Cannot get QSPI reset.\n"); - goto disable_clk; + goto disable_clks; } =20 rstc_ocp =3D devm_reset_control_get_optional_exclusive(dev, "qspi-ocp"); if (IS_ERR(rstc_ocp)) { ret =3D PTR_ERR(rstc_ocp); dev_err(dev, "Cannot get QSPI OCP reset.\n"); - goto disable_clk; + goto disable_clks; } =20 - if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) { + if (cqspi->is_jh7110) { rstc_ref =3D devm_reset_control_get_optional_exclusive(dev, "rstc_ref"); if (IS_ERR(rstc_ref)) { ret =3D PTR_ERR(rstc_ref); dev_err(dev, "Cannot get QSPI REF reset.\n"); - goto disable_clk; + goto disable_clks; } reset_control_assert(rstc_ref); reset_control_deassert(rstc_ref); @@ -1932,7 +1886,7 @@ static int cqspi_probe(struct platform_device *pdev) reset_control_assert(rstc_ocp); reset_control_deassert(rstc_ocp); =20 - cqspi->master_ref_clk_hz =3D clk_get_rate(cqspi->clk); + cqspi->master_ref_clk_hz =3D clk_get_rate(cqspi->clks[CLK_QSPI_REF].clk); host->max_speed_hz =3D cqspi->master_ref_clk_hz; =20 /* write completion is supported by default */ @@ -1958,12 +1912,6 @@ static int cqspi_probe(struct platform_device *pdev) cqspi->slow_sram =3D true; if (ddata->quirks & CQSPI_NEEDS_APB_AHB_HAZARD_WAR) cqspi->apb_ahb_hazard =3D true; - - if (ddata->jh7110_clk_init) { - ret =3D cqspi_jh7110_clk_init(pdev, cqspi); - if (ret) - goto disable_clk; - } if (ddata->quirks & CQSPI_DISABLE_STIG_MODE) cqspi->disable_stig_mode =3D true; =20 @@ -2029,11 +1977,8 @@ static int cqspi_probe(struct platform_device *pdev) disable_controller: cqspi_controller_enable(cqspi, 0); disable_clks: - if (cqspi->is_jh7110) - cqspi_jh7110_disable_clk(pdev, cqspi); -disable_clk: if (pm_runtime_get_sync(&pdev->dev) >=3D 0) - clk_disable_unprepare(cqspi->clk); + clk_bulk_disable_unprepare(CLK_QSPI_NUM, cqspi->clks); disable_rpm: if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) pm_runtime_disable(dev); @@ -2062,14 +2007,12 @@ static void cqspi_remove(struct platform_device *pd= ev) =20 cqspi_controller_enable(cqspi, 0); =20 - if (cqspi->is_jh7110) - cqspi_jh7110_disable_clk(pdev, cqspi); =20 if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) ret =3D pm_runtime_get_sync(&pdev->dev); =20 if (ret >=3D 0) - clk_disable(cqspi->clk); + clk_bulk_disable_unprepare(CLK_QSPI_NUM, cqspi->clks); =20 if (!(ddata && (ddata->quirks & CQSPI_DISABLE_RUNTIME_PM))) { pm_runtime_put_sync(&pdev->dev); @@ -2082,15 +2025,19 @@ static int cqspi_runtime_suspend(struct device *dev) struct cqspi_st *cqspi =3D dev_get_drvdata(dev); =20 cqspi_controller_enable(cqspi, 0); - clk_disable_unprepare(cqspi->clk); + clk_bulk_disable_unprepare(CLK_QSPI_NUM, cqspi->clks); return 0; } =20 static int cqspi_runtime_resume(struct device *dev) { struct cqspi_st *cqspi =3D dev_get_drvdata(dev); + int ret; + + ret =3D clk_bulk_prepare_enable(CLK_QSPI_NUM, cqspi->clks); + if (ret) + return ret; =20 - clk_prepare_enable(cqspi->clk); cqspi_wait_idle(cqspi); cqspi_controller_enable(cqspi, 0); cqspi_controller_init(cqspi); @@ -2173,7 +2120,6 @@ static const struct cqspi_driver_platdata versal2_osp= i =3D { =20 static const struct cqspi_driver_platdata jh7110_qspi =3D { .quirks =3D CQSPI_DISABLE_DAC_MODE, - .jh7110_clk_init =3D cqspi_jh7110_clk_init, }; =20 static const struct cqspi_driver_platdata pensando_cdns_qspi =3D { --=20 2.51.1 From nobody Mon Feb 9 14:10:05 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E6743306D36; Thu, 5 Feb 2026 18:10:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770315020; cv=none; b=twEgPjCu+BNGDpqTfDDVuIE6fTSC/eo/K+j9ry3QmGPiuxIB1+xEZtWxj64z5YLNyC2HNepyHEafgcVYuTZCdMsFILWBAt5Dde8m2AvJgwHO92kwkiOE9ssJx1DQLtTTyR+ne58FMVTbr9Gvk9S9QS5KMNVvBmfVeK0UQqQz560= ARC-Message-Signature: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260205-schneider-6-19-rc1-qspi-v5-3-843632b3c674@bootlin.com> References: <20260205-schneider-6-19-rc1-qspi-v5-0-843632b3c674@bootlin.com> In-Reply-To: <20260205-schneider-6-19-rc1-qspi-v5-0-843632b3c674@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Vaishnav Achath Cc: Thomas Petazzoni , =?utf-8?q?Herv=C3=A9_Codina?= , Wolfram Sang , Vignesh Raghavendra , Santhosh Kumar K , Pratyush Yadav , Pascal Eberhard , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, "Miquel Raynal (Schneider Electric)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Renesas RZ/N1 QSPI controllers embed a modified version of the Cadence IP with the following settings: - a limited bus clock range - no DTR support - no DMA - no useful interrupt flag - only direct accesses (no INDAC mode) - write protection The controller has been tested by running the SPI NOR check list with a custom RZ/N1D400 based board mounted with a Spansion s25fl128s1 quad SPI. Tested-by: Wolfram Sang Signed-off-by: Miquel Raynal (Schneider Electric) --- Output of the SPI NOR test procedure: s25fl128s1 0120184d0180 spansion xxd: /sys/bus/spi/devices/spi0.0/spi-nor/sfdp: No such file or directory md5sum: can't open '/sys/bus/spi/devices/spi0.0/spi-nor/sfdp': No such file= or directory 1+0 records in 1+0 records out Copied 65536 bytes from qspi_test to address 0x00000000 in flash Erased 65536 bytes from address 0x00000000 in flash Copied 65536 bytes from address 0x00000000 in flash to qspi_read 0000000 ffff ffff ffff ffff ffff ffff ffff ffff * 0010000 Copied 65536 bytes from qspi_test to address 0x00000000 in flash Copied 65536 bytes from address 0x00000000 in flash to qspi_read 71f8b056a4bf5f51639a972dc9aac55eb8654fdc qspi_test 71f8b056a4bf5f51639a972dc9aac55eb8654fdc qspi_read Read speed: * page read speed is 6464 KiB/s * 2 page read speed is 9014 KiB/s * eraseblock read speed is 14222 KiB/s Write speed: * page write speed is 621 KiB/s * 2 page write speed is 626 KiB/s * eraseblock write speed is 633 KiB/s Erase speed: * erase speed is 617 KiB/s --- drivers/spi/spi-cadence-quadspi.c | 56 +++++++++++++++++++++++++++++------= ---- 1 file changed, 42 insertions(+), 14 deletions(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index f14a746cba2d..649ff55333f0 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -110,6 +110,7 @@ struct cqspi_st { bool apb_ahb_hazard; =20 bool is_jh7110; /* Flag for StarFive JH7110 SoC */ + bool is_rzn1; /* Flag for Renesas RZ/N1 SoC */ bool disable_stig_mode; refcount_t refcount; refcount_t inflight_ops; @@ -1337,8 +1338,9 @@ static ssize_t cqspi_write(struct cqspi_flash_pdata *= f_pdata, * mode. So, we can not use direct mode when in DTR mode for writing * data. */ - if (!op->cmd.dtr && cqspi->use_direct_mode && - cqspi->use_direct_mode_wr && ((to + len) <=3D cqspi->ahb_size)) { + if ((!op->cmd.dtr && cqspi->use_direct_mode && + cqspi->use_direct_mode_wr && ((to + len) <=3D cqspi->ahb_size)) || + (cqspi->ddata && cqspi->ddata->quirks & CQSPI_NO_INDIRECT_MODE)) { memcpy_toio(cqspi->ahb_base + to, buf, len); return cqspi_wait_idle(cqspi); } @@ -1512,6 +1514,7 @@ static int cqspi_exec_mem_op(struct spi_mem *mem, con= st struct spi_mem_op *op) static bool cqspi_supports_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) { + struct cqspi_st *cqspi =3D spi_controller_get_devdata(mem->spi->controlle= r); bool all_true, all_false; =20 /* @@ -1538,6 +1541,9 @@ static bool cqspi_supports_mem_op(struct spi_mem *mem, /* A single opcode is supported, it will be repeated */ if ((op->cmd.opcode >> 8) !=3D (op->cmd.opcode & 0xFF)) return false; + + if (cqspi->is_rzn1) + return false; } else if (!all_false) { /* Mixed DTR modes are not supported. */ return false; @@ -1591,18 +1597,20 @@ static int cqspi_of_get_pdata(struct cqspi_st *cqsp= i) =20 cqspi->is_decoded_cs =3D of_property_read_bool(np, "cdns,is-decoded-cs"); =20 - if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) { - /* Zero signals FIFO depth should be runtime detected. */ - cqspi->fifo_depth =3D 0; - } + if (!(cqspi->ddata && cqspi->ddata->quirks & CQSPI_NO_INDIRECT_MODE)) { + if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) { + /* Zero signals FIFO depth should be runtime detected. */ + cqspi->fifo_depth =3D 0; + } =20 - if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) - cqspi->fifo_width =3D 4; + if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) + cqspi->fifo_width =3D 4; =20 - if (of_property_read_u32(np, "cdns,trigger-address", - &cqspi->trigger_address)) { - dev_err(dev, "couldn't determine trigger-address\n"); - return -ENXIO; + if (of_property_read_u32(np, "cdns,trigger-address", + &cqspi->trigger_address)) { + dev_err(dev, "couldn't determine trigger-address\n"); + return -ENXIO; + } } =20 if (of_property_read_u32(np, "num-cs", &cqspi->num_chipselect)) @@ -1666,6 +1674,9 @@ static void cqspi_controller_detect_fifo_depth(struct= cqspi_st *cqspi) struct device *dev =3D &cqspi->pdev->dev; u32 reg, fifo_depth; =20 + if (cqspi->ddata && cqspi->ddata->quirks & CQSPI_NO_INDIRECT_MODE) + return; + /* * Bits N-1:0 are writable while bits 31:N are read as zero, with 2^N * the FIFO depth. @@ -1790,6 +1801,8 @@ static int cqspi_probe(struct platform_device *pdev) cqspi =3D spi_controller_get_devdata(host); if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) cqspi->is_jh7110 =3D true; + if (of_device_is_compatible(pdev->dev.of_node, "renesas,rzn1-qspi")) + cqspi->is_rzn1 =3D true; =20 cqspi->pdev =3D pdev; cqspi->host =3D host; @@ -1887,7 +1900,12 @@ static int cqspi_probe(struct platform_device *pdev) reset_control_deassert(rstc_ocp); =20 cqspi->master_ref_clk_hz =3D clk_get_rate(cqspi->clks[CLK_QSPI_REF].clk); - host->max_speed_hz =3D cqspi->master_ref_clk_hz; + if (!cqspi->is_rzn1) { + host->max_speed_hz =3D cqspi->master_ref_clk_hz; + } else { + host->max_speed_hz =3D cqspi->master_ref_clk_hz / 2; + host->min_speed_hz =3D cqspi->master_ref_clk_hz / 32; + } =20 /* write completion is supported by default */ cqspi->wr_completion =3D true; @@ -1952,7 +1970,7 @@ static int cqspi_probe(struct platform_device *pdev) if (ddata && (ddata->quirks & CQSPI_SUPPORT_DEVICE_RESET)) cqspi_device_reset(cqspi); =20 - if (cqspi->use_direct_mode) { + if (cqspi->use_direct_mode && !cqspi->is_rzn1) { ret =3D cqspi_request_mmap_dma(cqspi); if (ret =3D=3D -EPROBE_DEFER) { dev_err_probe(&pdev->dev, ret, "Failed to request mmap DMA\n"); @@ -2132,6 +2150,12 @@ static const struct cqspi_driver_platdata mobileye_e= yeq5_ospi =3D { CQSPI_RD_NO_IRQ, }; =20 +static const struct cqspi_driver_platdata renesas_rzn1_qspi =3D { + .hwcaps_mask =3D CQSPI_SUPPORTS_QUAD, + .quirks =3D CQSPI_NO_SUPPORT_WR_COMPLETION | CQSPI_RD_NO_IRQ | + CQSPI_HAS_WR_PROTECT | CQSPI_NO_INDIRECT_MODE, +}; + static const struct of_device_id cqspi_dt_ids[] =3D { { .compatible =3D "cdns,qspi-nor", @@ -2173,6 +2197,10 @@ static const struct of_device_id cqspi_dt_ids[] =3D { .compatible =3D "amd,versal2-ospi", .data =3D &versal2_ospi, }, + { + .compatible =3D "renesas,rzn1-qspi", + .data =3D &renesas_rzn1_qspi, + }, { /* end of table */ } }; =20 --=20 2.51.1 From nobody Mon Feb 9 14:10:05 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C241E3081A2; Thu, 5 Feb 2026 18:10:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770315024; cv=none; b=HKB2HhIweK82IX0ExeZH+pxtbyuHEysFxa2P6/psZpbrQ0Wk09A+Qd2kJfJQTCjwJGyvITo3imhG8Q958saHKZGyno5QrS04MZoeSIgrAapmeWtQ1T3dK1gQlkzKWC3w0Xejy/wf88tiYPqDAqY8KhCy6Mt5GjnSlq+7jXLmskE= ARC-Message-Signature: i=1; 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Thu, 5 Feb 2026 18:10:22 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 498466074D; Thu, 5 Feb 2026 18:10:22 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id CE2F5119D1708; Thu, 5 Feb 2026 19:10:17 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1770315020; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=WccFrzV37pjQDcMtab7f2QieezsSKecv42H/QrPd54o=; b=t+lxdw18M+1R7h+F5pljwNQw+inxi8Dm8uL8YZcM4mmOzXxVuuv7PMwwfY55sn3+5d/jtb IHzC+NNdEXkDXeU0GMU/N7M4yO2OEdidRYsyJnPum2yAnUuBDhCCWgoqL8bCii5WyLX1+N 40w5ziXD7v73gx9IqBuKRNcy/VRqxElzqdi/qso3nUJGf+mBaBPmrPiXEV9gV6EUQh+Ff9 C/j/7aAAHW/N62KNUrhIb7ySTrcXJMLON0lELzKCNv4+LhzAG92AwS2+K47u2snA18aiNn A6naD5E2BffC59m5jfUPQEhVLbhJtgQRyqeejK48je84Xk75V3D2ZXI1p7ojTw== From: "Miquel Raynal (Schneider Electric)" Date: Thu, 05 Feb 2026 19:09:51 +0100 Subject: [PATCH v5 4/4] ARM: dts: r9a06g032: Describe the QSPI controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260205-schneider-6-19-rc1-qspi-v5-4-843632b3c674@bootlin.com> References: <20260205-schneider-6-19-rc1-qspi-v5-0-843632b3c674@bootlin.com> In-Reply-To: <20260205-schneider-6-19-rc1-qspi-v5-0-843632b3c674@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Vaishnav Achath Cc: Thomas Petazzoni , =?utf-8?q?Herv=C3=A9_Codina?= , Wolfram Sang , Vignesh Raghavendra , Santhosh Kumar K , Pratyush Yadav , Pascal Eberhard , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, "Miquel Raynal (Schneider Electric)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 Add a node describing the QSPI controller. There are 2 clocks feeding this controller: - one for the reference clock - one that feeds both the ahb and the apb interfaces As the binding expect either the ref clock, or all three (ref, ahb and apb) clocks, it makes sense to provide the same clock twice. Reviewed-by: Geert Uytterhoeven Tested-by: Wolfram Sang Signed-off-by: Miquel Raynal (Schneider Electric) --- arch/arm/boot/dts/renesas/r9a06g032.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/renesas/r9a06g032.dtsi b/arch/arm/boot/dts/r= enesas/r9a06g032.dtsi index 8debb77803bb..47143e6636d2 100644 --- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi +++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi @@ -66,6 +66,18 @@ soc { #size-cells =3D <1>; ranges; =20 + qspi0: spi@40005000 { + compatible =3D "renesas,r9a06g032-qspi", "renesas,rzn1-qspi"; + reg =3D <0x40005000 0x1000>, <0x10000000 0x10000000>; + interrupts =3D ; + clocks =3D <&sysctrl R9A06G032_CLK_QSPI0>, <&sysctrl R9A06G032_HCLK_QSP= I0>, + <&sysctrl R9A06G032_HCLK_QSPI0>; + clock-names =3D "ref", "ahb", "apb"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + rtc0: rtc@40006000 { compatible =3D "renesas,r9a06g032-rtc", "renesas,rzn1-rtc"; reg =3D <0x40006000 0x1000>; --=20 2.51.1