From nobody Mon Feb 9 00:53:44 2026 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 30E6133506F; Thu, 5 Feb 2026 06:07:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770271662; cv=none; b=eoXNp3irbBs+MMNguIZM5036vFzBfS11PpJBRyz7KAaTiLI6NwcO15YKySXhaauNsPtHPEiEHnG4CXUACLmYsFznoY3Y553nF1MMn3nkZT/+wt1Be9tPe/DlZwKo/90uch3Ebu0n23t+8mTth5+FEbODFmG1+ZXK3QEBgCb+AR0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770271662; c=relaxed/simple; bh=94kybmSK3L5D9FwcDBryTTemjApRuHICkM61YUdO5vs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=WBw4gArtJqKUKNetg/0G7XIa041VL59Fh1fVkhJ65xK1phUEBWEAldS0Fl4iBCtMtOpSgZg0eB4PSpSTi6dz9Vz0+58CBJ9GK2LcYXvqMtf7Uqco0smm9NxMnenNLdE2wWtRQlGw8LDbBymUIfDtk/Ju9ako6ZSI/tMmFIAMZKQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 5 Feb 2026 14:07:30 +0800 Received: from [127.0.1.1] (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 5 Feb 2026 14:07:30 +0800 From: Ryan Chen Date: Thu, 5 Feb 2026 14:07:22 +0800 Subject: [PATCH 4/4] dt-bindings: interrupt-controller: aspeed: Remove legacy AST2700 interrupt binding Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260205-irqchip-v1-4-b0310e06c087@aspeedtech.com> References: <20260205-irqchip-v1-0-b0310e06c087@aspeedtech.com> In-Reply-To: <20260205-irqchip-v1-0-b0310e06c087@aspeedtech.com> To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , Paul Walmsley , Palmer Dabbelt , "Albert Ou" , Alexandre Ghiti CC: , , , , , Ryan Chen X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1770271649; l=4143; i=ryan_chen@aspeedtech.com; s=20251126; h=from:subject:message-id; bh=94kybmSK3L5D9FwcDBryTTemjApRuHICkM61YUdO5vs=; b=W0brkznpcQsf8wSaCgi65FA86/dT8/rbmt2Kul/YxEM7azEc3tuqfRQbbcJukMHzbV6QsMC9e SkcxUdArKffAJKnTsjEsFA3BtWotZjQjgtH2mmdDNTtaW7iPEV8rUzN X-Developer-Key: i=ryan_chen@aspeedtech.com; a=ed25519; pk=Xe73xY6tcnkuRjjbVAB/oU30KdB3FvG4nuJuILj7ZVc= Remove the legacy AST2700 interrupt controller Devicetree binding. The legacy binding was limited to a PSP-centric view of the interrupt architecture and cannot describe interrupt routing and protection for the full AST2700 system. It is superseded by the new ASPEED AST2700 INTC0/INTC1 binding, which describes the interrupt controllers at the block-function level. There are no known upstream users of the removed binding. Signed-off-by: Ryan Chen --- .../interrupt-controller/aspeed,ast2700-intc.yaml | 90 ------------------= ---- 1 file changed, 90 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,= ast2700-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/= aspeed,ast2700-intc.yaml deleted file mode 100644 index 258d21fe6e35..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700= -intc.yaml +++ /dev/null @@ -1,90 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-int= c.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Aspeed AST2700 Interrupt Controller - -description: - This interrupt controller hardware is second level interrupt controller = that - is hooked to a parent interrupt controller. It's useful to combine multi= ple - interrupt sources into 1 interrupt to parent interrupt controller. - -maintainers: - - Kevin Chen - -properties: - compatible: - enum: - - aspeed,ast2700-intc-ic - - reg: - maxItems: 1 - - interrupt-controller: true - - '#interrupt-cells': - const: 1 - description: - The first cell is the IRQ number, the second cell is the trigger - type as defined in interrupt.txt in this directory. - - interrupts: - minItems: 1 - maxItems: 10 - description: | - Depend to which INTC0 or INTC1 used. - INTC0 and INTC1 are two kinds of interrupt controller with enable an= d raw - status registers for use. - INTC0 is used to assert GIC if interrupt in INTC1 asserted. - INTC1 is used to assert INTC0 if interrupt of modules asserted. - +-----+ +-------+ +---------+---module0 - | GIC |---| INTC0 |--+--| INTC1_0 |---module2 - | | | | | | |---... - +-----+ +-------+ | +---------+---module31 - | - | +---------+---module0 - +---| INTC1_1 |---module2 - | | |---... - | +---------+---module31 - ... - | +---------+---module0 - +---| INTC1_5 |---module2 - | |---... - +---------+---module31 - -required: - - compatible - - reg - - interrupt-controller - - '#interrupt-cells' - - interrupts - -additionalProperties: false - -examples: - - | - #include - - bus { - #address-cells =3D <2>; - #size-cells =3D <2>; - - interrupt-controller@12101b00 { - compatible =3D "aspeed,ast2700-intc-ic"; - reg =3D <0 0x12101b00 0 0x10>; - #interrupt-cells =3D <1>; - interrupt-controller; - interrupts =3D , - , - , - , - , - , - , - , - , - ; - }; - }; --=20 2.34.1