From nobody Sun Feb 8 22:06:13 2026 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A33E9334695; Thu, 5 Feb 2026 06:07:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770271660; cv=none; b=iEsS4hbf/6Ufxc1uKz+57NPO82eqaoHU+2xEEGDmVAfAgkRyooG9h+vHZG8/xj5RQQdy5DVVAzL79S/pERIU/9ebjJebK7b7fvMudwhtA42fn/632c+jA3wnUSWY7ye1MDVvg3NkldWXTPUwo/YANbJ0E5YJiCJaQIG7tWpE8rs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770271660; c=relaxed/simple; bh=0fuUkS4W8giyVzoGhPYy+wRAWNG8NtfTogigJsfUK9c=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=G/Mo1D/BG+n0bWbfe1W7WlOI/uZ/Aq3+D6/4IC/0yGaJ+Hf4sBefKyhbqRpK1tfvdm3IbWvUsRwhYjcsplgyo7mhaX46xWQE1UmeTMV29Y1W9B4CjFodzg85IkcJ0LalFO0mO4wFQ2hTdfjLR9xbb0dGyyTv6xayrL4K7jdAh8k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 5 Feb 2026 14:07:30 +0800 Received: from [127.0.1.1] (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 5 Feb 2026 14:07:30 +0800 From: Ryan Chen Date: Thu, 5 Feb 2026 14:07:19 +0800 Subject: [PATCH 1/4] dt-bindings: interrupt-controller: aspeed: Add ASPEED AST2700 INTC0/INTC1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260205-irqchip-v1-1-b0310e06c087@aspeedtech.com> References: <20260205-irqchip-v1-0-b0310e06c087@aspeedtech.com> In-Reply-To: <20260205-irqchip-v1-0-b0310e06c087@aspeedtech.com> To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , Paul Walmsley , Palmer Dabbelt , "Albert Ou" , Alexandre Ghiti CC: , , , , , Ryan Chen X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1770271649; l=8810; i=ryan_chen@aspeedtech.com; s=20251126; h=from:subject:message-id; bh=0fuUkS4W8giyVzoGhPYy+wRAWNG8NtfTogigJsfUK9c=; b=3IwrnqYWYgIrMWXMHNIWcw656dwRDf0J5V3NaL1guqyVO7NWgFMdeAqEnTcbhy5nNjxwyLEPM bqGGDrDj1qIAp/Ql18MaWlvlo351E46K+ELVATkc/0jJyCZYQpaS6wM X-Developer-Key: i=ryan_chen@aspeedtech.com; a=ed25519; pk=Xe73xY6tcnkuRjjbVAB/oU30KdB3FvG4nuJuILj7ZVc= INTC0 is used to assert GIC if interrupt in INTC1 asserted. INTC1 is used to assert INTC0 if interrupt of modules asserted. Signed-off-by: Ryan Chen --- .../aspeed,ast2700-interrupt.yaml | 207 +++++++++++++++++= ++++ 1 file changed, 207 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,= ast2700-interrupt.yaml b/Documentation/devicetree/bindings/interrupt-contro= ller/aspeed,ast2700-interrupt.yaml new file mode 100644 index 000000000000..8a27e1e667a1 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700= -interrupt.yaml @@ -0,0 +1,207 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-int= errupt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ASPEED AST2700 Interrupt Controllers (INTC0/INTC1) + +description: | + The ASPEED AST2700 SoC integrates two interrupt controller designs: + + - INTC0: Primary controller that routes interrupt sources to upstream, + processor-specific interrupt controllers + + - INTC1: Secondary controller whose interrupt outputs feed into + INTC0 + + The SoC contains four processors to which interrupts can be routed: + + - PSP: Primary Service Processor (Cortex-A35) + - SSP: Secondary Service Processor (Cortex-M4) + - TSP: Tertiary Sevice Processor (Cortex-M4) + - BMCU: Boot MCU (a RISC-V microcontroller) + + The following diagram illustrates the overall architecture of the + ASPEED AST2700 interrupt controllers: + + +-----------+ +-----------+ + | INTC0 | | INTC1(0)| + +-----------+ +-----------+ + | Router | +-------+ | Router | + | out int | + SOC0 + | out int | + +-----------+ | 0 0 <---+ INTx + | INTM | +-------+ + |PSP GIC <-|---+ . . | +Modules+ | . . <-----+ SOC1 + + +-----------+ | . . | +-------+ | . . | + INTx + + +-----------+ | . . | | . . | +Modules+ + |SSP NVIC <-|---+ . . <----------------+ . . | +-------+ + +-----------+ | . . | | . . | + +-----------+ | . . <-------- | . . | + |TSP NVIC <-|---+ . . | | ----+ . . | + +-----------+ | . . | | | | O P | + | . . | | | +-----------+ + | . . <---- | -------------------- + | . . | | | +-----------+ | + | M N | | ---------+ INTC1(1) | | + +-----------+ | +-----------+ | + | . | + | +-----------+ | + -------------+ INTC1(N) | | + +-----------+ | + +--------------+ | + + BMCU APLIC <-+--------------------------------------------- + +--------------+ + + INTC0 supports: + - 128 local peripheral interrupt inputs + - Fan-in from up to three INTC1 instances via banked interrupt lines (= INTM) + - Local peripheral interrupt outputs + - Merged interrupt outputs + - Software interrupt outputs (SWINT) + - Configurable interrupt routes targeting the PSP, SSP, and TSP + + INTC1 supports: + - 192 local peripheral interrupt inputs + - Banked interrupt outputs (INTM, 5 x 6 banks x 32 interrupts per bank) + - Configurable interrupt routes targeting the PSP, SSP, TSP, and BMCU + + One INTC1 instance is always present, on the SoC's IO die. A further two + instances may be attached to the SoC's one INTC0 instance via LTPI (LVDS + Tunneling Protocol & Interface). + + Interrupt numbering model + ------------------------- + The binding uses a controller-local numbering model. Peripheral device + nodes use the INTCx local interrupt number (hwirq) in their 'interrupts'= or + 'interrupts-extended' properties. + + For AST2700, INTC0 exposes the following (inclusive) input ranges: + + - 000..479: Independent interrupts + - 480..489: INTM0-INTM9 + - 490..499: INTM10-INTM19 + - 500..509: INTM20-INTM29 + - 510..519: INTM30-INTM39 + - 520..529: INTM40-INTM49 + + INTC0's (inclusive) output ranges are as follows: + + - 000..127: 1:1 local peripheral interrupt output to PSP + - 144..151: Software interrupts from the SSP output to PSP + - 152..159: Software interrupts from the TSP output to PSP + - 192..201: INTM0-INTM9 banked outputs to PSP + - 208..217: INTM30-INTM39 banked outputs to PSP + - 224..233: INTM40-INTM49 banked outputs to PSP + - 256..383: 1:1 local peripheral interrupt output to SSP + - 384..393: INTM10-INTM19 banked outputs to SSP + - 400..407: Software interrupts from the PSP output to SSP + - 408..415: Software interrupts from the TSP output to SSP + - 426..553: 1:1 local peripheral interrupt output to TSP + - 554..563: INTM20-INTM29 banked outputs to TSP + - 570..577: Software interrupts from the PSP output to TSP + - 578..585: Software interrupts from the SSP output to TSP + + Inputs and outputs for INTC1 instances are context-dependent. However, f= or the + first instance of INTC1, the (inclusive) output ranges are: + + - 00..05: INTM0-INTM5 + - 10..15: INTM10-INTM15 + - 20..25: INTM20-INTM25 + - 30..35: INTM30-INTM35 + - 40..45: INTM40-INTM45 + - 50..50: BootMCU + +maintainers: + - ryan_chen@aspeedtech.com + - andrew@codeconstruct.com.au + +properties: + compatible: + enum: + - aspeed,ast2700-intc0 + - aspeed,ast2700-intc1 + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + description: | + Single cell encoding the INTC local interrupt number (hwirq). + + aspeed,interrupt-ranges: + description: | + Describes how ranges of controller output pins are routed to a parent + interrupt controller. + + Each range entry is encoded as: + + + + where: + - out: First controller interrupt output index in the range. + - count: Number of consecutive controller interrupt outputs and = parent + interrupt inputs in this range. + - phandle: Phandle to the parent interrupt controller node. + - parent-specifier: Interrupt specifier, as defined by the parent + interrupt controller binding. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 3 + items: + description: Range descriptors with a parent interrupt specifier. + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + - aspeed,interrupt-ranges + +additionalProperties: false + +examples: + - | + #include + + intc0: interrupt-controller@12100000 { + compatible =3D "aspeed,ast2700-intc0-ic"; + reg =3D <0x12100000 0x3b00>; + interrupt-parent =3D <&gic>; + interrupt-controller; + #interrupt-cells =3D <1>; + + aspeed,interrupt-ranges =3D + <0 128 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <144 8 &gic GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <152 8 &gic GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, + <192 10 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, + <208 10 &gic GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, + <224 10 &gic GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, + <256 128 &ssp_nvic 0 0 >, + <384 10 &ssp_nvic 160 0 >, + <400 8 &ssp_nvic 144 0 >, + <408 8 &ssp_nvic 152 0 >, + <426 128 &tsp_nvic 0 0 >, + <554 10 &tsp_nvic 160 0 >, + <570 8 &tsp_nvic 144 0 >, + <578 8 &tsp_nvic 152 0 >; + }; + + - | + intc1: interrupt-controller@14c18000 { + compatible =3D "aspeed,ast2700-intc1-ic"; + reg =3D <0x14c18000 0x400>; + interrupt-parent =3D <&intc0>; + interrupt-controller; + #interrupt-cells =3D <1>; + + aspeed,interrupt-ranges =3D + <0 6 &intc0 480>, + <10 6 &intc0 490>, + <20 6 &intc0 500>, + <30 6 &intc0 510>, + <40 6 &intc0 520>, + <50 1 &bootmcu_plic 0>; + }; --=20 2.34.1