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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id af79cd13be357-8ca2fd2c3easm353674885a.32.2026.02.05.01.21.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Feb 2026 01:21:09 -0800 (PST) From: Yongxing Mou Date: Thu, 05 Feb 2026 17:20:54 +0800 Subject: [PATCH 2/3] phy: qcom: edp: Add per-version LDO configuration callback Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260205-edp_phy-v1-2-231882bbf3f1@oss.qualcomm.com> References: <20260205-edp_phy-v1-0-231882bbf3f1@oss.qualcomm.com> In-Reply-To: <20260205-edp_phy-v1-0-231882bbf3f1@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, Yongxing Mou X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1770283262; l=5992; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=dhNtEciXmxe7JOgKKpPwPoFS/KpvqGImKVUMYUBSVDI=; b=t1Qg1qmlB/s5FnDaWUtxt2AvlSg9gQrY/zes/o6FLTiWxnP36YjgHcJP8hsZj7dpX2xzVuEth 32vuizWSdgMBLFRFsK92V5YcVT8hSwu5GfW3Zp+nm6hJOEP9jgjT/08 X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjA1MDA2NyBTYWx0ZWRfX3FPtK52YJ6YK 7J0JueUW3ndp428RgZTAMfM5SiXz961BcU+Pul5g5MCAC+LcZR+RN8g1lA2oipP9yfqeYIzjT3s XO3IGaexLDlz1cRo60dOpURThXj+w5MhMevQysp3sisN/CxS7DEQIT70dhYvx5o4prnllA2nUW9 h/i4uoFvqlpOzOiopEJAA3r+/BvSiNegfBPsRXn1WBHc58DqYRGz3KJZODnLplA2LCfzH/qW2Ca dvP3v4+slTxFleW6sXotkN8xFgnTSQ602PhWJVdmqKyIYQi86h2SUm45qW0+VxZ03xYXsLOPMrb jibaxMawrHyBs+k4XgjK3tuGDW5DqTX0BFu/XBkunuVYI9PnzFO0/+yPBFI3DhY6ZZfh/i+HYbE VKG3em8Y6ux5RBUlbyMpezteMgJN6LQ0x4Fjt3kOvpV7cZiGFtN/7GNArvuTBYtzZps/+WLJWkj 3iRjS3f+7sYUs/GGh8g== X-Proofpoint-ORIG-GUID: jbHmHgEIYeTEgAgTYHdYWEWgjr0UYe1Z X-Authority-Analysis: v=2.4 cv=UoBu9uwB c=1 sm=1 tr=0 ts=69846107 cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=7aH6mENmw-U4l7sLY48A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 X-Proofpoint-GUID: jbHmHgEIYeTEgAgTYHdYWEWgjr0UYe1Z X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-05_01,2026-02-05_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 suspectscore=0 bulkscore=0 adultscore=0 malwarescore=0 spamscore=0 lowpriorityscore=0 impostorscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602050067 Introduce the com_ldo_config callback to support per=E2=80=91PHY LDO configuration. Signed-off-by: Yongxing Mou --- drivers/phy/qualcomm/phy-qcom-edp.c | 86 ++++++++++++++++++++++++++++++++-= ---- 1 file changed, 76 insertions(+), 10 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy= -qcom-edp.c index 10cbb7d9a8a0..388226dbad7f 100644 --- a/drivers/phy/qualcomm/phy-qcom-edp.c +++ b/drivers/phy/qualcomm/phy-qcom-edp.c @@ -81,6 +81,7 @@ struct phy_ver_ops { int (*com_clk_fwd_cfg)(const struct qcom_edp *edp); int (*com_configure_pll)(const struct qcom_edp *edp); int (*com_configure_ssc)(const struct qcom_edp *edp); + int (*com_ldo_config)(const struct qcom_edp *edp); }; =20 struct qcom_edp_phy_cfg { @@ -273,7 +274,7 @@ static int qcom_edp_set_voltages(struct qcom_edp *edp, = const struct phy_configur const struct qcom_edp_swing_pre_emph_cfg *cfg =3D edp->cfg->swing_pre_emp= h_cfg; unsigned int v_level =3D 0; unsigned int p_level =3D 0; - u8 ldo_config; + int ret; u8 swing; u8 emph; int i; @@ -300,13 +301,13 @@ static int qcom_edp_set_voltages(struct qcom_edp *edp= , const struct phy_configur if (swing =3D=3D 0xff || emph =3D=3D 0xff) return -EINVAL; =20 - ldo_config =3D edp->is_edp ? 0x0 : 0x1; + ret =3D edp->cfg->ver_ops->com_ldo_config(edp); + if (ret) + return ret; =20 - writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG); writel(swing, edp->tx0 + TXn_TX_DRV_LVL); writel(emph, edp->tx0 + TXn_TX_EMP_POST1_LVL); =20 - writel(ldo_config, edp->tx1 + TXn_LDO_CONFIG); writel(swing, edp->tx1 + TXn_TX_DRV_LVL); writel(emph, edp->tx1 + TXn_TX_EMP_POST1_LVL); =20 @@ -530,6 +531,52 @@ static int qcom_edp_com_configure_pll_v4(const struct = qcom_edp *edp) return 0; } =20 +static int qcom_edp_ldo_config_v3(const struct qcom_edp *edp) +{ + const struct phy_configure_opts_dp *dp_opts =3D &edp->dp_opts; + u32 ldo_config; + + if (!edp->is_edp) + ldo_config =3D 0x0; + else if (dp_opts->link_rate <=3D 2700) + ldo_config =3D 0x81; + else + ldo_config =3D 0x41; + + writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG); + writel(ldo_config, edp->tx1 + TXn_LDO_CONFIG); + + return 0; +} + +static int qcom_edp_ldo_config_v4(const struct qcom_edp *edp) +{ + const struct phy_configure_opts_dp *dp_opts =3D &edp->dp_opts; + u32 ldo_config; + + if (!edp->is_edp) + ldo_config =3D 0x0; + else if (dp_opts->link_rate <=3D 2700) + ldo_config =3D 0xC1; + else + ldo_config =3D 0x81; + + writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG); + writel(ldo_config, edp->tx1 + TXn_LDO_CONFIG); + + return 0; +} + +static const struct phy_ver_ops qcom_edp_phy_ops_v3 =3D { + .com_power_on =3D qcom_edp_phy_power_on_v4, + .com_resetsm_cntrl =3D qcom_edp_phy_com_resetsm_cntrl_v4, + .com_bias_en_clkbuflr =3D qcom_edp_com_bias_en_clkbuflr_v4, + .com_clk_fwd_cfg =3D qcom_edp_com_clk_fwd_cfg_v4, + .com_configure_pll =3D qcom_edp_com_configure_pll_v4, + .com_configure_ssc =3D qcom_edp_com_configure_ssc_v4, + .com_ldo_config =3D qcom_edp_ldo_config_v3, +}; + static const struct phy_ver_ops qcom_edp_phy_ops_v4 =3D { .com_power_on =3D qcom_edp_phy_power_on_v4, .com_resetsm_cntrl =3D qcom_edp_phy_com_resetsm_cntrl_v4, @@ -537,6 +584,7 @@ static const struct phy_ver_ops qcom_edp_phy_ops_v4 =3D= { .com_clk_fwd_cfg =3D qcom_edp_com_clk_fwd_cfg_v4, .com_configure_pll =3D qcom_edp_com_configure_pll_v4, .com_configure_ssc =3D qcom_edp_com_configure_ssc_v4, + .com_ldo_config =3D qcom_edp_ldo_config_v4, }; =20 static const struct qcom_edp_phy_cfg sa8775p_dp_phy_cfg =3D { @@ -550,7 +598,7 @@ static const struct qcom_edp_phy_cfg sa8775p_dp_phy_cfg= =3D { static const struct qcom_edp_phy_cfg sc7280_dp_phy_cfg =3D { .aux_cfg =3D edp_phy_aux_cfg_v4, .vco_div_cfg =3D edp_phy_vco_div_cfg_v4, - .ver_ops =3D &qcom_edp_phy_ops_v4, + .ver_ops =3D &qcom_edp_phy_ops_v3, }; =20 static const struct qcom_edp_phy_cfg sc8280xp_dp_phy_cfg =3D { @@ -733,12 +781,31 @@ static int qcom_edp_com_configure_pll_v6(const struct= qcom_edp *edp) return 0; } =20 +static int qcom_edp_ldo_config_v6(const struct qcom_edp *edp) +{ + const struct phy_configure_opts_dp *dp_opts =3D &edp->dp_opts; + u32 ldo_config; + + if (!edp->is_edp) + ldo_config =3D 0x0; + else if (dp_opts->link_rate <=3D 2700) + ldo_config =3D 0x51; + else + ldo_config =3D 0x91; + + writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG); + writel(ldo_config, edp->tx1 + TXn_LDO_CONFIG); + + return 0; +} + static const struct phy_ver_ops qcom_edp_phy_ops_v6 =3D { .com_power_on =3D qcom_edp_phy_power_on_v6, .com_resetsm_cntrl =3D qcom_edp_phy_com_resetsm_cntrl_v6, .com_bias_en_clkbuflr =3D qcom_edp_com_bias_en_clkbuflr_v6, .com_configure_pll =3D qcom_edp_com_configure_pll_v6, .com_configure_ssc =3D qcom_edp_com_configure_ssc_v6, + .com_ldo_config =3D qcom_edp_ldo_config_v6, }; =20 static struct qcom_edp_phy_cfg x1e80100_phy_cfg =3D { @@ -918,6 +985,7 @@ static const struct phy_ver_ops qcom_edp_phy_ops_v8 =3D= { .com_clk_fwd_cfg =3D qcom_edp_com_clk_fwd_cfg_v8, .com_configure_pll =3D qcom_edp_com_configure_pll_v8, .com_configure_ssc =3D qcom_edp_com_configure_ssc_v8, + .com_ldo_config =3D qcom_edp_ldo_config_v6, }; =20 static struct qcom_edp_phy_cfg glymur_phy_cfg =3D { @@ -932,7 +1000,6 @@ static int qcom_edp_phy_power_on(struct phy *phy) const struct qcom_edp *edp =3D phy_get_drvdata(phy); u32 bias0_en, drvr0_en, bias1_en, drvr1_en; unsigned long pixel_freq; - u8 ldo_config =3D 0x0; int ret; u32 val; u8 cfg1; @@ -941,11 +1008,10 @@ static int qcom_edp_phy_power_on(struct phy *phy) if (ret) return ret; =20 - if (edp->cfg->swing_pre_emph_cfg && !edp->is_edp) - ldo_config =3D 0x1; + ret =3D edp->cfg->ver_ops->com_ldo_config(edp); + if (ret) + return ret; =20 - writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG); - writel(ldo_config, edp->tx1 + TXn_LDO_CONFIG); writel(0x00, edp->tx0 + TXn_LANE_MODE_1); writel(0x00, edp->tx1 + TXn_LANE_MODE_1); =20 --=20 2.43.0