From nobody Mon Feb 9 18:21:47 2026 Received: from mail-ed1-f44.google.com (mail-ed1-f44.google.com [209.85.208.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 94783329E4E for ; Thu, 5 Feb 2026 22:02:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770328921; cv=none; b=fTRkuOEaVdCyLKUBsVcniZc6HPcRGZq9k10PwfI6s0B4nKCoXZmBGuZA6vVS6U1Zg63ejTTc46IBt/Xw+IuEfPA8QIXI3OhqeTKieJRW+MriNWH56n454mp3yxarZItSWb0Y7DqRef71VpUhFUI0TS6MfV7XprK4UDLjvJhQFLI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770328921; c=relaxed/simple; bh=U05JLftmyJnHY2XoTQa/nqqqQ5++HU8ZHdqPgaBReWs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:To:Cc; b=IMgGHqWrORFXYMPsEuPsTc+NbN1zAfTEyNCucBmfJzwemz7oHJLDEA4ZyQTCxDGSbjnGiOlyNHO9MCaYaH5sdsYRb96H8yJnjlGf9JBfEmGizqWugnVNCWxMY9Tn9DTsLfoZOmTfKlpa2Bipib6K5YxEejICD4YOvGOYQJ3UpbY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=Y2ZWOG9w; arc=none smtp.client-ip=209.85.208.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="Y2ZWOG9w" Received: by mail-ed1-f44.google.com with SMTP id 4fb4d7f45d1cf-6581327d6baso2439637a12.3 for ; Thu, 05 Feb 2026 14:02:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1770328919; x=1770933719; darn=vger.kernel.org; h=cc:to:message-id:content-transfer-encoding:mime-version:subject :date:from:from:to:cc:subject:date:message-id:reply-to; bh=DSe1MS03T8BW9ZubjvfneKpDOJEdsi+I8lH8q1oaCb4=; b=Y2ZWOG9wzo4xToeA9qHRyVHAIUjfEIyW7drWjryIS9pVCtcr+5oPsm+rsvQI5gJZD3 vCMF+fVckwt+OG2jzDms7CwJzliuxlfK2bIQ7POeDZnZCLUaOs2Cl5bxTDCvxvaA8Bj9 vEuiUSIxnhZ7tnKKD6wwygVpZx4EDTDIhgY9LZVog8FxmGWYgQB+hzvM0DOgKR7X/v/C q+SZtwx29cbYJtH/Apeunm6hJRuwr1kFlC5eyKtp9+3VZqs0l+EYyYbWYAJ1qLa3AP3E +zK3QCZczVLYBxEyQgMFDTLjCJmQALxE/kdZzU+F3qmiNEToGlP+G7pX37oXdeHZLJGW whVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770328919; x=1770933719; h=cc:to:message-id:content-transfer-encoding:mime-version:subject :date:from:x-gm-gg:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=DSe1MS03T8BW9ZubjvfneKpDOJEdsi+I8lH8q1oaCb4=; b=DEVLNuux08J87gAlDuutBTKObGCcO0DBu2AtHYh+tcjHC99nVE1p54shFkbZejeta4 nK+CDK5qc744YYzpfdiQQDjXuHjKxIpIvEGTV5yUw4kjNIGfiLEMN+bjc4XZBDxYf7d+ Rg5Yk0BRSaKU1IokHRw8CbBYr8s0piSSL7VZzRq1xkS1L9eRkfMrDy5v+ruG5rC+KdCO DSzTBlZglNKcDfLR/Fjr2ZmdQ5TQWVWvCT+RqnoFFlq2VzkgBFWAWGzgbmoBA9wj6H3i zbsXYlHPn8HvPKI3Yq8RlB4V/+FX+9FUKCTtilpEOmuimkg468kh6M5ueLGo3Jv+4gtS vRAQ== X-Forwarded-Encrypted: i=1; AJvYcCU5Ohvmhr5mOL2UBVsU21A7cbZszsRD1xPc5lzKkfSpLp68E35BULed+TspUlTPesl0aF2U/db2+wKZ+v8=@vger.kernel.org X-Gm-Message-State: AOJu0Yy0hQyoKrihPXtC14uCrQ5jkoVBoN1WYspoymoipOK+xOiChbRJ uF/bkUqGeWrxNLT9iRO08b7751E6mYBzxzZ/UPjgewUGn35qTAPMe/3mYjVV+IZCzkWFDXK4zPW NVgvuFQ4= X-Gm-Gg: AZuq6aLDz5PYBqYHwAvaWRRT8nkPJq0lIaSP2xkfwW0fXC3rDMzWm/9I/XCfjKwaGCW 4h/srGGGWgTqkbdTavqJvWK0ZlrGlgbdZTeJAWo2hNNLJtUB2OmedPks6Lvs2x+F947YU3zWw07 WLsyJrOlMEQAu5goxgBlF5bmCdMF/obW4gc7e71fU+6oKb93UWYDbqjMPKfaIyJW1Xr5rC9Yb12 x3+hEj1EjA9wm/ILD/G60lr7tItnVaV6gfx9wWwiFpwrwIAQeDzkNUs2HfDVBFXngUfxcf4tKpe xH9TbXo2EX1eD8qJPlYoNoj2Kz1S+V0dY0YpMsMFSuBoju9rfyjqQIDe2duBMww3bOBTAm8Se/t WB/p+G4IqG1WhN9mFVu3e9K9wrPtjs9DoxREtkCGnfuC4r24hG9LE4AwUeJIFfKy29xnnbchzTv pXl4fxqduf0u+UPuC9ESnd9vMS01/ulz2H1oV5XSsX0KEaiZLzUayBw57sQxf1indh78ac31Q69 LRWFQ== X-Received: by 2002:a17:907:6d1e:b0:b8e:12f9:5fce with SMTP id a640c23a62f3a-b8edf4636b0mr25927466b.61.1770328918709; Thu, 05 Feb 2026 14:01:58 -0800 (PST) Received: from puffmais2.c.googlers.com (244.175.141.34.bc.googleusercontent.com. [34.141.175.244]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8eda748963sm22893366b.12.2026.02.05.14.01.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Feb 2026 14:01:58 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Thu, 05 Feb 2026 22:01:57 +0000 Subject: [PATCH] clk: samsung: gs101: harmonise symbol names (clock arrays) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260205-clk-gs101-symbol-names-v1-1-a7d9a7a4d108@linaro.org> X-B4-Tracking: v=1; b=H4sIAFQThWkC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyDHUUlJIzE vPSU3UzU4B8JSMDIzMDQyNj3eScbN30YkMDQ93iytyk/BzdvMTc1GJdA3NzEwsLC9Pk5MQkJaD mgqLUtMwKsMHRsbW1ALdxm+xoAAAA X-Change-ID: 20260123-clk-gs101-symbol-names-07748885ccab To: Peter Griffin , Tudor Ambarus , Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd Cc: Juan Yescas , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.14.2 Most symbols for the clock descriptions (arrays) don't have a cmu_ prefix and all symbols have a _clks suffix where appropriate. Update the few outliers to also fall into this same scheme for consistency. Signed-off-by: Andr=C3=A9 Draszik --- drivers/clk/samsung/clk-gs101.c | 52 ++++++++++++++++++++-----------------= ---- 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs10= 1.c index 44a8ecd332fddce7d4e162219528462ce3c8c03f..d2bcd3a9daf8939157640c4e7a0= 0da3d39ac309e 100644 --- a/drivers/clk/samsung/clk-gs101.c +++ b/drivers/clk/samsung/clk-gs101.c @@ -339,7 +339,7 @@ #define GENERALIO_ACD_CHANNEL_3 0x3f0c #define GENERALIO_ACD_MASK 0x3f14 =20 -static const unsigned long cmu_top_clk_regs[] __initconst =3D { +static const unsigned long top_clk_regs[] __initconst =3D { PLL_LOCKTIME_PLL_SHARED0, PLL_LOCKTIME_PLL_SHARED1, PLL_LOCKTIME_PLL_SHARED2, @@ -638,7 +638,7 @@ static const unsigned long cmu_top_clk_regs[] __initcon= st =3D { GENERALIO_ACD_MASK, }; =20 -static const struct samsung_pll_clock cmu_top_pll_clks[] __initconst =3D { +static const struct samsung_pll_clock top_pll_clks[] __initconst =3D { /* CMU_TOP_PURECLKCOMP */ PLL(pll_0517x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk", PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, @@ -952,7 +952,7 @@ PNAME(mout_cmu_cmuref_p) =3D { "mout_cmu_top_boost_opti= on1", * For gates remove _UID _BLK _IPCLKPORT and _RSTNSYNC */ =20 -static const struct samsung_mux_clock cmu_top_mux_clks[] __initconst =3D { +static const struct samsung_mux_clock top_mux_clks[] __initconst =3D { MUX(CLK_MOUT_PLL_SHARED0, "mout_pll_shared0", mout_pll_shared0_p, PLL_CON0_PLL_SHARED0, 4, 1), MUX(CLK_MOUT_PLL_SHARED1, "mout_pll_shared1", mout_pll_shared1_p, @@ -1108,7 +1108,7 @@ static const struct samsung_mux_clock cmu_top_mux_clk= s[] __initconst =3D { CLK_CON_MUX_MUX_CMU_CMUREF, 0, 1), }; =20 -static const struct samsung_div_clock cmu_top_div_clks[] __initconst =3D { +static const struct samsung_div_clock top_div_clks[] __initconst =3D { DIV(CLK_DOUT_CMU_BO_BUS, "dout_cmu_bo_bus", "gout_cmu_bo_bus", CLK_CON_DIV_CLKCMU_BO_BUS, 0, 4), DIV(CLK_DOUT_CMU_BUS0_BUS, "dout_cmu_bus0_bus", "gout_cmu_bus0_bus", @@ -1253,13 +1253,13 @@ static const struct samsung_div_clock cmu_top_div_c= lks[] __initconst =3D { "mout_pll_shared3", CLK_CON_DIV_PLL_SHARED3_DIV2, 0, 1), }; =20 -static const struct samsung_fixed_factor_clock cmu_top_ffactor[] __initcon= st =3D { +static const struct samsung_fixed_factor_clock top_ffactor_clks[] __initco= nst =3D { FFACTOR(CLK_DOUT_CMU_HSI0_USBDPDBG, "dout_cmu_hsi0_usbdpdbg", "gout_cmu_hsi0_usbdpdbg", 1, 4, 0), FFACTOR(CLK_DOUT_CMU_OTP, "dout_cmu_otp", "oscclk", 1, 8, 0), }; =20 -static const struct samsung_gate_clock cmu_top_gate_clks[] __initconst =3D= { +static const struct samsung_gate_clock top_gate_clks[] __initconst =3D { GATE(CLK_GOUT_CMU_BUS0_BOOST, "gout_cmu_bus0_boost", "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_BUS0_BOOST, 21, 0, 0), GATE(CLK_GOUT_CMU_BUS1_BOOST, "gout_cmu_bus1_boost", @@ -1425,19 +1425,19 @@ static const struct samsung_gate_clock cmu_top_gate= _clks[] __initconst =3D { }; =20 static const struct samsung_cmu_info top_cmu_info __initconst =3D { - .pll_clks =3D cmu_top_pll_clks, - .nr_pll_clks =3D ARRAY_SIZE(cmu_top_pll_clks), - .mux_clks =3D cmu_top_mux_clks, - .nr_mux_clks =3D ARRAY_SIZE(cmu_top_mux_clks), - .div_clks =3D cmu_top_div_clks, - .nr_div_clks =3D ARRAY_SIZE(cmu_top_div_clks), - .fixed_factor_clks =3D cmu_top_ffactor, - .nr_fixed_factor_clks =3D ARRAY_SIZE(cmu_top_ffactor), - .gate_clks =3D cmu_top_gate_clks, - .nr_gate_clks =3D ARRAY_SIZE(cmu_top_gate_clks), + .pll_clks =3D top_pll_clks, + .nr_pll_clks =3D ARRAY_SIZE(top_pll_clks), + .mux_clks =3D top_mux_clks, + .nr_mux_clks =3D ARRAY_SIZE(top_mux_clks), + .div_clks =3D top_div_clks, + .nr_div_clks =3D ARRAY_SIZE(top_div_clks), + .fixed_factor_clks =3D top_ffactor_clks, + .nr_fixed_factor_clks =3D ARRAY_SIZE(top_ffactor_clks), + .gate_clks =3D top_gate_clks, + .nr_gate_clks =3D ARRAY_SIZE(top_gate_clks), .nr_clk_ids =3D CLKS_NR_TOP, - .clk_regs =3D cmu_top_clk_regs, - .nr_clk_regs =3D ARRAY_SIZE(cmu_top_clk_regs), + .clk_regs =3D top_clk_regs, + .nr_clk_regs =3D ARRAY_SIZE(top_clk_regs), .auto_clock_gate =3D true, .gate_dbg_offset =3D GS101_GATE_DBG_OFFSET, .option_offset =3D CMU_CMU_TOP_CONTROLLER_OPTION, @@ -2434,15 +2434,15 @@ PNAME(mout_hsi0_usb31drd_p) =3D { "fout_usb_pll", "dout_hsi0_usb31drd", "fout_usb_pll" }; =20 -static const struct samsung_pll_rate_table cmu_hsi0_usb_pll_rates[] __init= const =3D { +static const struct samsung_pll_rate_table hsi0_usb_pll_rates[] __initcons= t =3D { PLL_35XX_RATE(24576000, 19200000, 150, 6, 5), { /* sentinel */ } }; =20 -static const struct samsung_pll_clock cmu_hsi0_pll_clks[] __initconst =3D { +static const struct samsung_pll_clock hsi0_pll_clks[] __initconst =3D { PLL(pll_0518x, CLK_FOUT_USB_PLL, "fout_usb_pll", "oscclk", PLL_LOCKTIME_PLL_USB, PLL_CON3_PLL_USB, - cmu_hsi0_usb_pll_rates), + hsi0_usb_pll_rates), }; =20 static const struct samsung_mux_clock hsi0_mux_clks[] __initconst =3D { @@ -2660,8 +2660,8 @@ static const struct samsung_fixed_rate_clock hsi0_fix= ed_clks[] __initconst =3D { }; =20 static const struct samsung_cmu_info hsi0_cmu_info __initconst =3D { - .pll_clks =3D cmu_hsi0_pll_clks, - .nr_pll_clks =3D ARRAY_SIZE(cmu_hsi0_pll_clks), + .pll_clks =3D hsi0_pll_clks, + .nr_pll_clks =3D ARRAY_SIZE(hsi0_pll_clks), .mux_clks =3D hsi0_mux_clks, .nr_mux_clks =3D ARRAY_SIZE(hsi0_mux_clks), .div_clks =3D hsi0_div_clks, @@ -2791,7 +2791,7 @@ static const struct samsung_cmu_info hsi0_cmu_info __= initconst =3D { #define QCH_CON_UFS_EMBD_QCH_FMP 0x3094 #define QUEUE_CTRL_REG_BLK_HSI2_CMU_HSI2 0x3c00 =20 -static const unsigned long cmu_hsi2_clk_regs[] __initconst =3D { +static const unsigned long hsi2_clk_regs[] __initconst =3D { PLL_CON0_MUX_CLKCMU_HSI2_BUS_USER, PLL_CON1_MUX_CLKCMU_HSI2_BUS_USER, PLL_CON0_MUX_CLKCMU_HSI2_MMC_CARD_USER, @@ -3166,8 +3166,8 @@ static const struct samsung_cmu_info hsi2_cmu_info __= initconst =3D { .gate_clks =3D hsi2_gate_clks, .nr_gate_clks =3D ARRAY_SIZE(hsi2_gate_clks), .nr_clk_ids =3D CLKS_NR_HSI2, - .clk_regs =3D cmu_hsi2_clk_regs, - .nr_clk_regs =3D ARRAY_SIZE(cmu_hsi2_clk_regs), + .clk_regs =3D hsi2_clk_regs, + .nr_clk_regs =3D ARRAY_SIZE(hsi2_clk_regs), .sysreg_clk_regs =3D dcrg_memclk_sysreg, .nr_sysreg_clk_regs =3D ARRAY_SIZE(dcrg_memclk_sysreg), .clk_name =3D "bus", --- base-commit: 9845cf73f7db6094c0d8419d6adb848028f4a921 change-id: 20260123-clk-gs101-symbol-names-07748885ccab Best regards, --=20 Andr=C3=A9 Draszik